Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C16/4582—Rigid and flat substrates, e.g. plates or discs
  • C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
  • C23C16/4585—Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/02—Elements
  • C30B29/06—Silicon
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02381—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/02433—Crystal orientation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02656—Special treatments
  • H01L21/02658—Pretreatments

Definitions

• the present invention relates to a semiconductor wafer of monocrystalline silicon, having a substrate wafer of monocrystalline silicon and a layer of monocrystalline silicon that lies atop the substrate wafer, which is referred to hereinafter as semiconductor wafer of silicon with epitaxial layer (silicon epitaxial wafer).
• the production of semiconductor wafers of silicon with an epitaxial layer includes the deposition of the epitaxial layer on a substrate wafer by means of gas phase deposition (e.g., chemical vapor deposition, CVD).
• gas phase deposition e.g., chemical vapor deposition, CVD
• a particularly suitable CVD is one conducted in a single-wafer reactor under standard pressure (atmospheric pressure).
• US Patent Application Publication No. 2007/0227441 A1 points out periodic variations in the thickness of the epitaxial layer in the edge region of such semiconductor wafers of silicon. The reason is different growth rates at which the epitaxial layer grows. The different growth rates are correlated with the crystal orientation of the semiconductor wafer. In order to homogenize the thickness of the epitaxial layer in the edge region, US Patent Application Publication No. 2007/0227441 A1 proposes altering the structure of the susceptor by the period of the thickness variations.
• a semiconductor wafer of monocrystalline silicon having: a substrate wafer of monocrystalline silicon; and a layer of monocrystalline silicon that lies on a front side of the substrate wafer.
• the substrate wafer has a crystal orientation.
• An averaged front side-based ZDD of the semiconductor wafer with a division of a surface of an epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than ⁇ 30 nm/mm 2 and not more than 0 nm/mm 2 .
• An ESFQR max of the semiconductor wafer, with an edge exclusion of 1 mm and 72 sectors each with a length of 30 mm, is at most 10 nm.
• An embodiment of the present invention provides a semiconductor wafer of monocrystalline silicon.
• the semiconductor wafer includes a substrate wafer of monocrystalline silicon and a layer of monocrystalline silicon that lies on a front side of the substrate wafer.
• the substrate wafer has a crystal orientation.
• An averaged front side-based ZDD (double derivative of height Z) of the semiconductor wafer, with a division of the surface of the epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than ⁇ 30 nm/mm 2 and not more than 0 nm/mm 2 .
• the ESFQR max maximum edge site front least-squares range) of the semiconductor wafer, with an edge exclusion of 1 mm and 72 sectors each with a length of 30 mm, is at most 10 nm.
• ZDD and ESFQR are parameters that characterize the edge geometry of a semiconductor wafer, which are also addressed by SEMI standards (ZDD (SEMI M68-1015), ESFQR (SEMI M67-1015)).
• Front side-based ZDD describes the average near-edge curvature of the surface.
• ESFQR max denotes the ESFQR of that sector in which ESFQR is at its greatest.
• a semiconductor wafer of the present invention with an epitaxial layer shows virtually no angle-dependent variations in the edge geometry of the epitaxial layer, because the production thereof envisages preventing such variations from occurring.
• the epitaxial layer covers virtually only the main surface of the front side of the substrate layer that determines the crystal orientation of the substrate wafer and virtually no regions of the front side that have a different crystal orientation, because an oxide layer provided at the edge of the substrate layer largely prevents the epitaxial layer from being deposited in such regions.
• the edge geometry of the semiconductor wafer with an epitaxial layer is not less than ⁇ 30 nm/mm 2 and not more than 0 nm/mm 2 .
• the oxide layer on the back side additionally prevents material from being deposited on the back side while an epitaxial layer is being deposited on the front side, hence worsening the ESFQR. Therefore, the ESFQR max of the semiconductor wafer is at most 10 nm, with an edge exclusion of 1 mm and 72 sectors each having a length of 30 mm.
• the diameter of a semiconductor wafer of the present invention is preferably not less than 300 mm, more preferably 300 mm.
• the region of the edge and the back side of the substrate wafer is masked with an oxide layer, and the CMP (chemical mechanical polishing) step creates a mirror-polished front side of the substrate wafer consisting (for the most part) of a main surface with uniform crystal orientation.
• the crystal orientation of the main surface of the front side of the substrate wafer is preferably a ⁇ 100 ⁇ orientation or a ⁇ 110 ⁇ orientation.
• the epitaxial layer is subsequently deposited on the front side. There is now barely any occurrence of angle-dependent variations in the thickness of the epitaxial layer. Such variations originate from the deposition of the epitaxial layer on surfaces with different crystal orientation and at different deposition rates associated therewith.
• the presence of the oxide layer prevents deposition of an epitaxial layer thereon.
• Asymmetric double-sided polishing here means double-sided polishing in which material is removed more quickly on the front side than on the back side, and at the end of which the oxide layer has been completely polished away from the front side, while it is still present on the back side.
• EP 0 857 542 A1 describes how asymmetric removal of material can be brought about.
• the oxide layer is a layer of silicon dioxide and is preferably produced by means of CVD, more preferably by means of AP-CVD (atmospheric pressure CVD). Alternatively, the oxide layer can also be produced by means of LP-CVD (low pressure CVD) or thermally.
• the oxide layer preferably has a thickness of not less than 5 nm and not more than 100 nm.
• the substrate wafer is at first fully covered by the oxide layer. Subsequently, the substrate wafer is subjected to asymmetric DSP polishing, in the course of which the oxide layer on the front side of the substrate wafer is removed, but the oxide is conserved on the back side and in the region of the edge. This is followed by single-sided CMP polishing of the front side of the substrate wafer. The result of this procedure is that no oxide layer is present any longer in the CMP-polished regions of the substrate wafer.
• the epitaxial layer is deposited on the front side of the substrate wafer, which is free of the oxide layer. Native oxide may be removed prior to the deposition of the epitaxial layer by a treatment of the front side with hydrogen (H 2 bake).
• the substrate wafer lies on the susceptor of a CVD reactor such that the front side is exposed to the deposition gas. Since the crystal orientation of the front side is virtually uniform and is preferably a ⁇ 100 ⁇ crystal orientation or a ⁇ 110 ⁇ crystal orientation, the epitaxial layer grows with a virtually uniform deposition rate on the front side of the substrate wafer. Accordingly, the thickness of the epitaxial layer is essentially uniform. Angle-dependent variation in the thickness of the epitaxial layer in the edge region is virtually undetectable because the oxide layer is a barrier to epitaxial deposition in the edge region that is the cause thereof.
• the thickness of the epitaxial layer of silicon is preferably 1 to 15 ⁇ m, more preferably 1 to 7 ⁇ m.
• the deposition temperature is preferably in the range from 900° C. to 1250° C.
• the deposition gas contains a silane, preferably trichlorosilane, as silicon source and hydrogen.
• the oxide layer is removed, preferably by a wet-chemical route by means of a chemical containing hydrogen fluoride and optionally hydrogen chloride and/or ammonium fluoride.
• concentration of hydrogen fluoride is preferably 0.2% by weight to 49% by weight.
• the wet-chemical step may be part of a cleaning sequence, in the course of which the semiconductor wafer is treated with further chemicals, for example with ozone water and/or with SC1 solution.
• the oxide layer can also be removed under dry conditions, for example by means of plasma etching or reactive ion etching (RIE).
• a substrate wafer of monocrystalline silicon having a diameter of 300 mm and ⁇ 100 ⁇ orientation of the front side was fully coated with an oxide layer in a CVD reactor. Thereafter, the substrate wafer was subjected first to polishing by means of DSP (with a hard (more material-removing) polishing cloth on the front side and a soft (less material-removing) polishing cloth on the back side) and then to polishing of the front side by means of CMP, and cleaned.
• DSP with a hard (more material-removing) polishing cloth on the front side and a soft (less material-removing) polishing cloth on the back side
• the oxide layer was removed from the edge and the back side of the resultant epitaxially coated semiconductor wafer in a bath that contained hydrogen fluoride.
• the semiconductor wafer was cleaned and dried and subjected to a measurement of edge geometry.
• edge geometry With an edge exclusion of 1 mm and a division of the epitaxial layer into 16 sectors, the average front side-based ZDD, measured with a KLA-Tencor Wafersight instrument, was ⁇ 27 nm/mm 2 ; the ESFQR max was 8 nm with an edge exclusion of 1 mm and 72 sectors each with length 30 mm.
• a further substrate wafer of monocrystalline silicon having the properties of that from the example was coated as in the example with an epitaxial layer of monocrystalline silicon.
• production of the oxide layer was omitted. Omitting this had a clear adverse effect on the edge geometry of the resultant semiconductor wafer: the corresponding front side-based average ZDD had a value of ⁇ 120 nm/mm2 and a corresponding ESFQR max of 23 nm.
• the recitation of “at least one of A, B and C” should be interpreted as one or more of a group of elements consisting of A, B and C, and should not be interpreted as requiring at least one of each of the listed elements A, B and C, regardless of whether A, B and C are related as categories or otherwise.
• the recitation of “A, B and/or C” or “at least one of A, B or C” should be interpreted as including any singular entity from the listed elements, e.g., A, any subset from the listed elements, e.g., A and B, or the entire list of elements A, B and C.

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• 2018
  • 2018-01-11 DE DE102018200415.3A patent/DE102018200415A1/de active Pending
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