US10868037B2 - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device Download PDF

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Publication number
US10868037B2
US10868037B2 US16/502,877 US201916502877A US10868037B2 US 10868037 B2 US10868037 B2 US 10868037B2 US 201916502877 A US201916502877 A US 201916502877A US 10868037 B2 US10868037 B2 US 10868037B2
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layer
interconnecting
interconnecting layer
signal line
voltage
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US20200303400A1 (en
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Fumitaka Arai
Masakazu Goto
Masaki Kondo
Keiji Hosotani
Nobuyuki Momo
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Kioxia Corp
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Toshiba Memory Corp
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    • H01L27/11582—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H01L27/1157—
    • H01L27/11573—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • H01L27/11565—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

Definitions

  • Embodiments described herein relate generally to a semiconductor memory device.
  • An ideal memory device is a high speed, high storage density and low bit cost non-volatile semiconductor memory device. At present, there is no memory device that meets all the requirements, and thus a memory device suitable for the application is provided to the user.
  • FIG. 1 is a general view of a semiconductor memory device according to a first embodiment
  • FIG. 2 is a circuit diagram of a memory cell array provided in the semiconductor memory device according to the first embodiment
  • FIG. 3 is a cross-sectional view of a memory cell array and a readout circuit unit included in the semiconductor memory device according to the first embodiment
  • FIG. 4 is a plan view of a memory cell array and a readout circuit unit included in the semiconductor memory device according to the first embodiment
  • FIG. 5 is a diagram illustrating a writing operation of the semiconductor memory device according to the first embodiment
  • FIG. 6 is a diagram illustrating a reading operation of the semiconductor memory device according to the first embodiment
  • FIGS. 7 to 22 are views illustrating manufacturing processes of a memory cell array and a readout circuit unit included in a semiconductor memory device according to a first example of a second embodiment
  • FIGS. 23 to 31 are views illustrating manufacturing processes of a memory cell array and a readout circuit unit included in a semiconductor memory device according to a second example of the second embodiment
  • FIG. 32 is a plan view of a memory cell array and a readout circuit unit included in the semiconductor memory device according to a third embodiment
  • FIG. 33 is a cross-sectional view of the memory cell array and the readout circuit unit included in a semiconductor memory device according to the third embodiment
  • FIG. 34 is a cross-sectional view of a memory cell array and a readout circuit unit included in a semiconductor memory device according to a fourth embodiment
  • FIG. 35 is a diagram illustrating a writing operation of the semiconductor memory device according to the fourth embodiment.
  • FIG. 36 illustrates a “1” reading operation of the semiconductor memory device according to the fourth embodiment
  • FIG. 37 illustrates a “0” reading operation of the semiconductor memory device according to the fourth embodiment
  • FIG. 38 is a circuit diagram of a memory cell array provided in a semiconductor memory device according to a fifth embodiment.
  • FIG. 39 is a cross-sectional view of the memory cell array and the readout circuit unit included in the semiconductor memory device according to the fifth embodiment.
  • FIG. 40 is a plan view of the memory cell array and the readout circuit unit included in the semiconductor memory device according to the fifth embodiment.
  • FIG. 41 is a diagram illustrating a writing operation of the semiconductor memory device according to the fifth embodiment.
  • FIG. 42 is a diagram illustrating the reading operation of the semiconductor memory device according to a first example of the fifth embodiment
  • FIG. 43 is a diagram illustrating a reading operation of a semiconductor memory device according to a second example of the fifth embodiment.
  • FIG. 44 is a cross-sectional view of a memory cell array and a readout circuit unit included in a semiconductor memory device according to a sixth embodiment.
  • FIG. 45 is a plan view of the memory cell array and the readout circuit unit included in the semiconductor memory device according to the sixth embodiment.
  • a semiconductor memory device includes: a first interconnecting layer extending in a first direction; a first signal line extending in a second direction intersecting the first direction and perpendicular to a substrate; a first memory cell that stores first information between the first interconnecting layer and the first signal line; a second interconnecting layer provided above the first interconnecting layer and extending in the first direction; a third interconnecting layer provided above the second interconnecting layer and extending in the first direction; a fourth interconnecting layer provided above the third interconnecting layer and extending in the first direction; a fifth interconnecting layer disposed apart from the second interconnecting layer in a third direction intersecting the first and second directions and extending in the first direction; a sixth interconnecting layer disposed apart from the third interconnecting layer in the third direction and extending in the first direction; a seventh interconnecting layer disposed apart from the fourth interconnecting layer in the third direction and extending in the first direction; a second signal line provided above the first signal line,
  • a semiconductor memory device according to a first embodiment will be described.
  • a case of using a three-dimensionally stacked NAND flash memory as a semiconductor memory device will be described.
  • FIG. 1 First, an example of a general configuration of a semiconductor memory device 1 will be described with reference to FIG. 1 . It should be noted that in the example of FIG. 1 , although parts of coupling among blocks are indicated by arrow lines, the coupling between the blocks is not limited thereto.
  • the semiconductor memory device 1 includes an input/output circuit 10 , a logic controller 11 , a status register 12 , an address register 13 , a command register 14 , a sequencer 15 , a ready/busy circuit 16 , a voltage generator 17 , a memory cell array 18 , a row decoder 19 , a readout circuit 20 , a sense amplifier 21 , a data register 22 , and a column decoder 23 .
  • the input/output circuit 10 controls the input/output of a signal DQ with an external controller 2 .
  • the signal DQ includes, for example, data DAT, an address ADD, and a command CMD. More specifically, the input/output circuit 10 transmits the data DAT received from the external controller 2 to the data register 22 , transmits the address ADD to the address register 13 , and transmits the command CMD to the command register 14 . Further, the input/output circuit 10 transmits the status information STS received from the status register 12 , the data DAT received from the data register 22 , the address ADD received from the address register 13 and the like to the external controller 2 .
  • the logic controller 11 receives various control signals from the external controller 2 . Then, the logic controller 11 controls the input/output circuit 10 and the sequencer 15 in accordance with the received control signals.
  • the status register 12 temporarily holds status information STS in, for example, a writing operation, a reading operation, and an erasing operation, and notifies the external controller 2 whether the operation has terminated normally.
  • the address register 13 temporarily holds the received address ADD. Then, the address register 13 transfers a row address RADD to the row decoder 19 and transfers a column address CADD to the column decoder 23 .
  • the command register 14 temporarily stores the received command CMD and transfers it to the sequencer 15 .
  • the sequencer 15 controls the general operation of the semiconductor memory device 1 . More specifically, the sequencer 15 , in accordance with the received command CMD, controls for example, the status register 12 , the ready/busy circuit 16 , the voltage generator 17 , the row decoder 19 , the readout circuit 20 , the sense amplifier 21 , the data register 22 , and the column decoder 23 and the like, and executes a writing operation, a reading operation, an erasing operation, and the like.
  • the ready/busy circuit 16 transmits a ready/busy signal RBn to the external controller 2 in accordance with the operating state of the sequencer 15 .
  • the voltage generator 17 in accordance with control of the sequencer 15 , generates voltages required for the writing operation, the reading operation, and the erasing operation, and supplies the generated voltages as, for example, to the memory cell array 18 , the row decoder 19 , the sense amplifier 21 , and the data register 22 and the column decoder 23 and the like.
  • the row decoder 19 applies the voltage supplied from the voltage generator 17 to the readout circuit 20 and memory cell transistors in the memory cell array 18 .
  • the sense amplifier 21 applies the voltage supplied from the voltage generator 17 to the readout circuit 20 and the memory cell transistor in the memory cell array 18 via the readout circuit 20 .
  • the memory cell array 18 includes a plurality of blocks BLK (BLK 0 , BLK 1 , BLK 2 , . . . ) including a plurality of non-volatile memory cell transistors (hereinafter also referred to as “memory cells”) associated with rows and columns.
  • Each block BLK includes a plurality of (four in the present embodiment) string units SU (SU 0 to SU 3 ) which are a set of NAND strings NS in which memory cell transistors are coupled in series. It should be noted that the number of blocks BLK, the string units SU, and NAND strings NS in the memory cell array 18 may be selected as desired. Details of the memory cell array 18 will be described later.
  • the row decoder 19 decodes the row address RADD.
  • the row decoder 19 applies required voltages to the memory cell array 18 based on a decoded result.
  • the readout circuit 20 supplies the voltage applied from the sense amplifier 21 to the memory cell array 18 in the writing operation. Further, in the case of the reading operation, the readout circuit 20 switches the coupling with the sense amplifier 21 in accordance with the data read from the memory cell array 18 .
  • the readout circuit 20 includes a plurality of readout circuit units corresponding to the plurality of NAND strings NS. Details of the readout circuit unit will be described later.
  • the sense amplifier 21 senses data in accordance with the coupled state with the readout circuit 20 in the reading operation. In other words, the sense amplifier 21 reads data from the memory cell array 18 via the readout circuit 20 . Then, the sense amplifier 21 transmits the read data to the data register 22 . The sense amplifier 21 transmits writing data to the memory cell array 18 via the readout circuit 20 during the writing operation.
  • the data register 22 includes a plurality of latch circuits (not illustrated).
  • the latch circuits temporarily hold writing data or read data.
  • the column decoder 23 decodes the column address CADD, for example, during the writing operation, the reading operation, and the erasing operation, and selects the latch circuit in the data register 22 in accordance with the decoded result.
  • FIG. 2 illustrates a block BLK 0 , but the configurations of the other blocks BLK are also the same.
  • the block BLK 0 includes a plurality of string units SU.
  • Each of the string units SU includes a plurality of NAND strings NS.
  • Each of the NAND strings NS includes, for example, five memory cell transistors MC (MC 0 to MC 4 ) and selection transistors ST 1 and ST 2 .
  • the memory cell transistor MC includes a control gate and a charge storage layer, and holds data in a non-volatile manner.
  • a memory cell transistor MC when one of the memory cell transistors MC 0 to MC 4 is not limited, it is referred to as a memory cell transistor MC.
  • the memory cell transistor MC may be a MONOS type using an insulating film as the charge storage layer, or may be an FG type using a conductive layer as the charge storage layer.
  • the MONOS type will be described as an example.
  • the number of memory cell transistors MC is not limited to five, and may be eight, sixteen, thirty-two, sixty-four, ninety-six, one-hundred twenty-eight, etc., and the number is not limited.
  • one or more selection transistors ST 1 and ST 2 may be provided in each of the NAND strings NS.
  • respective current paths are coupled in series to the selection transistor ST 2 , the memory cell transistors MC 0 to MC 4 , and the selection transistor ST 1 in this order.
  • a drain of the selection transistor ST 1 is coupled to a corresponding readout circuit unit RCU.
  • a source of the selection transistor ST 2 is coupled to a source line SL.
  • Control gates of the memory cell transistors MC 0 to MC 4 of the NAND strings NS in the same block BLK are commonly coupled to different word lines WL 0 to WL 4 , respectively. More specifically, for example, control gates of a plurality of memory cell transistors MC 0 in block BLK 0 are commonly coupled to word line WL 0 .
  • the word lines WL 0 to WL 4 are coupled to the row decoder 19 .
  • the gates of the plurality of selection transistors ST 1 in the same string unit SU are commonly coupled to a selection gate line SGD. More specifically, the gates of selection transistors ST 1 in the string unit SU 0 are commonly coupled to a selection gate line SGD 0 . The gates of the selection transistors ST 1 in the string unit SU 1 are commonly coupled to a selection gate line SGD 1 .
  • the selection gate line SGD is coupled to the row decoder 19 .
  • the gates of the plurality of selection transistors ST 2 in the block BLK are commonly coupled to a selection gate line SGS.
  • the selection gate line SGS is coupled to the row decoder 19 . It should be noted that the gates of the selection transistors ST 2 may be coupled to different selection gate lines SGS for each of the string units SU.
  • the drains of the plurality of selection transistors ST 1 in the block BLK are coupled to different readout circuit units RCU.
  • the plurality of readout circuit units RCU corresponding to one string unit SU are commonly coupled to, for example, a cell source line CSL.
  • the plurality of readout circuit units RCU corresponding to one string unit SU are coupled to different bit lines BL (BL 0 to BL (N ⁇ 1), where N is a natural number of 2 or higher).
  • the plurality of NAND strings NS in the string unit SU are coupled to different bit lines BL via different readout circuit units RCU.
  • the bit lines BL are coupled to the sense amplifier 21 .
  • one NAND string NS of each string unit SU in the block BLK is commonly coupled to one bit line BL via the corresponding readout circuit unit RCU.
  • the sources of the selection transistors ST 2 in the plurality of blocks BLK are commonly coupled to the source line SL.
  • the string unit SU is a set of NAND strings NS each coupled to different bit lines BL via different readout circuit units RCU and coupled to the same selection gate line SGD.
  • the block BLK is a set of a plurality of string units SU sharing the word lines WL.
  • the memory cell array 18 is a set of a plurality of blocks BLK sharing the bit line BL.
  • an insulating layer 31 is formed on a semiconductor substrate 30 .
  • a silicon oxide film SiO 2
  • a circuit such as the row decoder 19 or the sense amplifier 21 may be provided in a region where the insulating layer 31 is formed, that is, between the semiconductor substrate 30 and an interconnecting layer 32 .
  • the interconnecting layer 32 functioning as a source line SL is formed on the insulating layer 31 .
  • the interconnecting layer 32 is made of a conductive material.
  • As the interconnecting layer 32 for example, an n-type semiconductor, a p-type semiconductor, or a metal material is used.
  • interconnecting layer 32 seven layers of interconnecting layers 33 functioning as the selection gate line SGS, the word lines WL 0 to WL 4 , and the selection gate line SGD are layered from the lower layer separately in a Z direction perpendicular to the semiconductor substrate 30 .
  • the interconnecting layers 33 extend in the X direction which is parallel to the semiconductor substrate 30 and intersects the Z direction.
  • the interconnecting layers 33 are made of a conductive material.
  • an n-type semiconductor, a p-type semiconductor, or a metal material is used as the interconnecting layers 33 .
  • TiN has a function as a barrier layer for preventing a reaction between W and SiO 2 when depositing W by, for example, chemical vapor deposition (CVD), or an adhesion layer for improving the adhesion of W.
  • a memory pillar MP whose bottom surface reaches the interconnecting layer 32 through the seven interconnecting layers 33 is formed.
  • One memory pillar MP corresponds to one NAND string NS.
  • the memory pillar MP includes a block insulating film 34 , a charge storage layer 35 , a tunnel insulating film 36 , a semiconductor layer 37 , a core layer 38 , and a cap layer 39 .
  • a hole corresponding to the memory pillar MP is formed so that the bottom surface reaches the interconnecting layer 32 through the interconnecting layers 33 .
  • the block insulating film 34 , the charge storage layer 35 , and the tunnel insulating film 36 are sequentially layered on the side surfaces of the holes.
  • the semiconductor layer 37 is formed such that the side surface is in contact with the tunnel insulating film 36 and the bottom surface is in contact with the interconnecting layer 32 .
  • the semiconductor layer 37 is a region in which the channels of the selection transistor ST 2 , the memory cell transistors MC 0 to MC 4 , and the selection transistor ST 1 are formed.
  • the semiconductor layer 37 functions as a signal line that couples current paths of the selection transistor ST 2 , the memory cell transistors MC 0 to MC 4 , and the selection transistor ST 1 . Further, in the memory pillar MP, the core layer 38 whose side surface and bottom surface are in contact with the semiconductor layer 37 is provided. On the semiconductor layer 37 and the core layer 38 , the cap layer 39 whose side surface is in contact with the tunnel insulating film 36 is formed.
  • the insulating material is used as the block insulating film 34 .
  • the insulating material may be, for example, a layered structure of Hf (Si) Ox/SiO 2 /Hf (Si) Ox using hafnium (Hf) and SiO 2 , or may be SiO 2 .
  • Hf (Si) Ox may or may not contain Si in HfOx.
  • a silicon nitride film (SiN) is used as the charge storage layer 35 .
  • SiO 2 or silicon oxynitride (SiON) is used as the tunnel insulating film 36 .
  • polysilicon is used as the semiconductor layer 37 and the cap layer 39 .
  • SiO 2 is used as the core layer 38 .
  • the memory pillar MP and five interconnecting layers 33 functioning respectively as word lines WL 0 to WL 4 constitute the memory cell transistors MC 0 to MC 4 , respectively.
  • the memory pillar MP and the interconnecting layers 33 functioning as the selection gate line SGD constitute the selection transistor ST 1 .
  • the memory pillar MP and the interconnecting layer 33 functioning as the selection gate line SGS constitute the selection transistor ST 2 .
  • a semiconductor layer 40 is formed on the cap layer 39 .
  • the readout circuit unit RCU is formed on the semiconductor layer 40 .
  • polysilicon is used as the semiconductor layer 40 .
  • the cap layer 39 may be omitted.
  • the readout circuit unit RCU includes, for example, five transistors TR (TR 0 a , TR 1 a , TR 2 a , TR 0 b , and TR 2 b ).
  • the transistors TR 0 a , TR 1 a , and TR 2 a are stacked above the semiconductor layer 40 , and their current paths are coupled in series.
  • the transistors TR 0 b and TR 2 b are stacked above the semiconductor layer 40 , and their current paths are coupled in series.
  • the transistors TR 0 a , TR 1 a , and TR 2 a are provided on the right side of the drawing, and the transistors TR 0 b and TR 2 b are provided on the left side of the drawing.
  • the sources of the transistors TR 0 a and TR 0 b are coupled to the semiconductor layer 40 .
  • the drains of the transistors TR 2 a and TR 2 b are coupled to a conductive layer 47 provided on the readout circuit unit RCU.
  • the source of the transistor TR 2 b and the drain of the transistor TR 0 b are coupled to the cell source line CSL.
  • the cell source line CSL is coupled to, for example, the row decoder 19 .
  • the gates of the transistors TR 0 a , TR 1 a , TR 2 a , TR 0 b , and TR 2 b are coupled to selection gate lines SG 0 a , SG 1 a , SG 2 a , SG 0 b , and SG 2 b , respectively.
  • the selection gate lines SG 0 a , SG 1 a , SG 2 a , SG 0 b , and SG 2 b are coupled to the row decoder 19 .
  • the selection gate lines SG 0 a and SG 0 b are formed in the same layer.
  • the cell source line CSL and a selection gate line SG 1 a are formed in the same layer.
  • the selection gate lines SG 2 a and SG 2 b are formed in the same layer.
  • the interconnecting layers 41 to 43 extending in the X direction are separately layered in the Z direction.
  • the interconnecting layers 41 to 43 are made of a conductive material.
  • a p-type semiconductor, a metal material, or the like is used as the interconnecting layers 41 and 43 .
  • an n-type semiconductor is used as the interconnecting layer 42 .
  • a readout circuit unit RCU which penetrates the interconnecting layers 41 to 43 and whose bottom surface is in contact with the semiconductor layer 40 is formed.
  • the readout circuit unit RCU separates the interconnecting layers 41 to 43 in the Y direction.
  • the interconnecting layers 41 to 43 formed on the right side of the drawing with respect to the readout circuit unit RCU function as the selection gate lines SG 0 a , SG 1 a , and SG 2 a , respectively.
  • the interconnecting layers 41 to 43 formed on the left side of the drawing with respect to the readout circuit unit RCU function as the selection gate line SG 0 b , the cell source line CSL, and the selection gate line SG 2 b.
  • the readout circuit unit RCU includes, for example, an insulating layer 44 , a semiconductor layer 45 , and an insulating layer 46 . More specifically, a trench RT corresponding to the readout circuit unit RCU is formed extending in the X direction, and the insulating layer 44 is formed on a side surface of the trench RT.
  • the insulating layer 44 functions as a gate insulating film of the transistors TR 0 a , TR 1 a , TR 2 a , TR 0 b , and TR 2 b .
  • the semiconductor layer 45 is formed with the side surface in contact with the insulating layer 44 and the bottom surface in contact with the semiconductor layer 40 .
  • the semiconductor layer 45 is a region in which channels of the transistors TR 0 a , TR 1 a , TR 2 a , TR 0 b , and TR 2 b are formed.
  • the semiconductor layer 45 functions as a signal line coupling in series the current paths of the transistors TR 0 a , TR 1 a and TR 2 a , and a signal line coupling in series the current paths of the transistors TR 0 b and TR 2 b .
  • the portion excluding the vicinity of the bottom of the semiconductor layer 45 (at least a portion upward of the bottom surface of the interconnecting layer 41 ) is separated into two parts in the X direction by the insulating layer 46 .
  • the material of the insulating layers 44 and 46 is selected from SiO 2 , SiN, SiON, a high dielectric constant material (for example, aluminum oxide, hafnium oxide or zirconium oxide) or the like.
  • the insulating layers 44 and 46 may be a mixture film or a laminated film of these materials.
  • SiO 2 is used as the insulating layers 44 and 46 will be described.
  • the semiconductor layer 45 is selected from, for example, polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe), an oxide semiconductor, and a two-dimensional semiconductor material (for example, MoS 2 or WSe 2 ). It should be noted that a laminated film including at least two of films made of these materials, for example, a laminated film of silicon and germanium, or a laminated film of a plurality of two-dimensional semiconductor materials may be used for the semiconductor layer 45 .
  • the material of the oxide semiconductor include an oxide such as indium (In), gallium (Ga), zinc (Zn), tin (Sn), and a mixture (compound) of these oxides.
  • the material of the oxide semiconductor is InGaZnO, InGaSnO, or the like.
  • a band gap of the oxide semiconductor is approximately three times larger than the band gap of silicon.
  • the band gap of InGaZnO is about 3.5 eV. Therefore, the leak of electrons due to interband tunneling between the conduction band and the valence band in the oxide semiconductor is negligible. Therefore, for example, when the transistors TR 0 a and TR 2 a are in an OFF state, the charge of the transistor TR 1 a is held in the semiconductor layer 45 (oxide semiconductor) and is not released to the memory pillar MP or the bit line BL.
  • interconnecting layers 41 to 43 functioning as selection gate lines SG 0 a , SG 1 a , SG 2 a , SG 0 b , and SG 2 b are not in contact with semiconductor layer 45 , but interconnecting layer 42 functioning as cell source line CSL is in contact with semiconductor layer 45 .
  • a conductive layer 47 is formed on the semiconductor layer 45 and the insulating layer 46 .
  • Conductive layer 47 is electrically coupled to the bit line BL.
  • the conductive layer 47 is made of a conductive material.
  • an n-type semiconductor is used as the conductive layer 47 .
  • the semiconductor layer 37 of the memory pillar MP and the semiconductor layer 45 of the readout circuit unit RCU are coupled via the semiconductor layer 40 (and the cap layer 39 ). Therefore, for example, the Y-direction diameter of the semiconductor layer 37 and the Y-direction width of the semiconductor layer 45 may be the same or different.
  • FIG. 4 illustrates the upper surfaces of the selection gate lines SG 0 a and SG 0 b and the upper surface of the word line WL 4 in the XY plane parallel to the semiconductor substrate 30 .
  • WL 4 plane the upper surface of the word line WL 4 (hereinafter, referred to as “WL 4 plane”) will be described.
  • memory pillars MP penetrating through the word line WL 4 are staggered in two rows in the X direction.
  • the block insulating film 34 , the charge storage layer 35 , the tunnel insulating film 36 , and the semiconductor layer 37 are sequentially layered on the side surface of the memory pillar MP, and the core layer 38 is formed inside the semiconductor layer 37 .
  • the region including the word line WL 4 and the memory pillar MP constitutes the memory cell transistor MC 4 .
  • the selection gate lines SG 0 a (interconnecting layer 41 ) and the selection gate lines SG 0 b (interconnecting layer 41 ) extending in the X direction are spaced apart from each other in the Y direction and alternately arranged. Between the selection gate lines SG 0 a and SG 0 b , a plurality of readout circuit units RCU and a plurality of holes AH are alternately arranged along the X direction.
  • the readout circuit unit RCU is formed above the memory pillar MP.
  • the insulating layers 44 are respectively formed on the two side surfaces of the trench RT corresponding to the readout circuit unit RCU in the Y direction.
  • a region including the selection gate line SG 0 a and the insulating layer 44 and the semiconductor layer 45 formed on the side surface of the trench RT facing the selection gate line SG 0 a constitutes the transistor TR 0 a .
  • a region including selection gate line SG 0 b and insulating layer 44 and semiconductor layer 45 formed on the side surface of trench RT facing selection gate line SG 0 b constitutes the transistor TR 0 b.
  • the holes AH are provided to separate the readout circuit unit RCU in the X direction. Therefore, the length (width) of the hole AH in the Y direction is longer than the length (width) of the trench RT in the Y direction, that is, of the readout circuit unit RCU.
  • the inside of the hole AH is filled with the insulating layer 48 .
  • SiO 2 is used as the insulating layer 48 .
  • FIG. 5 illustrates an example of the voltage of each interconnect during the writing operation.
  • the writing operation is an operation of raising the threshold voltage of the memory cell transistor MC (or maintaining the threshold voltage by inhibiting the injection) by injecting charges into the charge storage layer 35 .
  • Data is allocated to memory cell transistor MC in accordance with the level of the threshold voltage.
  • the memory cell transistor MC can hold 1-bit data, and a state where the threshold voltage is higher than the read voltage is allocated to “1” data, and a state where the threshold voltage is lower than the read voltage is allocated to “0” data. It should be noted that the memory cell transistor MC may be capable of holding two or more bits of data.
  • the operation of increasing the threshold voltage in the writing operation is referred to as “1” writing operation.
  • the operation for maintaining the threshold voltage is referred to as “0” writing operation.
  • a voltage VH is applied to the selection gate lines SG 0 a , SG 1 a , and SG 2 a of the readout circuit unit RCU.
  • Voltage VH is a voltage that turns ON the corresponding transistor TR.
  • a power supply voltage VDD may be used as the voltage VH. Accordingly, the transistors TR 0 a , TR 1 a , and TR 2 a are turned ON, and the bit line BL and the memory pillar MP are electrically coupled.
  • a voltage VL is applied to selection gate lines SG 0 b and SG 2 b .
  • the voltage VL is lower than voltage VH and the threshold voltage of the corresponding transistor, and turns the corresponding transistor TR into the OFF state.
  • the transistor TR may function as a normally on type.
  • the voltage VL is a negative voltage in order to turn the transistor TR into the OFF state.
  • the voltage VSS may be used as the voltage VL. Accordingly, the transistors TR 0 b and TR 2 b are turned into the OFF state. Therefore, cell source line CSL is not electrically coupled to bit line BL and memory pillar MP. For example, cell source line CSL is in a floating state.
  • a ground voltage VSS is applied to the bit line BL corresponding to the “1” writing operation.
  • the voltage VBL is applied to the bit line BL corresponding to the “0” writing operation.
  • the voltage VBL is a voltage higher than the voltage VSS.
  • a voltage VSGD is applied to the selection gate line SGD.
  • the selection transistor ST 1 whose current path is applied with the voltage VSS in the “1” writing operation is turned ON by applied the voltage VSGD.
  • the selection transistor ST 1 whose current path is applied with the voltage VBL in the “0” writing operation is turned into the OFF-state by applied the voltage VSGD.
  • the threshold voltage of the selection transistor ST 1 is Vt_stg
  • the voltage VSGD, the voltage VSS, and the voltage VBL have a relationship of VSS ⁇ (VSGD ⁇ Vt_stg) ⁇ VBL.
  • a voltage Voff is applied to the selection gate line SGS.
  • the voltage Voff is a voltage that turns the corresponding selection transistor ST 1 or ST 2 into the OFF state. Accordingly, the selection transistor ST 2 is turned into the OFF state.
  • Voltage VSRC is applied to source line SL.
  • the voltage VSRC is higher than the voltage VSS and lower than the voltage VBL.
  • a program voltage VPGM is applied to the selected word line WL 2
  • a voltage VPASS is applied to non-selected word lines WL 0 , WL 1 , WL 3 and WL 4 .
  • the voltage VPASS is a voltage for turning ON the memory cell transistor MC regardless of the threshold voltage of the memory cell transistor MC.
  • the voltage VPASS is higher than the voltage VH.
  • the voltage VPGM is higher than the voltage VPASS.
  • the selection transistor ST 1 In the memory pillar MP corresponding to the “1” writing operation, the selection transistor ST 1 is in the ON state. Therefore, the potential of the channel of the memory cell transistor MC is maintained at VSS. Therefore, a potential difference (VPGM-VSS) between the control gate and the channel is increased. As a result, charges are injected into the charge storage layer 35 , and the threshold voltage of the memory cell transistor MC 2 rises.
  • the selection transistors ST 1 and ST 2 are in a cutoff state. Therefore, the channel is brought into a floating state, and the channel potential rises due to capacitive coupling between the channel and the word line WL (reference numeral “CNL boost” in FIG. 5 ). Therefore, the potential difference between the control gate and the channel is reduced. As a result, since only little charges are injected into the charge storage layer 35 , the threshold voltage of the memory cell transistor MC 2 is maintained.
  • FIG. 6 illustrates an example of the voltage of each interconnect during the reading operation.
  • the operation of reading “0 data” is referred to as ““0” reading operation”.
  • the operation of reading “1” data is referred to as ““1” reading operation”.
  • a voltage VBLRD is applied to the bit line BL.
  • the voltage VBLRD is higher than the voltage VSS. Further, for example, the voltage VSS is applied to the source line SL.
  • the voltage VL is applied to the selection gate lines SG 0 b , SG 2 a , and SG 2 b of the readout circuit unit RCU. Accordingly, the transistors TR 0 b , TR 2 a , and TR 2 b are turned into the OFF state. By turning the transistors TR 0 b and TR 2 a into the OFF state, the bit line BL and the memory pillar MP are not electrically coupled.
  • the voltage VH is applied to selection gate lines SG 0 a and SG 1 a . Accordingly, the transistors TR 0 a and TR 1 a are turned ON. Also, the voltage VSS is applied to the cell source line CSL.
  • a voltage Von is applied to the selection gate lines SGD and SGS.
  • the voltage Von is a voltage that turns ON the corresponding selection transistor ST 1 or ST 2 . Accordingly, the selection transistors ST 1 and ST 2 are turned ON.
  • a read voltage VCGRV is applied to the selected word line WL 2
  • a voltage VREAD is applied to the non-selected word lines WL 0 , WL 1 , WL 3 and WL 4 .
  • the voltage VCGRV is a voltage set in accordance with the threshold voltage level of memory cell transistor MC, and is, for example, a voltage higher than voltage VL and lower than voltage VH.
  • the voltage VREAD is a voltage higher than voltage VH and voltage VCGRV.
  • the voltage VREAD is a voltage for turning ON the memory cell transistor MC regardless of the threshold voltage of the memory cell transistor MC.
  • the threshold voltage of the memory cell transistor MC 2 is higher than the voltage VCGRV. Therefore, the memory cell transistor MC 2 is turned into the OFF state.
  • the channels of memory cell transistors MC 3 and MC 4 and selection transistor ST 1 are brought into a floating state, and the channel potential rises due to capacitive coupling with the word lines WL 3 and WL 4 and selection gate line SGD.
  • a voltage VBST caused by the rise of the channel potential is applied to the channel of the transistor TR 1 a .
  • the threshold voltage of the memory cell transistor MC 2 is lower than the voltage VCGRV. Therefore, the memory cell transistor MC 2 is turned ON. Since the memory cell transistors MC 0 to MC 4 and the selection transistors ST 1 and ST 2 are turned ON, the voltage VSS of the source line SL is applied to the channel of the transistor TR 1 a in the readout circuit unit RCU. In this case, the voltage of the back gate of the transistor TR 2 b does not rise, and the transistor TR 2 b is maintained in the OFF state. As a result, the bit line BL and cell source line CSL are not electrically coupled. In other words, almost no current flows from the bit line BL to the cell source line CSL.
  • the sense amplifier 21 reads data of the memory cell transistor MC by detecting a reading current flowing from the bit line BL to the cell source line CSL in the reading operation.
  • the reading current fluctuates depending on channel resistance of the memory pillar MP.
  • the channel resistance of the memory pillar MP tends to increase. Therefore, the reading current flowing through the memory pillar MP is reduced. Then, since it becomes difficult for the sense amplifier 21 to detect the reading current, the possibility of erroneous reading increases, and the reading time tends to increase.
  • the semiconductor memory device 1 includes the readout circuit unit RCU corresponding to the memory pillar MP.
  • the readout circuit unit RCU can set the coupling between the bit line BL and the cell source line CSL provided in the readout circuit unit RCU in accordance with the data of the memory cell transistor MC. Therefore, during the reading operation, the sense amplifier 21 can read data of the memory cell transistor MC by detecting a reading current flowing from the bit line BL to the cell source line CSL. Since the influence of the channel resistance of the memory pillar MP, that is, the influence of the structure of the memory cell array 18 , the decrease in the reading current flowing through the bit line BL can be suppressed. Therefore, the semiconductor memory device can suppress erroneous reading and improve the reliability. In addition, since the semiconductor memory device can suppress an increase in reading time, the processing capacity can be improved.
  • FIG. 7 to FIG. 22 illustrate a plan view of the readout circuit unit RCU and a cross-sectional view taken along a line A 1 -A 2 of the plan view.
  • a method of forming a structure corresponding to the interconnecting layer 33 of the memory cell array 18 as a sacrificial layer, and then replacing the sacrificial layer with a conductive material to form the interconnecting layer 33 (hereinafter referred to as “replacement”) is applied will be described.
  • replacement replacement in this example, a case where the interconnecting layers 41 and 43 are formed by replacement in the readout circuit unit RCU will be described.
  • insulating layers 50 and seven sacrificial layers 51 corresponding to the interconnecting layer 33 are alternately layered.
  • SiO 2 is used as the insulating layers 50 .
  • SiN is used as the sacrificial layers 51 .
  • the sacrificial layers 51 are not limited to SiN.
  • the sacrificial layers 51 may be, for example, made of a material that can obtain a sufficient wet etching selectivity with respect to the insulating layers 50 .
  • the memory pillar MP whose bottom surface reaches the interconnecting layer 32 is formed. More specifically, the insulating layers 50 and the sacrificial layers 51 are processed to form holes corresponding to the memory pillar MP. Next, the block insulating film 34 , the charge storage layer 35 , and the tunnel insulating film 36 are sequentially layered, and the block insulating film 34 , the charge storage layer 35 , and the tunnel insulating film 36 at the bottom of the hole and on the uppermost insulating layer 50 are removed. Next, the semiconductor layer 37 and the core layer 38 are sequentially layered to fill the inside of the hole. Next, the semiconductor layer 37 and the core layer 38 on the uppermost insulating layer 50 are removed. At this time, parts of the semiconductor layer 37 and the core layer 38 are etched in the upper part of the hole. Then, a cap layer 39 is formed to fill the upper portion of the hole.
  • the sacrificial layers 51 are removed to form a voids AG. More specifically, for example, a slit (not illustrated) of which the bottom surface reaches the interconnecting layer 32 , and from which seven sacrificial layers 51 are exposed, is formed on the side surface.
  • the sacrificial layers 51 are made of SiN
  • the sacrificial layers 51 exposed from the side surface of the slit is etched by wet etching using phosphoric acid (H 3 PO 4 ) to form the voids AG.
  • TiN and W are sequentially deposited to fill the voids AG.
  • the interconnecting layer 33 is formed by removing W and TiN in the slit and on the insulating layers 52 .
  • the slit is filled with SiO 2 , for example.
  • the semiconductor layer 40 is formed on the cap layer 39 .
  • an insulating layer 53 is formed on the insulating layer 52 .
  • the insulating layer 53 functions as an etching stopper at the time of forming the trench RT.
  • an insulating layer 54 , a sacrificial layer 55 , an insulating layer 54 , a semiconductor layer 56 , an insulating layer 54 , a sacrificial layer 55 , and an insulating layer 54 are sequentially layered on the insulating layer 53 .
  • the sacrificial layers 55 correspond to the interconnecting layers 41 and 43 .
  • the semiconductor layer 56 corresponds to the interconnecting layer 42 .
  • the insulating layer 53 for example, aluminum oxide is used. It should be noted that the insulating layer 53 may be any material that can obtain an etching selectivity with the insulating layer 54 , the sacrificial layer 55 , and the semiconductor layer 56 .
  • SiO 2 is used as the insulating layer 54 .
  • SiN is used as the sacrificial layer 55 .
  • amorphous silicon is used as the semiconductor layer 56 .
  • the trench RT whose bottom surface reaches the semiconductor layer 40 is formed. More specifically, the insulating layers 53 and 54 , the sacrificial layer 55 , and the semiconductor layer 56 are processed to form a trench RT. Next, after the insulating layer 44 is formed, the insulating layer 44 at the bottom of the trench RT and on the uppermost insulating layer 54 is removed. Next, the semiconductor layer 45 and the insulating layer 46 are sequentially layered to fill the inside of the trench RT. Next, the semiconductor layer 45 and the insulating layer 46 on the uppermost insulating layer 54 are removed.
  • the insulating layer 54 is formed to cover the upper surfaces of the insulating layer 44 , the semiconductor layer 45 , and the insulating layer 46 formed in the trench RT.
  • holes AH are formed so that the bottom surface reaches insulating layer 52 so as to separate trench RT, that is, insulating layer 44 , semiconductor layer 45 , and insulating layer 46 , and then the inside is filled with an insulating layer 48 .
  • the hole RH where the bottom surface reaches the insulating layer 53 is formed.
  • the semiconductor layer 56 exposed on the side surface of the hole RH is removed.
  • the insulating layer 44 on the side surface of the trench RT exposed by removing the semiconductor layer 56 is removed to expose the semiconductor layer 45 .
  • the conductive layer 57 is formed in the hole RH and the region from which the semiconductor layer 56 has been removed.
  • the conductive layer 57 is in contact with the exposed side surface of the semiconductor layer 45 .
  • the conductive layer 57 is made of a conductive material.
  • an n-type semiconductor is used as the conductive layer 57 .
  • doped polysilicon doped with phosphorus (P) or arsenic (As) may be formed as an n-type semiconductor by CVD.
  • the conductive layer 57 in the hole RH is etched.
  • the etching amount is adjusted so that the conductive layer 57 remains in a portion in contact with the semiconductor layer 45 .
  • the holes RH and the region from which the semiconductor layer 56 has been removed are filled with a sacrificial layer 58 .
  • a sacrificial layer 58 For example, SiN is used as the sacrificial layer 58 . It should be noted that the sacrificial layer 58 may not completely fill the hole RH and the region from which the semiconductor layer 56 has been removed, and may have a cavity inside.
  • the holes RH in which the bottom surface reaches insulating layer 53 are formed.
  • the semiconductor layer 56 exposed on the side surfaces of the holes RH is removed.
  • the sacrificial layers 55 and 58 are removed by wet etching, for example.
  • conductive layers 59 are formed in the holes RH and in the region from which the semiconductor layer 56 and the sacrificial layer 55 have been removed.
  • the conductive layers 59 is made of a conductive material.
  • a layered structure of TiN and W is used as the conductive layers 59 .
  • the conductive layers 59 in the holes RH are removed, and the holes RH are filled with the insulating layers 60 .
  • SiO 2 is used as the insulating layers 60 .
  • the etching amount is adjusted so as not to etch the conductive layers 59 in the region from which the semiconductor layer 56 and the sacrificial layer 55 have been removed. Accordingly, the conductive layers 59 are separated into three layers in the Z direction, and the interconnecting layers 41 to 43 are formed.
  • FIG. 23 to FIG. 31 are a plan view of the readout circuit unit RCU and a cross-sectional view taken along a line A 1 -A 2 of the plan view.
  • a case where the readout circuit unit RCU is formed without using replacement will be described.
  • the memory pillar MP, the interconnecting layers 33 , and the semiconductor layer 40 are formed in the same manner as in FIGS. 7 to 9 of the first example.
  • the insulating layer 53 is formed.
  • SiN is used as the insulating layer 53 , for example.
  • an insulating layer 54 , an interconnecting layer 41 , an insulating layer 54 , an interconnecting layer 42 , an insulating layer 54 , and an interconnecting layer 43 are sequentially layered on the insulating layer 53 .
  • conductive materials having different etching selectivity are used for the interconnecting layers 41 and 43 and the interconnecting layer 42 .
  • metal materials may be used as the interconnecting layers 41 and 43
  • a p-type semiconductor may be used. More specifically, for example, a layered structure of TiN and W may be used as the metal material.
  • the p-type semiconductor for example, doped polysilicon doped with boron (B) may be formed by CVD.
  • an n-type semiconductor is used as the interconnecting layer 42 .
  • doped polysilicon doped with phosphorus (P) or arsenic (As) may be formed as an n-type semiconductor by CVD.
  • the insulating layer 44 , the semiconductor layer 45 , and the insulating layer 46 are formed in the trench RT.
  • the holes AH are formed and an interior is embedded by insulating layer 48 in the same manner as in the first example illustrated in FIG. 12 .
  • the hole RH where the bottom surface reaches the insulating layer 53 is formed.
  • the interconnecting layer 42 exposed on the side surface of the hole RH is removed.
  • the insulating layer 44 on the side surface of the trench RT exposed by removing the interconnecting layer 42 is removed to expose the semiconductor layer 45 .
  • the conductive layer 57 is formed in the hole RH and the region from which the interconnecting layer 42 has been removed.
  • the conductive layer 57 is in contact with the exposed side surface of the semiconductor layer 45 .
  • an n-type semiconductor is used as the conductive layer 57 .
  • the conductive layer 57 in the hole RH is etched.
  • the etching amount is adjusted so that the conductive layer 57 remains in a portion in contact with the semiconductor layer 45 .
  • the interconnecting layer 42 is formed in the hole RH and the region from which the interconnecting layer 42 has been removed.
  • the interconnecting layer 42 in the holes RH are removed, and the holes RH are filled with the insulating layers 60 .
  • SiO 2 is used as the insulating layers 60 .
  • the configuration according to the present embodiment can be applied to the first embodiment.
  • the readout circuit unit RCU and the memory cell array 18 include an array portion and a stepped coupling portion.
  • a conductive layer 47 is formed on the readout circuit unit RCU, that is, on the semiconductor layer 45 and the insulating layer 46 .
  • a bit line BL extending in the Y direction is formed.
  • the stepped coupling portion includes a plurality of contact plugs CC coupled to selection gate lines SG 0 a , SG 1 a , SG 2 a , SG 0 b , and SG 2 b and the cell source line CSL of the readout circuit unit RCU, and selection gate lines SGD and SGS and word lines WL 0 to WL 4 of the memory cell array 18 .
  • a interconnecting layer (not illustrated) is formed on the contact plug CC.
  • the interconnecting layer 43 corresponding to the selection gate line SG 2 a of the readout circuit unit RCU, the interconnecting layer 42 corresponding to the selection gate line SG 1 a , and the interconnecting layer 41 corresponding to the selection gate line SG 0 a are drawn from the array portion in the X direction toward the stepped coupling portion in a staircase pattern.
  • the interconnecting layer 43 corresponding to the selection gate line SG 2 b , the interconnecting layer 42 corresponding to the cell source line CSL, and the interconnecting layer 41 corresponding to the gate line SG 0 b are drawn from the array portion in the X direction toward the stepped coupling portion in a staircase pattern so that the interconnecting layers 41 to 43 are adjacent to each other in the Y direction via the slit SLT configured to separate in the Y direction.
  • the interconnecting layers 33 corresponding to the selection gate line SGD, the word lines WL 4 to WL 0 , and the selection gate line SGS are drawn out from the array portion in the X direction toward the stepped coupling portion at a position farther from the array portion than the stepped coupling portion of the readout circuit unit RCU.
  • Each of the interconnecting layers 33 and 41 to 43 is coupled to the contact plug CC in a drawn end region.
  • FIG. 33 is a cross-sectional view taken along a line B 1 -B 2 of FIG. 32 It should be noted that in the example of FIG. 33 , the insulating layers 50 and 52 to 54 described in the second embodiment are omitted.
  • interconnecting layers 33 and interconnecting layers 41 to 43 are layered above the interconnecting layer 32 apart from each other in the Z direction.
  • the seven interconnecting layers 33 and the interconnecting layers 41 to 43 are drawn in the order of the interconnecting layer 43 , the interconnecting layer 42 , the interconnecting layer 41 , and the seven interconnecting layers 33 in the X direction from the array portion to the stepped coupling portion.
  • the contact plugs CC are provided on end regions of the interconnecting layers 33 and 41 to 43 drawn in the X direction.
  • the configuration according to the present embodiment can be applied to the first embodiment.
  • FIG. 34 An example of the cross-sectional configuration of the readout circuit unit RCU and the memory cell array 18 will be described with reference to FIG. 34 . It should be noted that in the example of FIG. 34 , a part of an interlayer insulating film is omitted.
  • the configuration of the memory pillar MP is the same as that of FIG. 3 of the first embodiment.
  • the readout circuit unit RCU of the present embodiment includes, for example, six transistors TR (TR 0 a , TR 1 a , TR 2 a , TR 0 b , TR 2 b , and TRC).
  • TR transistors TR
  • TR 0 a transistors TR
  • TR 1 a transistors TR 1 a
  • TR 2 a transistors TR 1 a
  • TR 0 b transistors TR 2 b
  • TRC transistors
  • the gate of the transistor TRC is coupled to a control gate line CG.
  • the control gate line CG is coupled to the row decoder 19 .
  • An interconnecting layer 49 functioning as the control gate line CG is provided between the interconnecting layer 42 functioning as the selection gate line SG 1 a and the interconnecting layer 43 functioning as the selection gate line SG 2 a in the Z direction.
  • the interconnecting layer 49 is made of a conductive material. For example, a semiconductor, a metal material, or the like is used as the interconnecting layer 49 .
  • the other configuration of the readout circuit unit RCU is the same as that of FIG. 3 of the first embodiment.
  • FIG. 35 illustrates an example of the voltage of each interconnect during the writing operation.
  • a voltage VH is applied to the selection gate lines SG 0 a , SG 1 a , and SG 2 a and the control gate line CG of the readout circuit unit RCU. Accordingly, the transistors TR 0 a , TR 1 a , TR 2 a , and TRC are turned ON, and the bit line BL and the memory pillar MP are electrically coupled. Further, a voltage VL is applied to selection gate lines SG 0 b and SG 2 b . Accordingly, the transistors TR 0 b and TR 2 b are turned into the OFF state. Therefore, cell source line CSL is not electrically coupled to bit line BL and memory pillar MP. For example, cell source line CSL is in a floating state.
  • a ground voltage VSS is applied to the bit line BL corresponding to the “1” writing operation. Further, the voltage VBL is applied to the bit line BL corresponding to the “0” writing operation.
  • a voltage VSGD is applied to the selection gate line SGD.
  • a voltage Voff is applied to the selection gate line SGS.
  • Voltage VSRC is applied to source line SL.
  • a voltage VPGM is applied to the selected word line WL 2
  • a voltage VPASS is applied to non-selected word lines WL 0 , WL 1 , WL 3 and WL 4 .
  • the selection transistor ST 1 In the memory pillar MP corresponding to the “1” writing operation, the selection transistor ST 1 is in the ON state. Therefore, charges are injected into the charge storage layer 35 , and the threshold voltage of the memory cell transistor MC rises.
  • the selection transistors ST 1 and ST 2 are in the OFF state. Therefore, since only little charges are injected into the charge storage layer 35 , the threshold voltage of the memory cell transistor MC is maintained.
  • FIG. 36 and FIG. 37 illustrate an example of the voltage of each interconnect during the reading operation.
  • the reading operation in the present embodiment includes a pre-latch operation for latching data read from the memory cell transistor MC in the readout circuit unit RCU, and a latch reading operation for reading data from the readout circuit unit RCU.
  • the voltage VSS is applied to the bit line BL and the source line SL.
  • a voltage Von is applied to the selection gate lines SGD and SGS. Accordingly, the selection transistors ST 1 and ST 2 are turned ON.
  • the read voltage VCGRV is applied to the selected word line WL 2
  • the voltage VREAD is applied to the non-selected word lines WL 0 , WL 1 , WL 3 and WL 4 .
  • the memory cell transistor MC 2 is in the OFF state. Therefore, the voltage VBST is applied to the readout circuit unit RCU.
  • the voltage VL is applied to the selection gate lines SG 0 b , SG 2 a , and SG 2 b of the readout circuit unit RCU. Accordingly, the transistors TR 0 b , TR 2 a , and TR 2 b are turned into the OFF state.
  • the voltage VSS for example, is applied to the cell source line CSL.
  • a voltage VG 1 is applied to the selection gate line SG 0 a .
  • the voltage VG 1 is higher than the voltage VBST. Accordingly, the transistor TR 0 a is turned ON.
  • a voltage Vcut is applied to the selection gate line SG 1 a .
  • the voltage Vcut is a voltage which is lower than the voltage VG 1 and turns the transistor TR 1 a to which the voltage VSS is applied into the ON state, and turns the transistor TR 1 a to which the voltage VBST is applied into the OFF state. Therefore, in the readout circuit unit RCU corresponding to the “1” reading operation, the transistor TR 1 a is turned into the OFF state.
  • the voltage Vlatch is applied to the control gate line CG. For example, the voltage Vlatch is higher than the voltage Vcut and lower than the voltage VG 1 .
  • the voltage Vlatch is a voltage for latching data (charge) in the channel region (data latch region) of transistor TRC.
  • the transistor TR 1 a is turned into the OFF state, the charge is not latched in the data latch region.
  • the voltage VBLRD is applied to the bit line BL
  • the voltage VSS is applied to the source line.
  • the same voltage as in the pre-latch operation is applied to the word lines WL and the selection gate lines SGD and SGS.
  • the voltage VL is applied to the selection gate lines SG 0 a , SG 1 a , TR 2 a , and SG 0 b of the readout circuit unit RCU. Accordingly, the transistors TR 0 a , TR 1 a , TR 2 a , and TR 0 b are turned into the OFF state.
  • the voltage VG 1 is applied to the selection gate line SG 2 b . Accordingly, the transistor TR 2 b is turned ON.
  • the voltage VSS is applied to the cell source line CSL.
  • the transistor TRC can be regarded as a transistor in which the semiconductor layer 45 provided between the transistor TR 1 a and the transistor TR 2 a functions as a charge storage layer, and a channel is formed in the semiconductor layer 45 provided between the transistor TR 2 b and the cell source line CSL. Therefore, in accordance with the voltage of the control gate line CG, a channel is formed in the semiconductor layer 45 provided between the transistor TR 2 b and the cell source line CSL. In this state, a voltage Vsense is applied to control gate line CG. The voltage Vsense is higher than the voltage VSS and lower than the voltage Vcut.
  • the transistor TRC is turned into the ON state.
  • a channel is formed in the semiconductor layer 45 provided between the transistor TR 2 b and the cell source line CSL. Accordingly, the bit line BL and the cell source line CSL are electrically coupled, and a current flows from the bit line BL to the cell source line CSL.
  • the voltage applied to each interconnect is the same as in FIG. 36 .
  • the memory cell transistor MC 2 of the memory pillar MP corresponding to the “0” reading operation is turned ON. Therefore, the voltage VSS is applied to the readout circuit unit RCU from the source line SL.
  • the transistor TR 1 a of the readout circuit unit RCU is turned into the ON state. Therefore, the charge is latched in the data latch region of the transistor TRC.
  • the voltage applied to each interconnect is the same as in FIG. 37 .
  • the transistor TRC is in the OFF state. In other words, a channel is not formed in the semiconductor layer 45 provided between the transistor TR 2 b and the cell source line CSL. Therefore, the bit line BL and cell source line CSL are not electrically coupled. Therefore, almost no current flows from the bit line BL to the cell source line CSL.
  • the sense amplifier 21 reads data by detecting a current (or a change in voltage) flowing from the bit line BL to the cell source line CSL.
  • the reading operation is performed after the data (charge) is latched in the readout circuit unit RCU, so that the reading operation can be executed even if the voltage VBST is a relatively low voltage. Therefore, the reliability can be improved.
  • the charge can be held in the readout circuit unit RCU. Therefore, for example, even in the case where the voltage VBST decreases with time due to a leak of a channel or the like, erroneous reading can be suppressed.
  • FIG. 38 illustrates the block BLK 0 , but the configuration of the other blocks BLK is also the same.
  • the block BLK 0 includes a plurality of string units SU.
  • Each string unit SU includes a plurality of memory groups MG.
  • Each memory group MG includes two memory strings MSa and MSb.
  • memory string MS when the memory strings MSa and MSb do not have to be discriminated from each other, they are collectively referred to as “memory string MS”.
  • Memory string MSa includes, for example, five memory cell transistors MCa 0 to MCa 4 , and selection transistors ST 1 a and ST 2 a .
  • the memory string MSb includes, for example, five memory cell transistors MC 0 b to MC 4 b , and selection transistors ST 1 b and STR 2 b .
  • the memory cell transistors MC 0 a to MC 4 a and MC 0 b to MC 4 b do not have to be discriminated from each other, they are collectively referred to as “memory cell transistors MC”.
  • the memory cell transistors MC 0 a and MC 0 b do not have to be discriminated from each other, they are collectively referred to as a memory cell transistor MC 0 .
  • the selection transistors ST 1 a and ST 1 b do not have to be discriminated from each other, they are hereinafter referred to as a selection transistor ST 1 .
  • the selection transistors ST 2 a and STR 2 b do not have to be discriminated from each other, it is described as a selection transistor ST 2 .
  • the memory cell transistor MC may be a MONOS type using an insulating film as the charge storage layer, or may be an FG type using a conductive layer as the charge storage layer. In the present embodiment, the FG type will be described below as an example.
  • the number of memory cell transistors MC is not limited to five, and may be eight, sixteen, thirty-two, sixty-four, ninety-six, one-hundred twenty-eight, etc., and the number is not limited. Further, one or more selection transistors ST 1 and ST 2 may be provided in each of the memory string MS.
  • respective current paths are coupled in series to the selection transistor ST 2 , the memory cell transistors MC 0 to MC 4 , and the selection transistor ST 1 in this order. More specifically, in the memory string MSa, respective current paths of the selection transistor ST 2 a , the memory cell transistors MC 0 a to MC 4 a , and the selection transistor ST 1 a are coupled in series in this order. In the same manner, in the memory string MSb, respective current paths of the selection transistor ST 2 b , the memory cell transistors MC 0 b to MC 4 b , and the selection transistor ST 1 b are coupled in series in this order.
  • the drain of the selection transistor ST 1 a and the drain of the selection transistor ST 1 b included in the memory group MG are commonly coupled to the readout circuit unit RCU.
  • the plurality of bit lines BL are independently controlled by the sense amplifier 21 .
  • the source of the selection transistor ST 2 a and the source of the selection transistor ST 2 b included in each memory group MG in the block BLK are commonly coupled to the source line SL.
  • Control gates of the plurality of memory cell transistors MC 0 a to MC 4 a and MC 0 b to MC 4 b in the same block BLK are commonly coupled to word lines WL 0 a to WL 4 a and WL 0 b to WL 4 b provided for each block BLK.
  • word lines WL when the word lines WL 0 a to WL 4 a and WL 0 b to WL 4 b do not have to be discriminated from each other, they are collectively referred to as “word lines WL”. Further, for example, when the word lines WL 0 a and WL 0 b do not have to be discriminated from each other, they are collectively referred to as “word line WL 0 ”. The same applies to the other word lines WL 1 to WL 4 .
  • the word lines WL 0 to WL 4 are coupled to the row decoder 19 .
  • the gates of the plurality of selection transistors ST 1 a in the same string unit SU are commonly coupled to the selection gate line SGDa, and the gates of the plurality of selection transistors ST 1 b are commonly coupled to the selection gate line SGDb. More specifically, the gates of the plurality of selection transistors ST 1 a in the string unit SU 0 are commonly coupled to the selection gate line SGD 0 a , and the gates of the plurality of selection transistors ST 1 b are commonly coupled to the selection gate line SGD 0 b .
  • the gates of the plurality of selection transistors ST 1 a in the string unit SU 1 are commonly coupled to the selection gate line SGD 1 a
  • the gates of the plurality of selection transistors ST 1 b are commonly coupled to the selection gate line SGDb 1 .
  • the selection gate line SGD is coupled to the row decoder 19 .
  • the gates of the plurality of selection transistors ST 2 a in the same block BLK are commonly coupled to the selection gate line SGSa, and the gates of the plurality of selection transistors ST 2 b are commonly coupled to the selection gate line SGSb. It should be noted that the selection gate lines SGSa and SGSb may be provided for each string unit SU.
  • the plurality of memory groups MG in the block BLK are coupled to different readout circuit units RCU.
  • the plurality of readout circuit units RCU corresponding to one string unit SU are commonly coupled to, for example, a cell source line CSL. Further, the plurality of readout circuit units RCU corresponding to one string unit SU are coupled to different bit lines BL (BL 0 to BL (N ⁇ 1)). In other words, the plurality of memory groups MG in the string unit SU are coupled to different bit lines BL via different readout circuit units RCU.
  • the bit lines BL are coupled to the sense amplifier 21 . Further, one memory group MG of each string unit SU in the block BLK is commonly coupled to one bit line BL via the corresponding readout circuit unit RCU.
  • the sources of the selection transistors ST 2 a and ST 2 b in the plurality of blocks BLK are commonly coupled to the source line SL.
  • a configuration of the readout circuit unit RCU is the same as that of FIG. 3 of the first embodiment.
  • the memory trench MT extending in the X direction is formed to separate the plurality of interconnecting layers 33 in the Y direction.
  • seven interconnecting layers 33 arranged on the right side of the drawing with respect to the memory trench MT function as the selection gate line SGSa, the word lines WL 0 a to WL 4 a , and the selection gate line SGDa.
  • the seven interconnecting layers 33 arranged on the left side of the drawing with respect to the memory trench MT function as the selection gate line SGSb, the word lines WL 0 b to WL 4 b , and the selection gate line SGDb.
  • a plurality of block insulating films 64 a and a plurality of charge storage layers 65 a are formed between the memory trench MT and the interconnecting layers 33 functioning as the selection gate line SGSa, the word lines WL 0 a to WL 4 a , and the selection gate line SGDa. More specifically, in the XY plane, one side surface of the block insulating film 64 a is in contact with any side surface of the interconnecting layer 33 , and the other side surface of the block insulating film 64 a is in contact with one side surface of the charge storage layer 65 a . The other side surface of the charge storage layer 65 a is in contact with the insulating layer 66 formed on the side surface of the memory trench MT in the XY plane.
  • a plurality of block insulating films 64 b and a plurality of charge storage layers 65 b are formed between the memory trench MT and the interconnecting layer 33 which functions as the selection gate line SGSb, the word lines WL 0 b to WL 4 b , and the selection gate line SGDb.
  • An insulating layer 66 is formed on the side surface of the memory trench MT facing in the Y direction. Further, in the memory pillar MP, two semiconductor layers 67 a and 67 b are formed, extending in the Z direction, the side surfaces being in contact with the insulating layer 66 , and the bottom surfaces being in contact with the interconnecting layer 32 . Furthermore, an insulating layer 66 is formed between the two semiconductor layers 67 a and 67 b .
  • the semiconductor layer 67 a is a region in which the channels of the selection transistor ST 2 a , the memory cell transistors MC 0 a to MC 4 a , and the selection transistor ST 1 a are formed.
  • the semiconductor layer 67 a functions as a signal line that couples current paths of the selection transistor ST 2 a , the memory cell transistors MC 0 a to MC 4 a , and the selection transistor ST 1 a .
  • the semiconductor layer 67 b is a region in which the channels of the selection transistor ST 2 b , the memory cell transistors MC 0 b to MC 4 b , and the selection transistor ST 1 b are formed. Therefore, the semiconductor layer 67 b functions as a signal line that couples current paths of the selection transistor ST 2 b , the memory cell transistors MC 0 b to MC 4 b , and the selection transistor ST 1 b.
  • the insulating layer 66 provided between the semiconductor layer 67 a and the charge storage layer 65 a functions as a tunnel insulating film of the selection transistors ST 1 a and ST 2 b and the memory cell transistors MC 0 b to MC 4 b .
  • the insulating layer 66 provided between the semiconductor layer 67 b and the charge storage layer 65 b functions as a tunnel insulating film of the selection transistors ST 1 b and ST 2 b and the memory cell transistors MC 0 b to MC 4 b.
  • the insulating material is used as the block insulating films 64 a and 64 b .
  • the insulating material may be, for example, a layered structure of Hf (Si) Ox/SiO 2 /Hf (Si) Ox using Hf and SiO 2 , or may be SiO 2 .
  • Hf (Si) Ox may or may not contain Si in Hf Ox.
  • polysilicon is used as the charge storage layers 65 a and 65 b .
  • the charge storage layers 65 a and 65 b may contain a metal such as TaN, TiN, W or Ru.
  • SiO 2 or SiON is used as the insulating layers 66 .
  • polysilicon is used as the semiconductor layers 67 a and 67 b and the cap layer 69 .
  • the selection transistor ST 2 a , the memory cell transistors MC 0 a to MC 4 a , and the seven interconnecting layers 33 functioning as the selection transistor ST 1 a and the semiconductor layer 67 a constitute a memory string MSa. More specifically, a region including interconnecting layer 33 functioning as selection gate line SGSa and semiconductor layer 67 a constitutes the selection transistor ST 2 a . A region including the interconnecting layers 33 functioning respectively as the word lines WL 0 a to WL 4 a and the semiconductor layer 67 a constitutes the memory cell transistors MC 0 a to MC 4 a , respectively.
  • a region including interconnecting layer 33 functioning as the selection gate line SGDa and semiconductor layer 67 a constitutes the selection transistor ST 1 a .
  • the selection transistor ST 2 b , the memory cell transistors MC 0 b to MC 4 b , and the seven interconnecting layers 33 functioning as the selection transistor ST 1 b and the semiconductor layer 67 b constitute a memory string MSb.
  • a region including interconnecting layer 33 functioning as selection gate line SGSb and semiconductor layer 67 b constitutes the selection transistor ST 2 b .
  • a region including the interconnecting layers 33 functioning respectively as the word lines WL 0 b to WL 4 b and the semiconductor layer 67 b constitutes the memory cell transistors MC 0 b to MC 4 b , respectively.
  • a region including interconnecting layer 33 functioning as the selection gate line SGDb and semiconductor layer 67 b constitutes the selection transistor ST 1 b.
  • FIG. 40 illustrates the SG 0 plane and the WL 4 plane in the XY plane.
  • the configuration on the SG 0 plane is the same as FIG. 4 of the first embodiment.
  • the word lines WL 4 a (interconnecting layer 33 ) and the word lines WL 4 b (interconnecting layer 33 ) extending in the X direction are alternately arranged apart from each other in the Y direction.
  • a memory trench MT extending in the X direction is formed between the word line WL 4 a and the word line WL 4 b .
  • the plurality of semiconductor layers 67 a and 67 b are disposed respectively in the X direction.
  • the semiconductor layers 67 a and 67 b are disposed apart from each other in the Y direction.
  • a charge storage layer 65 a is formed in contact with the side surface of the memory trench MT facing the semiconductor layer 67 a .
  • a block insulating film 64 a is formed in contact with the charge storage layer 65 a .
  • the charge storage layer 65 b is formed in contact with the side surface of the memory trench MT facing semiconductor layer 67 b .
  • a block insulating film 64 b is formed in contact with the charge storage layer 65 b.
  • a region including the semiconductor layers 67 a and 67 b , the charge storage layers 65 a and 65 b , and the block insulating films 64 a and 64 b adjacent in the Y direction functions as one memory pillar MP.
  • the one memory pillar MP corresponds to one memory group MG.
  • a region including the interconnecting layer 33 functioning as the word line WL 4 a , the block insulating film 64 a , the charge storage layer 65 a , and the semiconductor layer 67 a constitutes the memory cell transistor MC 4 a .
  • a region including the interconnecting layer 33 functioning as the word line WL 4 b , the block insulating film 64 b , the charge storage layer 65 b , and the semiconductor layer 67 b constitutes a memory cell transistor MC 4 b.
  • FIG. 41 illustrates an example of the voltage of each interconnect during the writing operation.
  • the voltages applied to the bit lines BL, the source lines SL, and each interconnect of the readout circuit unit RCU are the same as in FIG. 5 of the first embodiment.
  • voltage VSGD is applied to selection gate lines SGDa and SGDb.
  • Voltage Voff is applied to selection gate lines SGSa and SGSb.
  • a program voltage VPGM is applied to the selected word line WL 2 b
  • the voltage VPASS is applied to non-selected word lines WL 0 b , WL 1 b , WL 3 b , WL 4 b , and WL 0 a to WL 4 a.
  • the selection transistors ST 1 a , ST 1 b , ST 2 a , and STR 2 b are in the cutoff state. Therefore, the channels of the memory strings MSa and MSb are in a floating state. As a result, almost no charge is injected into the charge storage layer 35 corresponding to the memory cell transistor MC 2 b . Therefore, the threshold voltage of the memory cell transistor MC 2 b is maintained.
  • FIG. 42 illustrates an example of the voltage of each interconnect during the reading operation. A case where the memory cell transistor MC 2 b of the memory string MSb is selected will be described below.
  • the voltages applied to the bit lines BL, the source lines SL, and each interconnect of the readout circuit unit RCU are the same as in FIG. 6 of the first embodiment.
  • the voltage Von is applied to the selection gate lines SGDb and SGSb. Accordingly, the selection transistors ST 1 b and STR 2 b are turned into the ON state.
  • the read voltage VCGRV is applied to the selected word line WL 2 b
  • the voltage VREAD is applied to the non-selected word lines WL 0 b , WL 1 b , WL 3 b and WL 4 b.
  • voltage Voff is applied to the selection gate lines SGDa and SGSa of non-selected memory strings MSa. Accordingly, the selection transistors ST 1 a and ST 2 a are turned into the OFF state. As a result, the channel of the non-selected memory string MSa is brought into a floating state.
  • the negative voltage VBB is applied to the non-selected word lines WL 0 a to WL 4 a .
  • the negative voltage VBB is a voltage that brings the memory cell transistor MC into the cutoff state regardless of the threshold voltage of the memory cell transistor MC.
  • the memory cell transistor MC 2 b is turned into the OFF state. Therefore, the channel potentials of memory cell transistors MC 3 b and MC 4 b and selection transistor ST 1 b rise.
  • a voltage VBST caused by the rise of the channel potential is applied to the channel of the transistor TR 1 a . Then, capacitive coupling between the channel of the transistor TR 1 a and the channel of the transistor TR 2 b causes the voltage at the back gate of the transistor TR 2 b to rise, and the transistor TR 2 b is turned ON. As a result, bit line BL and cell source line CSL are electrically coupled, and a current flows from the bit line BL to cell source line CSL.
  • the memory cell transistor MC 2 b is turned ON. Therefore, in the readout circuit unit RCU, the voltage VSS of the source line SL is applied to the channel of the transistor TR 1 a via the memory string MSb. In this case, the voltage of the back gate of the transistor TR 2 b does not rise, and the transistor TR 2 b is maintained in the OFF state. As a result, the bit line BL and cell source line CSL are not electrically coupled. In other words, no current flows from the bit line BL to the cell source line CSL.
  • FIG. 43 illustrates an example of the voltage of each interconnect during the reading operation. Points different from the first example will be mainly described below.
  • the voltage Von is applied to the selection gate line SGDa of the non-selected memory string MSa, and the voltage VREAD is applied to the non-selected word lines WL 0 a to WL 4 a.
  • the memory cell transistor MC 2 b In the memory string MSb corresponding to the “1” reading operation, the memory cell transistor MC 2 b is turned into the OFF state. Therefore, the channel potentials of memory cell transistors MC 3 b and MC 4 b and selection transistor ST 1 b rise. Further, in the non-selected memory string MSa, the selection transistor ST 2 a is turned into the OFF state. Therefore, the channel potentials of memory cell transistors MC 0 a to MC 4 a and selection transistor ST 1 a rise. In the readout circuit unit RCU, the voltage VBST due to the above-mentioned increase of the channel potential is applied to the channel of the transistor TR 1 a .
  • the memory cell transistor MC 2 b is turned ON. Therefore, in the readout circuit unit RCU, the voltage VSS of the source line SL is applied to the channel of the transistor TR 1 a via the memory string MSb. In this case, the voltage of the back gate of the transistor TR 2 b does not rise, and the transistor TR 2 b is maintained in the OFF state. As a result, the bit line BL and cell source line CSL are not electrically coupled. In other words, no current flows from the bit line BL to the cell source line CSL.
  • the channel potential of the non-selected memory string MS can be raised in the “0” reading operation. Therefore, for example, when the selected memory cell transistor MC of the selected memory string MS is relatively close to the selection transistor ST 1 and the voltage VBST cannot be sufficiently obtained, or even when an OFF current flows from the selected memory cell transistor MC to the source line SL side and thus the voltage VBST tends to decrease with time, the voltage VEST required for the reading operation in the readout circuit unit RCU can be obtained by the increase in the channel potential of the non-selected memory string MS.
  • the readout circuit unit RCU described in the fourth embodiment may be applied to the readout circuit unit RCU of the present embodiment.
  • the memory cell transistor MC is the FG type has been described in the present embodiment, it may be the MONOS type.
  • a configuration of the readout circuit unit RCU is the same as that of FIG. 34 of the fourth embodiment.
  • the readout circuit unit RCU is provided corresponding to the memory pillar MP.
  • one memory pillar MP corresponds to one memory string MS.
  • the memory string MS includes, for example, four memory cell transistors MC (MC 0 to MC 3 ), three cutoff transistors XG (XG 0 to XG 2 ), and a selection transistor ST 1 . It should be noted that the number of memory cell transistors MC and the cutoff transistors XG in the memory string MS may be selected as desired. For example, the number of cutoff transistors XG is one less than that of the memory cell transistors MC.
  • a plurality of the memory cell transistors MC and a plurality of the cutoff transistors XG are alternately layered in the Z direction, and the selection transistor ST 1 is provided thereon. More specifically, the memory cell transistor MC 0 , the cutoff transistor XG 0 , the memory cell transistor MC 1 , the cutoff transistor XG 1 , the memory cell transistor MC 2 , the cutoff transistor XG 2 , the memory cell transistor MC 3 , and the selection transistor ST 1 are sequentially stacked on the insulating layer 31 , and their current paths are coupled in series. Then, the selection transistor ST 1 is coupled to the corresponding readout circuit unit RCU via the semiconductor layer 40 .
  • the cutoff transistor XG 0 functions as a switch element for controlling charge transfer between the memory cell transistor MC 0 and the memory cell transistor MC 1 .
  • the cutoff transistor XG 1 functions as a switch element for controlling transfer of charge between the memory cell transistor MC 1 and the memory cell transistor MC 2 .
  • the cutoff transistor XG 2 functions as a switch element for controlling charge transfer between the memory cell transistor MC 2 and the memory cell transistor MC 3 .
  • the gates of memory cell transistors MC 0 to MC 3 are coupled to word lines WL 0 to WL 3 , respectively.
  • the gates of cutoff transistors XG 0 to XG 2 are coupled to cutoff gate lines XL 0 to XL 2 , respectively.
  • the gate of the selection transistor ST 1 is coupled to the selection gate line SGD.
  • the word lines WL 0 to WL 3 , the cutoff gate lines XL 0 to XL 2 , and the selection gate line SGD are coupled to row decoder 19 .
  • An insulating layer 31 is formed on a semiconductor substrate 30 .
  • SiO 2 is used as the insulating layers 31 .
  • interconnecting layers 70 that function respectively as the word line WL 0 , a cutoff gate line XL 0 , a word line WL 1 , a cutoff gate line XL 1 , a word line WL 2 , a cutoff gate line XL 2 , a word line WL 3 and a selection gate line SGD are layered apart from each other in the Z direction.
  • the interconnecting layers 70 extend in the X direction.
  • the interconnecting layers 70 are made of a conductive material.
  • the interconnecting layers 70 for example, the n-type semiconductor, the p-type semiconductor, or a metal material is used.
  • a memory pillar MP whose bottom surface reaches the insulating layer 31 through the eight interconnecting layers 70 is formed.
  • the memory pillar MP according to the present embodiment includes the insulating layer 71 , an oxide semiconductor layer 72 , a core layer 73 , and a cap layer 74 .
  • holes corresponding to the memory pillars MP are formed so that the bottom surfaces reach the insulating layer 31 through the interconnecting layers 70 .
  • An insulating layer 71 and an oxide semiconductor layer 72 are sequentially layered on side surfaces of the holes.
  • the insulating layer 71 functions as a gate insulating film of the memory cell transistors MC 0 to MC 3 , the cutoff transistors XG 0 to XG 2 , and the selection transistor ST 1 .
  • the oxide semiconductor layer 72 functions as a charge storing layer of the memory cell transistors MC 0 to MC 3 .
  • the oxide semiconductor layer 72 is a region where the channels of the memory cell transistors MC 0 to MC 4 , the cutoff transistors XG 0 to XG 2 , and the selection transistor ST 1 are formed, and functions as current paths (signal lines) for transferring the charges to the charge storing layer.
  • the core layer 73 is formed with the side surface is in contact with the oxide semiconductor layer 72 and the bottom surface in contact with the insulating layer 31 .
  • a cap layer 74 whose side surface is in contact with the insulating layer 71 is formed. It should be noted that the cap layer 74 may be omitted.
  • the material of the insulating layer 71 is selected, for example, from SiO 2 , SiON, a high dielectric constant material (for example, aluminum oxide, hafnium oxide, or zirconium oxide).
  • the insulating layer 71 may be a mixture film of these materials or a laminated film.
  • the material of the oxide semiconductor layer 72 is an oxide such as indium (In), gallium (Ga), zinc (Zn), tin (Sn), or a mixture (compound) of these oxides.
  • the material of the oxide semiconductor layer 72 is InGaZnO, InGaSnO, or the like. It should be noted that a material used for the oxide semiconductor layer 72 may be used for the cap layer 74 .
  • SiO 2 is used, for example.
  • Memory cell transistors MC 0 to MC 3 are formed of memory pillars MP and four interconnecting layers 70 functioning as word lines WL 0 to WL 3 , respectively.
  • cutoff transistors XG 0 to XG 2 are formed of the memory pillars MP and the interconnecting layers 70 functioning as the cutoff gate lines XL 0 to XL 2 , respectively.
  • the memory pillar MP and the interconnecting layer 70 functioning as the selection gate line SGD constitute the selection transistor ST 1 .
  • the source line SL is omitted. Further, in the memory pillar MP, the semiconductor layer functioning as a current path coupling the bit line BL and the source line SL is omitted.
  • FIG. 45 illustrates the SG 0 plane in the XY plane and the upper surface of the word line WL 3 (hereinafter referred to as the “WL 3 plane”).
  • the configuration on the SG 0 plane is the same as FIG. 4 of the first embodiment.
  • a plurality of memory pillars MP penetrating through the word line WL 3 (interconnecting layer 70 ) are staggered in two rows in the X direction.
  • the insulating layer 71 and the oxide semiconductor layer 72 are sequentially layered on the side surface of the memory pillar MP, and the core layer 73 is formed inside the oxide semiconductor layer 72 .
  • the region including the word line WL 3 and the memory pillar MP constitute the memory cell transistor MC 3 .
  • the semiconductor memory device includes the memory pillar MP coupled to the readout circuit unit RCU having the latch function and including the oxide semiconductor layer 72 .
  • the oxide semiconductor layer 72 can be used as the charge storing layer of the memory cell transistor MC and a current path for transferring the charges stored in the charge storing layer of the to the readout circuit unit RCU.
  • a semiconductor memory device includes: a first interconnecting layer ( 33 ; WL) extending in a first direction (X direction); a first signal line ( 37 ) extending in a second direction (Z direction) intersecting the first direction and perpendicular to a substrate ( 30 ); a first memory cell (MC) that stores first information between the first interconnecting layer and the first signal line; a second interconnecting layer (SG 0 a ) provided above the first interconnecting layer and extending in the first direction; a third interconnecting layer (SG 1 a ) provided above the second interconnecting layer and extending in the first direction; a fourth interconnecting layer (SG 2 a ) provided above the third interconnecting layer and extending in the first direction; a fifth interconnecting layer (SG 0 b ) disposed apart from the second interconnecting layer in a third direction (Y direction) intersecting the first and second directions and extending in the first direction; a sixth interconnecting layer (CSL) disposed apart from the
  • the semiconductor memory device capable of improving the reliability can be provided.
  • the “coupling” in the above embodiment includes a state in which it is indirectly coupled with another something such as a transistor or a resistor interposed therebetween.

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JP2018157208A (ja) 2017-03-16 2018-10-04 東芝メモリ株式会社 半導体メモリ

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US20220059570A1 (en) * 2020-08-21 2022-02-24 Kioxia Corporation Semiconductor memory device
US11605647B2 (en) * 2020-08-21 2023-03-14 Kioxia Corporation Ferroelectric-type semiconductor memory device with hole transfer-type layer

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US20200303400A1 (en) 2020-09-24
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