US10714243B2 - Variable resistance circuit, oscillator circuit, and semiconductor device - Google Patents

Variable resistance circuit, oscillator circuit, and semiconductor device Download PDF

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US10714243B2
US10714243B2 US16/284,678 US201916284678A US10714243B2 US 10714243 B2 US10714243 B2 US 10714243B2 US 201916284678 A US201916284678 A US 201916284678A US 10714243 B2 US10714243 B2 US 10714243B2
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circuit
variable resistance
switch
resistor
resistance
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US20190267972A1 (en
Inventor
Takahiro Kikuchi
Toshikazu Kuwano
Sachiyuki Abe
Shuji Kawaguchi
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C10/00—Adjustable resistors
    • H01C10/50—Adjustable resistors structurally combined with switching arrangements
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C10/00—Adjustable resistors
    • H01C10/06—Adjustable resistors adjustable by short-circuiting different amounts of the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C10/00—Adjustable resistors
    • H01C10/16—Adjustable resistors including plural resistive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
    • H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/02—Automatic control of frequency or phase; Synchronisation using a frequency discriminator comprising a passive frequency-determining element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/16—Resistor networks not otherwise provided for

Definitions

  • the present invention relates to a variable resistance circuit whose resistance value can be changed according to a control signal. Furthermore, the invention relates to an oscillator circuit that uses such a variable resistance circuit, a semiconductor device that includes such a variable resistance circuit, and the like.
  • a semiconductor device such as a microcomputer includes an oscillator circuit that supplies a clock signal to a CPU (Central Processing Unit) and peripheral circuits.
  • the oscillation frequency can be matched with a target frequency by adjusting the resistance value of a resistor that constitutes the oscillator circuit.
  • a variable resistance circuit whose resistance value can be changed according to a control signal is used.
  • variable resistance circuit In a known variable resistance circuit, a plurality of switch circuits are respectively connected in parallel to a plurality of resistors that constitute a ladder resistor circuit, for example. As a result of controlling each switch circuit to an OFF state or an ON state, the resistance value of the variable resistance circuit can be adjusted by switching the element through which a current supplied to the variable resistance circuit flows between the resistor and the switch circuit.
  • a clock oscillator circuit that automatically adjusts the oscillation frequency through trimming with reference to a clock that is accurate at a low speed is disclosed in JP-A-2000-341119 (Paragraphs 0007-0008 and 0027-0028, FIGS. 1 and 3 ), as a related technology.
  • This clock oscillator circuit includes an oscillator that outputs a clock whose oscillation frequency changes according to the value of a parameter, a frequency measurement circuit that measures the oscillation frequency of the oscillator with reference to a calibration clock, and a trimming control circuit that trims the parameter using a binary search according to the measured oscillation frequency.
  • the clock oscillator circuit oscillates at a frequency that is in inverse proportion to the product of the resistance value of a resistor 2 and the capacitance value of a capacitor 3 by repeating charging and discharging of the capacitor 3 , and outputs a clock pulse to a clock terminal.
  • inputs of a switch array 8 are respectively connected to gates of N+1 P-channel transistors, and the drain and source of each P-channel transistor are respectively connected to two ends of the corresponding resistor having a resistance value of R multiplied to the power of 2 in the resistor 2 .
  • the resistor 2 and the switch array 8 constitute a variable resistance circuit
  • the N+1 P-channel transistors in the switch array 8 correspond to a plurality of switch circuits that are respectively connected in parallel to the plurality of resistors included in the resistor 2 , which is a ladder resistor circuit.
  • An advantage of some aspects of the invention is to accurately adjust the resistance value of a variable resistance circuit, when the resistance value of the variable resistance circuit is adjusted, by reducing the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistances of switch circuits even if the switch circuits that each bypass a resistor included in a ladder resistor circuit are switched between an OFF state and an ON state. Also, another advantage of some aspects of the invention is to provide an oscillator circuit that uses such a variable resistance circuit. Furthermore, another advantage of some aspects of the invention is to provide a semiconductor device including such a variable resistance circuit.
  • a variable resistance circuit includes: a ladder resistor circuit including a plurality of resistors; a first switch circuit connected in series to one end of one resistor of the plurality of resistors; and a second switch circuit connected in parallel to a series circuit of the one resistor and the first switch circuit. When one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off.
  • the first switch circuit when the second switch circuit is turned off, the first switch circuit is turned on and is included in the current path of the variable resistance circuit along with a resistor.
  • the second switch circuit when the second switch circuit is turned on and is included in the current path of the variable resistance circuit, the first switch circuit is turned off. Therefore, even if the second switch circuit for bypassing a resistor included in the ladder resistor circuit is switched between an OFF state and an ON state, the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistance of the second switch circuit can be reduced, and the resistance value of the variable resistance circuit can be accurately adjusted.
  • variable resistance circuit includes a plurality of the first switch circuits and a plurality of the second switch circuits, and the number of the plurality of first switch circuits may be the same as the number of the plurality of second switch circuits.
  • variable resistance circuit further includes a third switch circuit connected in parallel to a resistor, of the plurality of resistors, that is not connected to the first switch circuit.
  • third switch circuit instead of the first and second switch circuits in some units in the variable resistance circuit, the number of switch circuits in the variable resistance circuit can be reduced, and the circuit area can be reduced.
  • the first switch circuit, the second switch circuit, and the third switch circuit may each include the same number of switch elements. Furthermore, the first switch circuit, the second switch circuit, and the third switch circuit may each desirably have the same on-resistance.
  • a configuration can be realized in which, in a unit in which the first and second switch circuits are provided, the on-resistance of the switch circuit included in the current path of the variable resistance circuit does not noticeably change regardless of whether the first switch circuit is turned on or the second switch circuit is turned on. Also, if the resistance value of a resistor in a unit in which the third switch circuit is provided is larger than the resistance value of a resistor in another unit, the error in the change rate of the resistance value of the variable resistance circuit due to the on-resistance of the third switch circuit can be suppressed to a certain range.
  • An oscillator circuit includes: a charging and discharging type oscillator configured to perform an oscillation operation at an oscillation frequency according to the amount of a control current, and a control current generation unit that includes any of the variable resistance circuits described above, and is configured to generate the control current based on an output voltage of a temperature sensor, using a resistance value, of the variable resistance circuit, that is set by a control signal.
  • the control current is generated based on the output voltage of the temperature sensor using the resistance value. Therefore, since the oscillation frequency of the oscillator circuit is controlled by the control current, an oscillator circuit can be provided whose oscillation frequency is continuously temperature-compensated according to the change in temperature without switching the resistance element or the capacitance element that is used in the oscillation operation, and in which noise, jitter, or the like is reduced.
  • a semiconductor device includes any of the variable resistance circuits described above.
  • a semiconductor device can be provided in which, even if the second switch circuit for bypassing a resistor included in the ladder resistor circuit is switched between an OFF state and an ON state, the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistance of the second switch circuit can be reduced, and the resistance value of the variable resistance circuit can be accurately adjusted.
  • FIG. 1 is a block diagram illustrating an exemplary configuration of a semiconductor device according to one embodiment of the invention.
  • FIG. 2 is a circuit diagram illustrating an exemplary configuration of an oscillator circuit shown in FIG. 1 .
  • FIG. 3 is a circuit diagram illustrating an exemplary configuration of a charging and discharging type oscillator shown in FIG. 2 .
  • FIG. 4 is a circuit diagram illustrating an exemplary configuration of a control current generation unit shown in FIG. 2 .
  • FIG. 5 is a diagram illustrating a temperature characteristic of a reference voltage generated by a reference voltage generation circuit.
  • FIG. 6 is a diagram illustrating a temperature characteristic of an output voltage of a temperature characteristic slope correction circuit.
  • FIG. 7 is a diagram illustrating a temperature characteristic of a control current generated by a voltage-current converter circuit.
  • FIG. 8 is a diagram illustrating a frequency error in a state in which the temperature characteristic of the oscillator circuit is not compensated.
  • FIG. 9 is a diagram illustrating a frequency error in a state in which the temperature characteristic of the oscillator circuit is compensated.
  • FIG. 10 is a circuit diagram illustrating a configuration of a variable resistance circuit according to a comparative example.
  • FIG. 11 is a circuit diagram illustrating an exemplary configuration of a variable resistance circuit according to one embodiment of the invention.
  • FIG. 12 is a circuit diagram illustrating a specific example of first and second switch circuits shown in FIG. 11 .
  • FIG. 13 is a diagram in which resistance values of the variable resistance circuits according to the comparative example and the embodiment are compared.
  • FIG. 14 is a diagram in which amounts of increase in resistance value of the variable resistance circuits according to the comparative example and the embodiment are compared.
  • FIG. 15 is a circuit diagram illustrating a configuration of a modification of the variable resistance circuit according to one embodiment of the invention.
  • FIG. 1 is a block diagram illustrating an exemplary configuration of a semiconductor device according to one embodiment of the invention.
  • the semiconductor device includes a variable resistance circuit according to one embodiment of the invention.
  • a microcomputer including an oscillator circuit 10 , a CPU 20 , a nonvolatile memory 30 , a RAM (Random Access Memory) 40 , and a peripheral circuit 50 is shown as an example of the semiconductor device.
  • the oscillator circuit 10 generates a clock signal CLK having a predetermined frequency by performing an oscillation operation, and supplies the clock signal CLK to the CPU 20 and the peripheral circuit 50 .
  • the CPU 20 operates in synchronization with the clock signal CLK supplied from the oscillator circuit 10 , and performs various types of signal processing and control processing according to programs.
  • the nonvolatile memory 30 stores programs, data, and the like for the CPU 20 to perform the various types of signal processing and control processing.
  • the nonvolatile memory 30 stores control data including first and second control signals that are used to adjust the oscillation frequency of the oscillator circuit 10 , and supplies the control data to the oscillator circuit 10 .
  • control data including first and second control signals that are used to adjust the oscillation frequency of the oscillator circuit 10 , and supplies the control data to the oscillator circuit 10 .
  • a plurality of fuses may be provided separate from the nonvolatile memory 30 in order to store the control data.
  • the RAM 40 is used as a work area of the CPU 20 , and temporarily stores programs and data that have been read out from the nonvolatile memory 30 , or results of computation and the like performed by the CPU 20 according to programs.
  • FIG. 2 is a circuit diagram illustrating an exemplary configuration of the oscillator circuit shown in FIG. 1 .
  • the oscillator circuit 10 according to one embodiment of the invention includes a charging and discharging type oscillator 60 and a control current generation unit 70 , and operates by being supplied with a high-potential side power supply potential VDD and a low-potential side power supply potential VSS from a regulator or the like.
  • the power supply potential VSS is assumed to be ground potential (0V).
  • the charging and discharging type oscillator 60 generates an oscillation signal Fout by performing an oscillation operation at an oscillation frequency according to the amount of a control current Icnt.
  • the oscillation signal Fout is used as the clock signal CLK shown in FIG. 1 .
  • the control current generation unit 70 includes a variable resistance circuit according to one embodiment of the invention, and generates the control current Icnt based on an output voltage of a temperature sensor using the resistance value of the variable resistance circuit that is set based on the control signals.
  • FIG. 3 is a circuit diagram illustrating an exemplary configuration of the charging and discharging type oscillator shown in FIG. 2 .
  • the charging and discharging type oscillator 60 includes P-channel MOS (metal oxide semiconductor) transistors QP 1 and QP 2 , N-channel MOS transistors QN 1 and QN 2 , capacitors C 1 and C 2 , inverters 61 to 66 , and an RS flip-flop (RS latch) 67 .
  • the inverter 65 generates the oscillation signal Fout by inverting an output signal output from an output terminal Q of the RS flip-flop 67
  • the inverter 66 generates an inverted oscillation signal Fx by further inverting the oscillation signal Fout.
  • the control current Icnt supplied to the charging and discharging type oscillator 60 is supplied to a source of the transistor QP 1 and a source of the transistor QP 2 by current mirror circuits or the like.
  • the transistor QP 1 has a gate to which the oscillation signal Fout is supplied.
  • the transistor QN 1 has a drain connected to a drain of the transistor QP 1 , a source connected to an interconnect of the power supply potential VSS, and a gate to which the oscillation signal Fout is applied.
  • One end of the capacitor C 1 is connected to the drain of the transistor QP 1 and the drain of the transistor QN 1 , and the other end is connected to the interconnect of the power supply potential VSS.
  • the signal generated at the one end of the capacitor C 1 is buffered by the inverters 61 and 62 , and then supplied to a reset terminal R of the RS flip-flop 67 as a reset signal.
  • the transistor QP 2 has a gate to which the inverted oscillation signal Fx is applied.
  • the transistor QN 2 has a drain connected to a drain of the transistor QP 2 , a source connected to the interconnect of the power supply potential VSS, and a gate to which the inverted oscillation signal Fx is applied.
  • One end of the capacitor C 2 is connected to the drain of the transistor QP 2 and the drain of the transistor QN 2 , and the other end is connected to the interconnect of the power supply potential VSS.
  • the signal generated at the one end of the capacitor C 2 is buffered by the inverters 63 and 64 , and then supplied to a set terminal S of the RS flip-flop 67 as a set signal.
  • the RS flip-flop 67 is set, when the reset signal is at a low level, at a timing when the set signal rises, and activates the output signal to a high level, and is reset, when the set signal is at a low level, at a timing when the reset signal rises, and deactivates the output signal to a low level.
  • the oscillation signal Fout is changed to a high level, and the inverted oscillation signal Fx is changed to a low level. Accordingly, the transistor QP 1 is turned off and the transistor QN 1 is turned on, and therefore charges accumulated in the capacitor C 1 are discharged, and the reset signal is changed to a low level.
  • the transistor QP 2 is turned on and the transistor QN 2 is turned off, and therefore the control current Icnt flows to the capacitor C 2 , the capacitor C 2 is charged, and the set signal is changed to a high level.
  • the RS flip-flop 67 is set, and the output signal is activated to a high level.
  • the oscillation signal Fout is changed to a low level and the inverted oscillation signal Fx is changed to a high level. Therefore, the transistor QP 2 is turned off and the transistor QN 2 is turned on, and as a result, charges accumulated in the capacitor C 2 are discharged and the set signal is changed to a low level.
  • the transistor QP 1 is turned on and the transistor QN 1 is turned off, the control current Icnt flows to the capacitor C 1 , the capacitor C 1 is charged, and the reset signal is changed to a high level.
  • the RS flip-flop 67 is reset, and the output signal is deactivated to a low level.
  • the charging and discharging type oscillator 60 performs a highly accurate oscillation operation.
  • the speed at which the RS flip-flop 67 is repeatedly set and reset is approximately proportional to the amount of the control current Icnt, and therefore the oscillation frequency of the charging and discharging type oscillator 60 can be controlled by the amount of the control current Icnt.
  • FIG. 4 is a circuit diagram illustrating an exemplary configuration of the control current generation unit shown in FIG. 2 .
  • the control current generation unit 70 includes a reference voltage generation circuit 71 , a temperature characteristic slope correction circuit 72 , and a voltage-current converter circuit 73 .
  • the reference voltage generation circuit 71 includes a PNP bipolar transistor QB 1 and a differential amplifier circuit AMP 1 , for example, and generates a reference voltage V 1 having a first temperature characteristic.
  • the transistor QB 1 has an emitter to which a constant current Iref is supplied, and a collector and a base that are connected to an interconnect of the power supply potential VSS. Since the base of the transistor QB 1 is connected to the collector, the transistor QB 1 is equivalent to a diode.
  • the differential amplifier circuit AMP 1 includes a non-inverting input terminal connected to the emitter of the transistor QB 1 , and an inverting input terminal connected to an output terminal, and functions as a voltage follower that buffers the voltage applied to the non-inverting input terminal, and outputs the voltage from the output terminal. Therefore, the reference voltage generation circuit 71 generates the reference voltage V 1 based on the voltage between the emitter, and the base and collector, of the transistor QB 1 .
  • a temperature sensor is constituted by a bipolar transistor, and the reference voltage V 1 having a first temperature characteristic can be generated based on the output voltage of the temperature sensor.
  • FIG. 5 is a diagram schematically illustrating the temperature characteristic of the reference voltage generated by the reference voltage generation circuit shown in FIG. 4 .
  • the horizontal axis shows the temperature T
  • the vertical axis shows the reference voltage V 1 generated by the reference voltage generation circuit 71 .
  • the reference voltage V 1 decreases as the temperature T increases.
  • the temperature characteristic of the reference voltage V 1 is mainly determined by the temperature characteristic of the transistor QB 1 .
  • the temperature characteristic of the control current Icnt that is ultimately output from the control current generation unit 70 is adjustable, the temperature dependency of the constant current Iref has a predetermined allowable range.
  • the temperature characteristic slope correction circuit 72 includes a constant voltage generation circuit 72 a , a differential amplifier circuit AMP 2 , and resistors R 71 and R 72 , for example, corrects the slope of the temperature characteristic of the reference voltage V 1 according to the first control signal included in the control data shown in FIG. 1 , and generates an output voltage V 2 having a second temperature characteristic.
  • the constant voltage generation circuit 72 a is constituted by a bandgap reference circuit or the like, for example, and generates a constant voltage Vref.
  • the constant voltage Vref desirably has an extremely low temperature dependency, because the temperature characteristic of the control current Icnt that is ultimately output from the control current generation unit 70 is adjustable, the temperature dependency of the constant voltage Vref has a predetermined allowable range.
  • the differential amplifier circuit AMP 2 has a non-inverting input terminal to which the constant voltage Vref is applied, and an inverting input terminal that is connected to the output terminal of the reference voltage generation circuit 71 via the resistor R 71 and is also connected to an output terminal of the differential amplifier circuit AMP 2 via the resistor R 72 , and outputs an output voltage V 2 from the output terminal by amplifying the reference voltage V 1 using the constant voltage Vref as a reference.
  • At least one of the resistors R 71 and R 72 is a variable resistance circuit that is used to adjust the amplification factor (closed loop gain) of the differential amplifier circuit AMP 2 , and has a resistance value that is set according to the first control signal.
  • the temperature characteristic slope correction circuit 72 can correct the slope of the temperature characteristic of the reference voltage V 1 to a desired slope based on the resistance value of the resistor R 72 (or R 71 ).
  • V 2 of the differential amplifier circuit AMP 2 is obtained as in equation (1) assuming that the open loop gain of the differential amplifier circuit AMP 2 is sufficiently large.
  • FIG. 6 is a diagram schematically illustrating a temperature characteristic of the output voltage of the temperature characteristic slope correction circuit shown in FIG. 4 .
  • the horizontal axis shows the temperature T
  • the vertical axis shows the output voltage V 2 of the temperature characteristic slope correction circuit 72 .
  • the output voltage V 2 increases as the temperature T increases.
  • the voltage-current converter circuit 73 includes a differential amplifier circuit AMP 3 , an N-channel MOS transistor QN 3 , P-channel MOS transistors QP 3 and QP 4 , and a resistor R 73 , for example, converts the output voltage V 2 of the temperature characteristic slope correction circuit 72 to the control current Icnt, and adjusts the amount of the control current Icnt according to the second control signal included in the control data shown in FIG. 1 .
  • the differential amplifier circuit AMP 3 includes a non-inverting input terminal to which the output voltage V 2 of the temperature characteristic slope correction circuit 72 is applied, and an inverting input terminal to which a feedback voltage FB is applied, and outputs an output voltage V 3 from an output terminal.
  • the transistor QN 3 has a gate to which the output voltage V 3 of the differential amplifier circuit AMP 3 is applied, and a source connected to the interconnect of the power supply potential VSS via the resistor R 73 .
  • the transistors QP 3 and QP 4 constitute a current mirror circuit.
  • the transistor QP 3 has a source connected to an interconnect of the power supply potential VDD, and a drain and a gate that are connected to a drain of the transistor QN 3 .
  • the transistor QP 4 has a source connected to the interconnect of the power supply potential VDD, and a gate connected to the drain and gate of the transistor QP 3 .
  • a current proportional to the current flowing through the transistor QP 3 flows through the transistor QP 4 , and as a result, the control current Icnt is output from the drain of the transistor QP 4 .
  • the transistor QN 3 controls the amount of current that flows through the transistor QP 3 according to the output voltage V 2 of the temperature characteristic slope correction circuit 72 .
  • the feedback voltage FB is generated at one end of the resistor R 73 . Since the feedback voltage FB is applied to the inverting input terminal of the differential amplifier circuit AMP 3 , the feedback voltage FB becomes equal to the output voltage V 2 of the temperature characteristic slope correction circuit 72 that is applied to the non-inverting input terminal.
  • control current Icnt is expressed by equation (2) using a current I 3 flowing through the transistor QN 3 .
  • ⁇ is a proportional constant that is determined by the size ratio between the transistors QP 3 and QP 4 that constitute the current mirror circuit.
  • the resistor R 73 is a variable resistance circuit used to adjust the voltage-current conversion rate of the transistor QN 3 , and has a resistance value that is set according to the second control signal.
  • the voltage-current converter circuit 73 adjusts the amount of control current Icnt that is output from the transistor QP 4 based on the resistance value of the resistor R 73 . With this, the oscillation frequency at a given temperature can be set to a desired frequency.
  • FIG. 7 is a diagram schematically illustrating a temperature characteristic of the control current generated by the voltage-current converter circuit shown in FIG. 4 .
  • the horizontal axis shows the temperature T
  • the vertical axis shows the control current Icnt generated by the voltage-current converter circuit 73 .
  • the control current Icnt increases as the temperature T increases.
  • the amount of control current Icnt is adjusted ( FIG. 7 ) by adjusting the resistance value of the resistor R 73 in the voltage-current converter circuit 73 so that the oscillation frequency at a given temperature (25° C., for example) matches the target value.
  • the temperature characteristic of the output voltage V 2 is adjusted ( FIG. 6 ) by adjusting the resistance value of the resistor R 72 (or R 71 ) in the temperature characteristic slope correction circuit 72 so that the frequency error at a high temperature (85° C., for example) or a low temperature ( ⁇ 40° C., for example) decreases.
  • the first and second control signals for setting these resistance values are stored in the nonvolatile memory 30 (or fuses) shown in FIG. 1 as the control data, and the first and second control signals are automatically read out when the oscillator circuit is started up, and are used. In this way, as a result of storing the control data corresponding to each oscillator circuit in the storage, the characteristics of each oscillator circuit can be improved.
  • FIG. 8 is a diagram illustrating an exemplary frequency error in a state in which the temperature characteristic of the oscillator circuit is not compensated.
  • FIG. 9 is a diagram illustrating an exemplary frequency error in a state in which the temperature characteristic of the oscillator circuit is compensated.
  • the horizontal axis shows the environmental temperature Ta [° C.] around the oscillator circuit, and the vertical axis shows measured values of the frequency error [%].
  • the control current Icnt supplied to the charging and discharging type oscillator 60 shown in FIG. 2 is made constant regardless of the temperature.
  • the charging and discharging type oscillator 60 has a temperature dependency in which the oscillation frequency decreases as the environmental temperature Ta increases, as shown in FIG. 8 .
  • the control current Icnt is made to have an appropriate temperature characteristic by the control current generation unit 70 shown in FIG. 2 , the temperature dependency of the oscillation frequency of the charging and discharging type oscillator 60 is suppressed by making use of the temperature characteristic of the control current Icnt, as shown in FIG. 9 .
  • the charging and discharging type oscillator 60 shown in FIG. 2 has a temperature dependency in which the oscillation frequency increases as the environmental temperature Ta increases in a state in which the temperature characteristic of the oscillator circuit is not compensated.
  • an NPN bipolar transistor may be used instead of the PNP bipolar transistor in the reference voltage generation circuit 71 shown in FIG. 4 .
  • the NPN bipolar transistor is connected on the power supply potential VDD side.
  • a configuration may be adopted in which both the PNP bipolar transistor and NPN bipolar transistor are included in the reference voltage generation circuit 71 , and switching is performed to use one of them.
  • an inverting amplifier circuit may be added to the temperature characteristic slope correction circuit 72 shown in FIG. 4 , or the differential amplifier circuit AMP 2 may perform a non-inverting amplification operation.
  • the control current is generated based on the output voltage of a temperature sensor using the set resistance value. Therefore, since the oscillation frequency of the oscillator circuit is controlled by the control current, it is possible to provide an oscillator circuit whose oscillation frequency is continuously temperature-compensated according to a change in temperature without switching the resistance element or the capacitance element that is used in the oscillation operation, and in which noise, jitter, or the like is reduced.
  • variable resistance circuit that can be used as the resistor R 71 or R 72 in the temperature characteristic slope correction circuit 72 shown in FIG. 4 , and the resistor R 73 in the voltage-current converter circuit 73 will be described while being compared with a comparative example.
  • FIG. 10 is a circuit diagram illustrating a configuration of a variable resistance circuit according to a comparative example.
  • FIG. 11 is a circuit diagram illustrating an exemplary configuration of the variable resistance circuit according to one embodiment of the invention.
  • the resistance value of the variable resistance circuit is controlled by four one-bit control signals SEL 1 to SEL 4 will be described, as an example.
  • a variable resistance circuit 80 ( FIG. 11 ) includes a ladder resistor circuit including a plurality of adjustment resistors (hereinafter, simply referred to as “resistors”) R 1 to R 4 connected in series to a basic resistor R 0 , between a node N 1 and a node N 2 .
  • resistors hereinafter, simply referred to as “resistors”
  • an i th resistor R 1 has a resistance value of 2 (i-1) ⁇ R.
  • the resistance values of the resistors R 1 to R 4 are respectively R, 2R, 4R, and 8R.
  • variable resistance circuit according to the comparative example further includes a plurality of switch circuits SW 1 to SW 4 that are respectively connected in parallel to the resistors R 1 to R 4 , and inverters 81 to 84 that respectively invert the control signals SEL 1 to SEL 4 and supply the inverted control signals to the respective switch circuits SW 1 to SW 4 .
  • variable resistance circuit In the variable resistance circuit according to the comparative example, the number of switch circuits that are controlled to be turned on in order to bypass resistors included in the ladder resistor circuit changes when the resistance value of the variable resistance circuit is adjusted, and therefore, the total value of on-resistances of switch circuits included in the current path of the variable resistance circuit also changes. Accordingly, the change amount of resistance value due to the selection/non-selection of resistors included in the ladder resistor circuit is influenced by an unintended change in the total on-resistance of switch circuits, and as a result, an error from the desired change amount of the resistance value occurs.
  • the variable resistance circuit according to one embodiment of the invention 80 includes a first switch circuit (first switch circuit SW 11 , for example) connected in series to one end of one resistor (resistor R 1 , for example), of a plurality of resistors that constitute a ladder resistor circuit, a second switch circuit (second switch circuit SW 21 , for example) connected in parallel to a series circuit of the resistor and the first switch circuit, and an inverter (inverter 81 , for example) that inverts a control signal (control signal SEL 1 , for example) and supplies the inverted control signal to the second switch circuit.
  • the resistor R 1 , the first switch circuit SW 11 , the second switch circuit SW 21 , and the inverter 81 constitute one unit, and the variable resistance circuit 80 may include a plurality of units connected in series. The number of units can be increased or decreased according to the required resistance value adjustable range.
  • the other of the first and second switch circuits SW 11 and SW 21 is turned off.
  • the control signal SEL 1 for selecting the resistor R 1 is activated, the first switch circuit SW 11 is turned on and the second switch circuit SW 21 is turned off, and the resistor R 1 is included in the current path of the variable resistance circuit 80 .
  • the first switch circuit SW 11 when the second switch circuit SW 21 is turned off, the first switch circuit SW 11 is turned on and is included in the current path of the variable resistance circuit 80 along with the resistor R 1 .
  • the second switch circuit SW 21 when the second switch circuit SW 21 is turned on and is included in the current path of the variable resistance circuit 80 , the first switch circuit SW 11 is turned off.
  • the second switch circuit SW 21 for bypassing the resistor R 1 included in the ladder resistor circuit is switched between an OFF state and an ON state, the error in the change amount of the resistance value of the variable resistance circuit 80 due to the on-resistance of the second switch circuit SW 21 can be reduced, and the resistance value of the variable resistance circuit 80 can be accurately adjusted. Also, a semiconductor device including such a variable resistance circuit 80 can be provided.
  • FIG. 12 is a circuit diagram illustrating a specific example of the first and second switch circuits shown in FIG. 11 .
  • the first switch circuit SW 11 includes an N-channel MOS transistor QN 11 and a P-channel MOS transistor QP 11 , as switch elements
  • the second switch circuit SW 21 includes an N-channel MOS transistor QN 21 and a P-channel MOS transistor QP 21 , as switch elements.
  • any number of switch elements may be included in one switch circuit, it is desirable that the number of switch elements is the same and the on-resistance is the same between the first switch circuit and the second switch circuit that are provided with respect to the same resistor. With this, the on-resistance of the switch circuit included in the current path of the variable resistance circuit 80 can be made equal regardless of which of the first and second switch circuits is turned on. Note that the on-resistances being the same means that the switch circuits have sufficiently the same on-resistance in order to achieve the advantage of the invention.
  • the control signal SEL 1 for selecting the resistor R 1 is supplied to gates of the transistors QN 11 and QP 21 . Also, the inverter 81 inverts the control signal SEL 1 and supplies an inverted control signal XSEL 1 to gates of the transistors QN 21 and QP 11 .
  • the control signal SEL 1 for selecting the resistor R 1 when the control signal SEL 1 for selecting the resistor R 1 is activated to a high level, the transistors QN 11 and QP 11 are turned on and the transistors QN 21 and QP 21 are turned off, and the resistor R 1 is included in the current path of the variable resistance circuit 80 .
  • the control signal SEL 1 for selecting the resistor R 1 is deactivated to a low level, the transistors QN 11 and QP 11 are turned off and the transistors QN 21 and QP 21 are turned on, and the resistor R 1 is bypassed.
  • the on-resistance of each switch circuit can be reduced by adjusting the capability balance between the N-channel MOS transistor and the P-channel MOS transistor that constitute the switch circuit or increasing the sizes thereof. Also, the on-resistance of the switch circuit can be reduced by increasing the gate-source voltages of the N-channel MOS transistor and the P-channel MOS transistor.
  • the first and second switch circuits may be provided for each of the plurality of resistors included in the ladder resistor circuit.
  • the variable resistance circuit 80 includes a plurality of first switch circuits SW 11 to SW 14 , a plurality of second switch circuits SW 21 to SW 24 , and inverters 81 to 84 that are respectively associated with the resistors R 1 to R 4 , and the number of first switch circuits SW 11 to SW 14 is the same as the number of second switch circuits SW 21 to SW 24 .
  • FIG. 13 is a diagram in which resistance values of the variable resistance circuits according to the comparative example and the embodiment are compared.
  • FIG. 14 is a diagram in which amounts of increase in resistance value of the variable resistance circuits according to the comparative example and the embodiment are compared.
  • the horizontal axis shows the control value SEL represented by the four one-bit control signals SEL 4 to SEL 1 .
  • the vertical axis shows the resistance value [ ⁇ ] of the series circuit of the basic resistor R 0 and the variable resistance circuit shown in FIG. 10 or 11 .
  • the vertical axis shows the amount of increase [ ⁇ ] in the resistance value of the variable resistance circuit shown in FIG. 10 or 11 .
  • FIGS. 13 and 14 show simulation results.
  • the conditions of the simulation is that the resistance value of the basic resistor R 0 is 1000 ⁇ , the resistance values of the resistors R 1 to R 4 are respectively 150 ⁇ , 300 ⁇ , 600 ⁇ , and 1200 ⁇ , and the on-resistance of each switch circuit is 100 ⁇ .
  • the resistance value of the series circuit of the basic resistor R 0 and the variable resistance circuit increases as the control value SEL increases.
  • the resistance value of the variable resistance circuit does not linearly increase as the control value SEL increases.
  • the amount of increase in the resistance value of the variable resistance circuit when the control value SEL increases by “1” varies in a range between 50 ⁇ to 350 ⁇ .
  • the resistance value of the variable resistance circuit 80 linearly increases as the control value SEL increases, as shown in FIG. 13 .
  • the amount of increase in the resistance value of the variable resistance circuit 80 when the control value SEL increases by “1” is kept constant to 150 ⁇ , and the resistance value of the variable resistance circuit 80 solely depends on the resistance values of the resistors selected in the ladder resistor circuit.
  • the resistance value of the basic resistor R 0 may be set to 600 ⁇ , which is obtained by subtracting 400 ⁇ of on-resistance in total from 1000 ⁇ of the resistance value of the basic resistor R 0 .
  • the on-resistances of the switch circuits need not to be taken into consideration when the oscillator circuit is designed.
  • FIG. 15 is a circuit diagram illustrating a configuration of a modification of the variable resistance circuit according to one embodiment of the invention.
  • the resistance values of the resistors R 1 to R 4 are assumed to be respectively 150 ⁇ , 300 ⁇ , 600 ⁇ , and 1200 ⁇ . If the on-resistance of each switch circuit is assumed to be 100 ⁇ , because the resistance value of the resistor R 3 or R 4 is sufficiently large relative to 100 ⁇ , even if the first switch circuit connected in series to the resistor R 3 or R 4 is omitted, the change rate of the resistance value of the variable resistance circuit 80 a is not largely affected.
  • Each resistor R 1 -R 4 and its associated circuitry i.e.
  • switch circuits and inverters can be considered a resistance sub-circuit.
  • the R 1 /R 2 resistance sub-circuits Du to the differences in configuration between the R 1 /R 2 resistance sub-circuits and the R 3 /R 4 resistance sub circuits (described below) the R 1 /R 2 resistance sub-circuits are first resistance sub-circuits 150 and the R 3 /R 4 resistance sub-circuits are second resistance sub-circuits 152 .
  • variable resistance circuit 80 a includes a ladder resistor circuit including a plurality of resistors R 1 to R 4 , a first switch circuit (first switch circuit SW 11 , for example) connected in series to one end of one resistor (resistor R 1 , for example), of the resistors R 1 to R 4 , a second switch circuit (second switch circuit SW 21 , for example) connected in parallel to a series circuit of the resistor (resistor R 1 ) and the first switch circuit (first switch circuit SW 11 ), and a third switch circuit (third switch circuit SW 33 , for example) connected in parallel to a resistor (resistor R 3 , for example), of the resistors R 1 to R 4 , that is not connected to a first switch circuit.
  • first switch circuit SW 11 and SW 21 when one of the first and second switch circuits SW 11 and SW 21 is turned on, the other of the first and second switch circuits SW 11 and SW 21 is turned off.
  • variable resistance circuit 80 a may further include a first switch circuit SW 12 connected in series to one end of the resistor R 2 , a second switch circuit SW 22 connected in parallel to a series circuit of the resistor R 2 and the first switch circuit SW 12 , and a third switch circuit SW 34 connected in parallel to the resistor R 4 .
  • first switch circuit SW 12 connected in series to one end of the resistor R 2
  • second switch circuit SW 22 connected in parallel to a series circuit of the resistor R 2 and the first switch circuit SW 12
  • a third switch circuit SW 34 connected in parallel to the resistor R 4 .
  • the number of switch circuits in the variable resistance circuit 80 can be reduced, and the circuit area can be reduced.
  • the first switch circuits SW 11 and SW 12 , the second switch circuits SW 21 and SW 22 , and the third switch circuits SW 33 and SW 34 may each include the same number of switch elements. Furthermore, it is desirable that the first switch circuits SW 11 and SW 12 , the second switch circuits SW 21 and SW 22 , and the third switch circuits SW 33 and SW 34 each have the same on-resistance.
  • the on-resistance of the switch circuit included in the current path of the variable resistance circuit 80 does not noticeably change regardless of whether the first switch circuit SW 11 is turned on or the second switch circuit SW 21 is turned on.
  • the resistance value of the resistor R 3 or R 4 in a unit in which the third switch circuit SW 33 or SW 34 is provided is larger than the resistance value of the resistor R 1 or R 2 in another unit, the error in the change rate of the resistance value of the variable resistance circuit 80 due to the on-resistance of the third switch circuit SW 33 or SW 34 can be suppressed to be in a certain range.

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000341119A (ja) 1999-05-31 2000-12-08 Nec Corp クロック発振回路
JP2007036151A (ja) 2005-07-29 2007-02-08 Seiko Instruments Inc 抵抗分圧回路を備えた半導体装置
US20110304376A1 (en) 2010-06-10 2011-12-15 Fumiyasu Utsunomiya Semiconductor integrated circuit including variable resistor circuit
US20120092078A1 (en) 2010-10-13 2012-04-19 Yasukazu Kai Variable resistor circuit and oscillation circuit
US20120182065A1 (en) 2011-01-17 2012-07-19 Kazuaki Sano Resistive divider circuit and voltage detection circuit
US8570139B2 (en) * 2010-07-26 2013-10-29 Samsung Electronics Co., Ltd. Variable resister having resistance varying geometrically ratio and control method thereof
US9046910B2 (en) * 2011-03-31 2015-06-02 Renesas Electronics Corporation Constant current generation circuit and microprocessor including the same
US9503058B1 (en) * 2015-02-24 2016-11-22 Xilinx, Inc. Relaxation oscillator
US20190199287A1 (en) 2017-12-27 2019-06-27 Seiko Epson Corporation Oscillation circuit, microcomputer and electronic device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009217809A (ja) * 2008-02-12 2009-09-24 Seiko Epson Corp 基準電圧生成回路、集積回路装置および信号処理装置
JP2015177512A (ja) * 2014-03-18 2015-10-05 セイコーエプソン株式会社 回路装置及び電子機器
US9577628B2 (en) * 2015-04-08 2017-02-21 Lockheed Martin Corporation Gate pulsing gate ladder
JP6638340B2 (ja) * 2015-11-12 2020-01-29 セイコーエプソン株式会社 回路装置、発振器、電子機器及び移動体

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000341119A (ja) 1999-05-31 2000-12-08 Nec Corp クロック発振回路
US6329860B1 (en) 1999-05-31 2001-12-11 Nec Corporation Clock generator producing clock signal quickly adjusted to target frequency
JP2007036151A (ja) 2005-07-29 2007-02-08 Seiko Instruments Inc 抵抗分圧回路を備えた半導体装置
US20110304376A1 (en) 2010-06-10 2011-12-15 Fumiyasu Utsunomiya Semiconductor integrated circuit including variable resistor circuit
JP2011258827A (ja) 2010-06-10 2011-12-22 Seiko Instruments Inc 可変抵抗回路を備えた半導体集積回路
US8570139B2 (en) * 2010-07-26 2013-10-29 Samsung Electronics Co., Ltd. Variable resister having resistance varying geometrically ratio and control method thereof
JP2012085163A (ja) 2010-10-13 2012-04-26 Lapis Semiconductor Co Ltd 可変抵抗回路および発振回路
US20120092078A1 (en) 2010-10-13 2012-04-19 Yasukazu Kai Variable resistor circuit and oscillation circuit
US20120182065A1 (en) 2011-01-17 2012-07-19 Kazuaki Sano Resistive divider circuit and voltage detection circuit
JP2012151186A (ja) 2011-01-17 2012-08-09 Seiko Instruments Inc 抵抗分割回路及び電圧検出回路
US9046910B2 (en) * 2011-03-31 2015-06-02 Renesas Electronics Corporation Constant current generation circuit and microprocessor including the same
US9503058B1 (en) * 2015-02-24 2016-11-22 Xilinx, Inc. Relaxation oscillator
US20190199287A1 (en) 2017-12-27 2019-06-27 Seiko Epson Corporation Oscillation circuit, microcomputer and electronic device
JP2019118006A (ja) 2017-12-27 2019-07-18 セイコーエプソン株式会社 発振回路、マイクロコンピューター、及び、電子機器

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