US10204791B1 - Contact plug for high-voltage devices - Google Patents

Contact plug for high-voltage devices Download PDF

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US10204791B1
US10204791B1 US15/713,457 US201715713457A US10204791B1 US 10204791 B1 US10204791 B1 US 10204791B1 US 201715713457 A US201715713457 A US 201715713457A US 10204791 B1 US10204791 B1 US 10204791B1
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Prior art keywords
interconnect
contact
hfet
plug
disposed
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Alexey Kudymov
Linlin Liu
Jamal Ramdani
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Power Integrations Inc
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Power Integrations Inc
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Priority to US15/713,457 priority Critical patent/US10204791B1/en
Assigned to POWER INTEGRATIONS, INC. reassignment POWER INTEGRATIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUDYMOV, ALEXEY, LIU, LINLIN, RAMDANI, JAMAL
Priority to JP2018175459A priority patent/JP7285629B2/ja
Priority to TW112124478A priority patent/TWI850004B/zh
Priority to TW111127106A priority patent/TWI807925B/zh
Priority to TW107132951A priority patent/TWI773828B/zh
Priority to EP18195756.4A priority patent/EP3460841B1/en
Priority to CN201811108439.0A priority patent/CN109616521B/zh
Priority to CN202410360127.8A priority patent/CN118315420A/zh
Priority to US16/221,027 priority patent/US10665463B2/en
Publication of US10204791B1 publication Critical patent/US10204791B1/en
Application granted granted Critical
Priority to US16/857,049 priority patent/US11373873B2/en
Priority to US17/824,287 priority patent/US11776815B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H01L21/28593—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T asymmetrical sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • This disclosure relates generally to semiconductor devices, and more specifically to high voltage heterostructure field effect transistors (HFETs)
  • HFET high voltage field effect transistor
  • HEMT high-electron mobility transistor
  • GaN gallium nitride
  • HEMT high-electron mobility transistor
  • HFETs based on gallium nitride (GaN) and other wide bandgap nitride III materials can be used with electrical devices in high-speed switching and high-power applications (such as power switches and power converters) due to their high electron mobility, high breakdown voltage, and high saturation electron velocity characteristics. These physical properties allow HFETs to change states substantially faster than other semiconductor switches that conduct the same currents at similar voltages.
  • the materials used in the construction of HFETs also allow them to operate at higher temperatures than transistors that use traditional silicon-based technology.
  • FIG. 1A is a cross-sectional side view of an example semiconductor device which may use an asymmetrical plug interconnect structure, in accordance with an embodiment of the disclosure.
  • FIG. 1B is a cross-sectional side view of another example semiconductor device which may use an asymmetrical plug interconnect structure, in accordance with an embodiment of the disclosure.
  • FIG. 2 is a cross-sectional side view of an example semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the disclosure.
  • FIG. 3A is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in accordance with an embodiment of the disclosure.
  • FIG. 3B is a cross-sectional side view of an example semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the disclosure.
  • FIG. 4 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in accordance with an embodiment of the disclosure.
  • FIG. 5 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in accordance with an embodiment of the disclosure.
  • FIG. 6 is an example process flow for fabricating a semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the disclosure.
  • Interconnects and plugs may be used to connect metals separated by passivation, oxide, and/or interlayer dielectric (ILD) layers.
  • interconnects and plugs may be used to couple the ohmic contacts (e.g., the source and drain) of an HFET to their respective metal layers. These metal layers may be disposed above the passivation and ILD layers.
  • the overall thickness of the passivation, oxide, and ILD layers are generally quite thick in order for the HFET to hold voltage without breaking down. In one example, the overall thickness of the passivation, ILD, and/or oxide layers is at least 3.7 micrometers ( ⁇ m).
  • a via hole is formed to deposit interconnect metal above the electrical contact to the semiconductor material.
  • This via hole is placed at the center of the ohmic contact and an interconnect is deposited in the via hole.
  • the plug is then formed in the center of the interconnect (which is recessed).
  • the overall depth of the plug may need to be as deep as the combined thickness of the passivation, ILD, and other oxide layers (e.g., 3.7 ⁇ m).
  • One type of plug which may be used is a tungsten plug, also referred to as a W-plug.
  • the depth of the plug is generally limited to about 2 ⁇ m due to process constraints.
  • two plugs may be needed to reach the equivalent thickness of passivation, ILD, and other oxide layers.
  • the processing steps required to form two stacked plugs may add extra cost to the device as compared to forming one plug. Also by eliminating the two-step plug process, reliability of the process may be increased.
  • an asymmetrical plug interconnect structure is used.
  • One or more passivation layers are formed above the ohmic contact.
  • a via hole is formed in the one or more passivation layers such that interconnect metal may be deposited and couple to the ohmic contact.
  • the interconnect via is formed off-center from the middle axis of the ohmic contact.
  • a “wing” is formed above the one or more passivation layers, and one or more plugs may be formed above the wing of interconnect metal.
  • the one or more plugs are formed off-center from the center axis of the ohmic contact, opposite the hole created by the interconnect via. As will be shown, the layout of the plugs and via hole may alternate around the center axis.
  • FIG. 1A is a cross-sectional side view of an example semiconductor device 100 , which may use an asymmetrical plug interconnect structure.
  • Semiconductor device 100 includes substrate 102 , first active layer 104 , second active layer 108 , gate dielectric 110 , gate 112 , contacts 114 and 116 , passivation/interconnect region 118 , and planarized surface 120 .
  • layer of electrical charge 106 may form between (or proximate to the interface of) first active layer 104 and second active layer 108 due to the bandgap energy difference between the two layers. Layer of electrical charge 106 may define the lateral conductive channel.
  • the layer of electrical charge 106 includes a two-dimensional electron gas (2DEG), since electrons are free to move in two dimensions but are tightly confined in the third dimension.
  • first active layer 104 is sometimes called a channel layer while second active layer 108 is sometimes called the barrier layer or donor layer.
  • First active layer 104 is disposed over the substrate 102 .
  • Second active layer 108 is disposed on first active layer 104 .
  • Gate dielectric layer 110 is disposed on second active layer 108 .
  • Gate 112 is formed atop gate dielectric layer 110 , while contacts 114 and 116 are shown as extending vertically down through gate dielectric 110 to electrically connect to second active layer 108 .
  • Contact 114 may be a drain contact while contact 116 may be a source contact.
  • source and drain ohmic contacts 114 and 116 are laterally spaced-apart, with gate 112 being disposed between source and drain contacts 114 and 116 .
  • First active layer 104 is disposed over substrate 102 , and substrate 102 may be formed from materials such as sapphire (Al 2 O 3 ), silicon (Si), or silicon carbide (SiC). Various techniques of fabrication may call for layers of other materials to be disposed between substrate 102 and first active layer 120 to facilitate the construction of the device.
  • First active layer 104 may include a first semiconductor material having a first bandgap.
  • first active layer 104 may include semiconductor materials containing nitride compounds of group III elements.
  • first active layer 104 may be grown or deposited on substrate 102 and may include GaN.
  • Second active layer 108 may include a second semiconductor material (e.g., aluminum gallium nitride (AlGaN)) having a second bandgap that is different than the first bandgap of first active layer 104 .
  • a second semiconductor material e.g., aluminum gallium nitride (AlGaN)
  • AlGaN aluminum gallium nitride
  • different group III nitride semiconductor materials such as aluminum indium nitride (AlInN) and aluminum indium gallium nitride (AlInGaN)
  • second active layer 108 may include a non-stoichiometric compound (e.g., a group III nitride semiconductor material, such as AlXGa1-XN, where 0 ⁇ X ⁇ 1). In such materials, the ratios of the elements are not easily represented by ordinary whole numbers.
  • Second active layer 108 may be grown or deposited on first active layer 104 .
  • Gate dielectric 110 may include silicon nitride (SiN) or Si 3 N 4 . In other examples, different nitride-based compounds, such as carbon nitride (CN) or boron nitride (BN), may be used for gate dielectric 110 . Although FIG. 1A illustrates a single gate dielectric 110 , it should be appreciated that multiple gate dielectric layers may be used, and can include other oxide materials such as aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium Oxide (ZrO 2 ), etc. Gate dielectric 110 may be deposited through atomic layer deposition (ALD), or the like.
  • ALD atomic layer deposition
  • gate 112 contacts the gate dielectric 110 and may include a gold nickel (NiAu) stack. In another example, gate 112 may include a titanium gold (TiAu) stack or molybdenum gold (MoAu) stack. In operation, gate 112 controls the forward conduction path between drain terminal (contact 116 ) and source terminal (contact 114 ). Contact 116 and contact 114 may include titanium (Ti), molybdenum (Mo), aluminum (Al), or gold (Au). Above the contacts 114 / 116 and drain 112 is a passivation/interconnect region 118 . The passivation/interconnect region 118 may include one or more passivation layers, oxide layers, and interlayer dielectrics (ILDs).
  • ILDs interlayer dielectrics
  • the thickness of the passivation/interconnect region 118 is shown as Z 1 121 .
  • the thickness Z 1 121 may be 3.7 ⁇ m or more.
  • metal layers may be disposed on planarized surface 120 at the top of passivation/interconnect region 118 .
  • the asymmetric plug interconnect structure (not shown) is within the passivation/interconnect region 118 and couples to contacts 114 and 116 .
  • FIG. 1B is a cross-sectional side view of an example semiconductor device 101 , which may use an asymmetrical plug interconnect structure.
  • Semiconductor device 101 includes substrate 102 , first active layer 104 , second active layer 108 , gate dielectric 110 , gate 112 , ohmic contacts 114 and 116 , passivation/interconnect region 118 , and planarized surface 120 .
  • the structure shown for semiconductor device 101 of FIG. 1B is similar to semiconductor device 100 shown in FIG. 1A ; however, semiconductor device 101 may be formed using a gold-free process. It should be appreciated that similarly named and numbered elements couple and function as described above; however, in FIG.
  • ohmic contacts 114 and 116 extend through the gate dielectric 110 , second active layer 108 , first active layer 104 , and intercept electrical charge layer 106 .
  • An Ohmic contact forms where the metal of contacts 114 / 116 intercepts the electrical charge layer 106 .
  • Gate 112 may include titanium (Ti), titanium nitride (TiN), and aluminum copper (AlCu), while contacts 114 and 116 may include titanium (Ti), aluminum (Al) or titanium nitride (TiN).
  • a portion of contacts 114 and 116 sits atop the second active layer 108 , while another portion of contacts 114 and 116 extends through second active layer 108 , first active layer 104 , and electrical charge layer 106 .
  • the width of the portion of contacts 114 and 116 that extends through the second active layer 108 , first active layer 104 , and the electrical charge layer 106 is substantially 2-10 ⁇ m.
  • the length of the portion of contacts 114 and 116 , that sits atop second active layer 108 is substantially 0.5 ⁇ m.
  • each contact 114 and 116 has two portions that sit atop second active layer 108 .
  • FIG. 2 is a cross-sectional side view if an example semiconductor device 200 with an asymmetric plug interconnect structure.
  • Semiconductor device 200 may include active device 203 (e.g., a simplified view of the semiconductor structure shown in FIGS. 1A and 1B , including the first and second active layers, e.g., GaN/AlGaN, and the electrical charge layer, e.g., 2DEG), gate dielectric 210 , contact 216 , passivation layer 222 , silicon dioxide remnant 224 , interlayer dielectric (ILD) 226 , interconnect metal 228 , and plugs 230 and 232 . Further shown in FIG.
  • active device 203 e.g., a simplified view of the semiconductor structure shown in FIGS. 1A and 1B , including the first and second active layers, e.g., GaN/AlGaN, and the electrical charge layer, e.g., 2DEG
  • gate dielectric 210 gate dielectric 210
  • the asymmetric plug interconnect structure includes interconnect 228 and plugs 230 and 232 .
  • contact region (e.g., the structure of metals and semiconductors used to contact active device 203 ) includes contact 216 extending through gate dielectric 210 and second active layer, into the first active layer.
  • Contact 216 may be coupled to the layer of electrical charge (see e.g., layer of electrical charge 106 in FIGS. 1A and 1B ).
  • Passivation layer 222 is disposed proximate to contact 216 and gate dielectric 210 , and at least part of contact 216 is disposed between passivation layer 222 and the second active layer (in active device 203 ).
  • contact 216 forms an ohmic contact with active device 203 .
  • contact 216 is electrically coupled to supply/withdraw electrons from the electrical charge layer (e.g., electrical charge layer 106 of FIG. 1A ).
  • Interconnect 228 extends through passivation layer 222 , and is coupled to contact 216 .
  • a first portion of interconnect 228 e.g., the “wing” portion of interconnect 228 that is disposed on, and substantially coplanar with, passivation layer 222
  • passivation layer 222 is disposed so that passivation layer 222 is positioned between the first portion of interconnect 228 and the second active layer.
  • the first portion of interconnect 228 is substantially laterally coextensive with a first side of contact 216 .
  • a second portion of interconnect 228 extends through passivation layer 222 to electrically couple to contact 216 .
  • the second portion of interconnect 228 substantially forms a trapezoid, where a first parallel side of the trapezoid includes metal and is coupled to contact 216 .
  • nonparallel sides of the trapezoid include the metal and are in contact with passivation layer 222 .
  • the second parallel side of the trapezoid includes an oxide (e.g., remnant 224 ) and is larger than the first parallel side.
  • interlayer dielectric 226 is disposed proximate to interconnect 228
  • the first portion of interconnect 228 is disposed between interlayer dielectric 226 and passivation layer 222 .
  • Plug 230 and plug 232 extend into interlayer dielectric 226 , and are coupled to the first portion (e.g., the “wing”) of interconnect 228 .
  • contact 216 (which may include metal) partially sits on top of the gate dielectric layer 210 to form an Ohmic contact with the electrical charge layer in a gold-free process. However, contact 216 can sit on top of the active device 203 when a gold-based process is used.
  • passivation layer 222 is disposed above the gate dielectric layer 210 , contact 216 .
  • Passivation layer 222 may include a nitride-based compound, such as silicon nitride SiN. Although only one passivation layer 222 is shown, multiple passivation layers may be used. Multiple passivation layers may also be interlaced with oxide layers or the like. Passivation/oxide/ILD layers may be deposited using plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • interconnect 228 is disposed above contact 216 and extends through passivation layer 222 .
  • Via footprint 240 defines the sidewall/trench of interconnect metal 228 .
  • via footprint 240 is offset from the center of the contact 216 (axis A 238 ).
  • the center of via footprint 240 is offset from axis A 238 by the distance d 2 243 .
  • the width of the footprint is shown as distance d 1 242 .
  • the width d 1 242 of the via footprint 240 defines the bottom width of the trench. The top of the trench is wider than the width d 1 242 because of the formation process of the via.
  • the metal used for interconnect 228 also forms a “wing” (e.g., the first portion of interconnect 228 ) on the opposite side of the via along axis A 238 .
  • the wing of interconnect 228 is the metal portion of the interconnect 238 which sits above the passivation layer 222 .
  • Interconnect 228 is used to couple the contact 216 to other metal layers, which are disposed on the planarized surface 220 (along with plugs 230 and 232 ).
  • silicon dioxide remnant 224 is disposed above the passivation layer 222 and fills the via/trench created by the interconnect metal 228 .
  • Tetraethyl orthosilicate (TEOS) may be used to deposit the silicon dioxide to form silicon dioxide remnant 224 .
  • the silicon dioxide could be deposited using saline-based or disaline-based processes.
  • the silicon dioxide formed using TEOS is generally of lower density and may be utilized for electrical blockage.
  • interlayer dielectric (ILD) 226 e.g., an oxide
  • ILD interlayer dielectric
  • the top of interlayer dielectric oxide 226 is planarized to result in planarized surface 220 .
  • plugs 230 and 232 are disposed through the ILD 226 to contact interconnect 228 .
  • Plugs 230 and 232 are attached to interconnect 228 and are disposed in the planarized surface 220 (to couple to other metals layers).
  • plugs 230 and 232 are tungsten plugs with depth Z 2 248 .
  • the depth of plugs 230 and 232 are generally limited by the process.
  • the depth Z 2 248 of plug 230 is substantially double the width of plug 230 .
  • the total thickness from gate dielectric 210 to planarized surface 220 is shown as thickness Z 1 221 .
  • plugs 230 and 232 are deep enough to reach the wing of interconnect 228 at approximately the depth of the ILD oxide 226 , which is much smaller than the thickness Z 1 221 and shown as depth Z 2 248 . This allows simplification of the manufacturing process for the semiconductor device 200 .
  • FIG. 3A is a top down view of an example layout of semiconductor device 300 with an asymmetric plug interconnect structure and alternating via/plug layout.
  • Semiconductor device 300 includes a portion of active device 303 , contact region 399 , an ohmic contact/metal drain footprint 314 , ohmic contact/metal source footprint 316 , plug footprints 331 A, 331 B, and 331 C for the source, plug footprints 333 A, 333 B, and 333 C for the drain, via footprints 340 A, 340 B, and 340 C for the source, and via footprints 341 A, 341 B, and 341 C for the drain. Further shown in FIG. 3A is also the distance d 1 342 , which is one example of the width of the via footprint for the drain.
  • contact region 399 is included in at least one of a source region (e.g., source contact 316 ) or a drain region (e.g., drain contact 314 ) of the HFET—in the depicted example, multiple contact regions 398 / 399 are included in both the source and drain electrodes and are vertically (with respect to the page orientation) aligned. Also, plugs 331 C in contact region 399 are disposed closer to the first side (right hand side of page) of the HFET than second plugs 331 B included in a second contact region 398 which are disposed closer to the second side (left hand side) of the HFET. In other words, an orientation of second contact region 398 is a mirror image of contact region 399 .
  • plugs 331 A/ 331 B/ 331 C have a width and a length, where the length of the plug is larger than the width. As shown previously in other figures, the height of plugs 331 A/ 331 B/ 331 C is greater than or equal to a thickness of the interlayer dielectric.
  • the depicted example outlines (large dashed box) a portion of the active device: active area 303 (e.g., first and second active layer and the electrical charge layer).
  • active area 303 e.g., first and second active layer and the electrical charge layer.
  • a first solid line illustrates the top down outline of drain contact 314 (e.g., the ohmic contact/metal for the drain). As shown, drain contact 314 is generally finger shaped.
  • a second solid line illustrates the top down outline of source contact 316 (e.g., the ohmic contact/metal for the source). As shown, source contact 316 is generally finger shaped.
  • Via footprint for 340 A, 340 B, 340 C and plug outline 331 A, 331 B, and 331 C for the source 316 are also depicted.
  • the top down outline for the grouping of plugs 331 A, 331 B, and 331 C is bar shaped.
  • each grouping of plugs 331 A, 331 B, and 331 C includes two bars.
  • the via footprints 340 A, 340 B, and 340 C are alternated with the grouping of plugs 331 A, 331 B, and 331 C.
  • Via outline 340 A is on the left side of source contact 316 while grouping of plugs 331 A is on the right side of source contact 316 .
  • via outline 340 B is on the right side of source contact 316 while the grouping of plugs 331 B is on the left side (e.g., a mirror image of plugs 331 A).
  • via outline 340 C is on the left side while the grouping of plugs 331 C is on the right side of source contact 316 . This mirrored pattern may continue for the entire length of the source contact 316 .
  • cross-section B-B′ is also shown across via footprint 340 A and the grouping of plugs 331 A.
  • the example semiconductor device 200 shown in FIG. 2 may be one example of the semiconductor device in the cross-section B-B′.
  • Via footprint for 341 A, 341 B, 341 C and plug outline 333 A, 333 B, and 333 C for the drain contact 314 are also depicted.
  • plugs 333 A, 333 B, and 333 C are bar shaped.
  • Each grouping of plugs 333 A, 333 B, and 333 C includes three bars.
  • the width of drain contact 314 is wider than the width of source contact 316 . Accordingly, more plugs may be included in drain contact 314 .
  • the via footprints 341 A, 341 B, 341 C are alternated with the grouping of plugs 333 A, 333 B, and 333 C.
  • Via outline 341 A is on the left side of drain contact 314 while grouping of plugs 333 A is on the right side of source contact 316 . Conversely, while via outline 341 B is on the right side of drain contact 314 , while the grouping of plugs 333 B is on the left side. Further, via outline 341 C is on the left side while grouping of plugs 333 C is on the right side of drain contact 314 . This pattern may be repeated for the entire length of drain 314 . The cross-section along C-C′ of the drain is shown in FIG. 3B .
  • FIG. 3B is a cross-sectional side view of another example semiconductor device 301 with an asymmetric plug interconnect structure.
  • Semiconductor device 301 is cut along the cross-section C-C′ in FIG. 3A and includes an asymmetric plug interconnect structure.
  • the structure includes active device 303 , gate dielectric 310 , ohmic contact 314 , passivation layer 322 , silicon dioxide (TEOS) remnant 324 , interlayer dielectric (ILD) 326 , interconnect metal 328 , and plugs 330 , 332 and 334 . Further shown in FIG.
  • the active device 303 may include the first and second active layers and electrical charge layer discussed in connection with FIGS. 1A and 1B .
  • the asymmetric plug interconnect structure includes interconnect 328 and plugs 330 , 332 , and 334 . Similarly named and numbered elements couple and function as described above; however, three plugs ( 330 , 332 , and 334 ) are illustrated instead of the two plugs shown in FIG. 2 .
  • axis A 338 represents the center of ohmic contact 314 .
  • Depth Z 1 321 represents depth from the planarized surface 320 to the gate dielectric layer 310 .
  • Depth Z 2 348 represents depth of plugs 330 , 332 , 334 , or the distance from the planarized surface 320 to the TEOS derived silicon oxide 324 .
  • Distance d 1 342 represents the width of the via used to create the trench for interconnect 328 .
  • the minimum for distance d 1 342 may be substantially 2 ⁇ m.
  • Distance d 2 343 represents the distance between the center of the via for interconnect 328 and axis A 338 . In one example, distance d 2 343 is substantially 1 ⁇ 4 of distance d 3 334 .
  • Distance d 3 334 represents the length of contact 314 .
  • interconnect 328 may have substantially the same length of contact 314 . However, it should be appreciated that the “wing” of interconnect 328 may extend beyond distance d 3 334 to form the field plate for contact 314 .
  • Distance d 4 345 represents the distance between the end of the wing of interconnect 328 and plug 334 . This distance may be determined by the processing steps used to fabricate the architectures depicted.
  • Distance d 4 345 may be substantially zero and plug 334 starts at the edge of the “wing” of interconnect 328 . However, distance d 4 345 is dependent on the topography capability of the process to deposit the plugs. Distance d 4 345 may be 0.5 ⁇ m.
  • Distance d 5 346 represents the width of the plug opening. Plugs 330 , 332 , 334 are wider at the top (planarized surface 320 ) and taper towards the bottom. In one example, the ratio of the depth of the plug (Z 2 348 ) to the width of the plug opening at the planarized surface 320 is substantially two. In other words, distance d 5 346 is substantially half of the depth Z 2 348 . In one example, the distance d 5 346 is substantially 1 ⁇ m.
  • Distance d 6 347 represents the distance between each plug. In one example, the distance is substantially 0.6 ⁇ m.
  • FIG. 4 is a top down view of another example layout of semiconductor device 400 with an asymmetric plug interconnect structure and alternating via/plug layout.
  • Semiconductor device 400 includes a portion of the active device 403 , ohmic contact/metal drain footprint 414 , ohmic contact/metal source footprint 416 , contact region 499 , plug footprints 431 A, 431 B, and 431 C for the source, plug footprints 433 A, 433 B, and 433 C for the drain, via footprints 440 A, 440 B, and 440 C for the source, and via footprint 441 A, 441 B, and 441 C for the drain. Further shown in FIG. 4 is distance d 1 442 , which is one example of the width of the via footprint for source contact 416 .
  • FIG. 4 is similar to FIG. 3A ; however, instead of a long continuous bar for the plugs, the plugs shown include a grouping of circles in a line.
  • the cross-section shown in FIG. 2 may be one example of semiconductor device 400 at cross-section D-D′.
  • the cross-section shown in FIG. 3B may be one example of semiconductor device 400 at cross-section E-E′.
  • FIG. 5 is a top level view of an example layout of semiconductor device 500 with an asymmetric plug interconnect structure and alternating via/plug layout.
  • Semiconductor device 500 includes a portion of active device 503 , ohmic contact/metal drain footprint 514 , ohmic contact/metal source footprint 516 , contact region 599 , plug footprint 531 for the source, plug footprint 533 for the drain, via footprints 540 A and 540 B for the source, and via footprints 541 A and 541 B for the drain. Further shown in FIG. 5 is distance d 1 542 , which is one example of the width of the via footprint for the source contact 516 .
  • FIG. 5 is similar to FIG. 3A and FIG. 4 , however, the via and plugs alternate in a different lateral direction than the via and plugs shown in FIG. 3A and FIG. 4 .
  • the cross-section of the semiconductor device 500 is similar to the cross-section of the semiconductor devices shown in FIG. 2 and FIG. 3B ; however, the device shown in FIG. 5 may have more plugs. For the example shown, there may be six plugs illustrated in the cross-section on the wing of the asymmetrical plug interconnect structure.
  • FIG. 6 is an example process flow for fabricating a semiconductor device with an asymmetric plug interconnect structure.
  • One of ordinary skill in the art having the benefit of the present disclosure will appreciate that the process flow depicted can occur in any order and even in parallel. Additionally, blocks may be added to, and removed from, the process flow in accordance with the teachings of the present disclosure.
  • Block 602 illustrates forming the active device including the first and second active layer, and the electrical charge layer.
  • the gate dielectric may also be formed.
  • the gate dielectric is disposed on a surface of the semiconductor material, and the second active layer is disposed between the gate dielectric and the first active layer.
  • Block 604 shows forming a via for an ohmic contact to the semiconductor material.
  • the via may be etched using inductively coupled plasma (ICP), or the like.
  • ICP inductively coupled plasma
  • the trench that is etched may extend through the gate dielectric, second active layer, and into the first active layer.
  • Block 606 depicts depositing the metal to form a contact.
  • a metal is deposited using physical vapor deposition (PVD) and the metal lines the walls of the trench formed in block 604 .
  • the metal may extend from the gate oxide to the first active layer.
  • Block 608 illustrates annealing the metal of the contact between the metal and semiconductor using rapid thermal annealing (RTA) or the like.
  • RTA rapid thermal annealing
  • Block 610 shows depositing passivation and interlayer dielectrics (ILDs). These layers may be deposited using plasma-enhanced chemical vapor deposition (PECVD).
  • PECVD plasma-enhanced chemical vapor deposition
  • Block 612 depicts forming a via for the interconnect. This may be achieved by etching a trench through the passivation layer, and the trench may reach the contact.
  • Block 614 illustrates depositing the metal for the interconnect in the via/trench formed in block 612 .
  • interconnect metal is deposited using physical vapor deposition (PVD).
  • the metal may be deposited in the trench, and on the passivation layer, to form the interconnect.
  • the metal may line the walls of the trench (in a second portion of the interconnect), and (in a first “wing” portion of the interconnect) the metal is substantially coplanar with the passivation layer.
  • the interconnect may extend through the first passivation layer and electrically couple to the first contact.
  • the first portion of the interconnect is disposed on the passivation layer so that the passivation layer is disposed between the first portion of the interconnect and the second active layer. It should be appreciated that in some examples, blocks 610 , 612 , and 614 may be repeated for multiple passivation layers.
  • Block 616 illustrates depositing silicon oxide using tetraethyl orthosilicate (TEOS).
  • TEOS tetraethyl orthosilicate
  • Block 616 illustrates depositing silicon oxide using tetraethyl orthosilicate (TEOS).
  • TEOS tetraethyl orthosilicate
  • silicon dioxide could be deposited using saline or disilane.
  • Block 618 shows planarizing residual silicon oxide from the TEOS deposition.
  • planarization may be done using a resist etch back (REB) process or chemical-mechanical planarization (CMP) process.
  • REB resist etch back
  • CMP chemical-mechanical planarization
  • Block 620 depicts depositing the interlayer dielectric proximate to the interconnect.
  • the first portion of the interconnect is disposed between the interlayer dielectric and the passivation layer.
  • Block 622 illustrates forming the plug by etching, depositing, and then planarizing the top surface of the plug.
  • the trench that is etched may have a width, a length, and a height, where the length of the trench is larger than the width, and the height is equal to a thickness of the interlayer dielectric.
  • ICP Inductively coupled plasma
  • CMP CMP
  • Planarizing may be used to remove residual metal disposed on the surface of the interlayer dielectric.
  • a first plug may be disposed closer to a first side of the HFET than a second plug in a second contact region, and the second plug is disposed closer to a second side, opposite the first side, of the HFET.
  • the orientation of the second contact region may be a mirror image of the first contact region.

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US15/713,457 US10204791B1 (en) 2017-09-22 2017-09-22 Contact plug for high-voltage devices
JP2018175459A JP7285629B2 (ja) 2017-09-22 2018-09-19 ＧａＮデバイスのための非対称プラグ技術
TW112124478A TWI850004B (zh) 2017-09-22 2018-09-19 用於氮化鎵裝置之非對稱插塞技術
TW111127106A TWI807925B (zh) 2017-09-22 2018-09-19 用於氮化鎵裝置之非對稱插塞技術
TW107132951A TWI773828B (zh) 2017-09-22 2018-09-19 用於氮化鎵裝置之非對稱插塞技術
EP18195756.4A EP3460841B1 (en) 2017-09-22 2018-09-20 Asymmetrical plug-interconnect structure for gan devices
CN201811108439.0A CN109616521B (zh) 2017-09-22 2018-09-21 用于GaN器件的非对称塞块技术
CN202410360127.8A CN118315420A (zh) 2017-09-22 2018-09-21 一种高电子迁移率晶体管
US16/221,027 US10665463B2 (en) 2017-09-22 2018-12-14 Asymmetrical plug technique for GaN devices
US16/857,049 US11373873B2 (en) 2017-09-22 2020-04-23 Asymmetrical plug technique for GaN devices
US17/824,287 US11776815B2 (en) 2017-09-22 2022-05-25 Asymmetrical plug technique for GaN devices

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EP3460841B1 (en) 2021-11-03
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CN109616521B (zh) 2024-03-08
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US10665463B2 (en) 2020-05-26
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US20220406607A1 (en) 2022-12-22
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