TWI835915B - 金屬閘極電晶體的製作方法 - Google Patents

金屬閘極電晶體的製作方法 Download PDF

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TWI835915B
TWI835915B TW108140046A TW108140046A TWI835915B TW I835915 B TWI835915 B TW I835915B TW 108140046 A TW108140046 A TW 108140046A TW 108140046 A TW108140046 A TW 108140046A TW I835915 B TWI835915 B TW I835915B
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layer
gate
substrate
dielectric layer
metal gate
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李志成
陳威任
李凱霖
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聯華電子股份有限公司
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Abstract

一種金屬閘極電晶體的製作方法包含提供一基底,一層間介電層覆蓋基底,一虛置閘極埋入層間介電層,一高介電常數層位在虛置閘極和基底之間,接著移除虛置閘極以形成一溝渠,其中高介電常數層由溝渠曝露出來,在移除虛置閘極之後,進行一離子植入製程,將氟離子植入高介電常數層,最後在離子植入製程之後,形成一金屬閘極填入溝渠。

Description

金屬閘極電晶體的製作方法
本發明係關於一種金屬閘極電晶體的製作方法,特別是有關於一種在移除虛置閘極後,將氟離子植入高介電常數層的製作方法。
在習知半導體產業中,多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor,MOS)電晶體中,作為標準的閘極填充材料選擇。然而,隨著MOS電晶體尺寸持續地微縮,傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低,及其難以避免的空乏效應(depletion effect)等問題,使得等效的閘極介電層厚度增加、閘極電容值下降,進而導致元件驅動能力的衰退等困境。
因此,半導體業界更嘗試以新的閘極填充材料,例如利用金屬閘極來取代傳統的多晶矽閘極,用以作為匹配高介電常數(High-K)閘極介電層的控制電極。然而在閘極介電層形成時,不可避免的會產生晶格缺陷(defect)或晶格空位(vacancy),這些缺陷或空位可能會影響後續形成的電晶體效能。
有鑑於此,本發明提供一種金屬閘極電晶體的製作方法以解決上述晶格缺陷和晶格空位的問題。
根據本發明之一較佳實施例,一種金屬閘極電晶體的製作方法包含:首先提供一基底,一層間介電層覆蓋基底,一虛置閘極埋入層間介電層,一高介電常數層位在虛置閘極和基底之間,接著移除虛置閘極以形成一溝渠,其中高介電常數層由溝渠曝露出來,在移除虛置閘極之後,進行一離子植入製程,將氟離子植入高介電常數層,最後在離子植入製程之後,形成一金屬閘極填入溝渠。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
第1圖至第5圖為根據本發明之一較佳實施例所繪示的金屬閘極電晶體的製作方法。
如第1圖所示,首先提供一基底10,基底10可以為一矽基底、一鍺基底、一砷化鎵基底、一矽鍺基底、一磷化銦基底、一氮化鎵基底、一碳化矽基底或是一矽覆絕緣基底。此外如第6圖所示,基底10可以為凸出於一基板10a上的鰭狀結構。
請再度參閱第1圖,在基底10上依序形成一閘極介電層12、一高介電常數層14、一虛置閘極16和一上蓋層18,閘極介電層12包含氧化矽、氮化矽、氮碳化矽、氮氧化矽、氮碳氧化矽或其它絶緣材料,高介電常數層14包含氧化鋁、氧化鋯、鈦酸鍶鋇(barium strontium titanate, BST)、鋯鈦酸鉛(lead zirconate titanate, PZT)、矽酸鋯(ZrSiO4 )、氧化矽鉿(HfSiO2 )、氮氧化矽鉿(HfSiON)或氧化鉭。虛置閘極16包含多晶矽或其它含矽材料層。上蓋層18包含氮化矽或氧化矽。閘極介電層12、高介電常數層14、虛置閘極16和上蓋層18可以使用化學氣相沉積製程、物理氣相沉積製程或原子層沉積製程製作。
之後在閘極介電層12、高介電常數層14、虛置閘極16和上蓋層18的周圍形成一襯墊層20和一側壁子22,襯墊層20可以為氧化矽,較佳地襯墊層20係利用加熱製程製作,側壁子22可以包含氧化矽、氮化矽、氮碳化矽、氮氧化矽、氮碳氧化矽或其它絶緣材料,側壁子22可以利用沉積製程加上蝕刻製程完成。形成側壁子22之後,在虛置閘極16兩側的基底10內,各自形成一源極/汲極摻雜區24。源極/汲極摻雜區24可以利用在基底10中植入N型或P型摻質來形成,在另一較佳實施例,源極/汲極摻雜區24使用選擇性磊晶成長製程(Selective Epitaxial Growth, SEG)形成一或多層之半導體材料層,例如矽、鍺、鍺化矽或碳化矽等。
如第2圖所示,形成一蝕刻停止層26順應的覆蓋基底10、側壁子22和上蓋層18,蝕刻停止層26可以包含氮化矽或氮碳化矽,接著再形成一層間介電層28覆蓋蝕刻停止層26,層間介電層28可以為矽玻璃(PSG)或硼磷矽玻璃(BPSG)等氧化矽材料。如第3圖所示,平坦化層間介電層28和蝕刻停止層26直至曝露出虛置閘極16,層間介電層28和蝕刻停止層26可以利用化學機械研磨的方式來進行平坦化。如第4圖所示,移除虛置閘極16後形成一溝渠30,由溝渠30曝露出高介電常數層14,然後以層間介電層28、蝕刻停止層26、側壁子22和襯墊層20為遮罩,進行一離子植入製程32,將氟離子植入高介電常數層14。根據本發明之一較佳實施例,在進行離子植入製程32時,氟離子亦植入閘極介電層12。此外根據本發明之一較佳實施例,離子植入製程32所使用的植入能量為6000電子伏特,植入的氟離子濃度(dosage)為5E15 原子個數/平方公分,依據閘極介電層12或高介電常數層14的厚度不同,植入能量和氟離子的濃度可以調整。
如第5圖所示,在離子植入製程32之後,形成一金屬閘極34填入溝渠30,此時本發明之金屬閘極電晶體100業已完成。金屬閘極34可以為單層金屬層或複合金屬層,例如鋁(Al)、鈦(Ti)、鉭(Ta)、鎢(W)、鈮(Nb)、鉬(Mo)、銅(Cu)、氮化鈦(TiN)、碳化鈦(TiC)、氮化鉭(TaN)、鈦鎢(Ti/W)、或鈦與氮化鈦(Ti/TiN),此外,在金屬閘極34和高介電常數層14之間,可以視所製作的電晶體的導電型態而設置不同的功函數金屬層(圖未示),若是P型電晶體,功函數金屬層可為一滿足P型電晶體所需功函數要求的金屬,例如氮化鈦(TiN)、碳化鈦(TiC)、氮化鉭TaN)、碳化鉭(TaC)、碳化鎢(WC)、或氮化鋁鈦(TiAlN)。若是N型電晶體時,功函數金屬層可為一滿足N型電晶體所需功函數要求的金屬,例如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)或鋁化鉿(HfAl)。
本發明利用將氟離子植入高介電常數層和閘極介電層中,以修補在高介電常數層和閘極介電層中的晶格缺陷或晶格空位,在修補晶格缺陷或晶格空位後,本發明所形成的金屬閘極的電晶體其汲極引發位能障下降(Drain Induced Barrier Lowering, DIBL)的情況會降低,閃爍雜訊(Flicker Noise)和負偏壓溫度不穩定性(Negative Bias Temperature Instability, NBIT)也會減少,如此一來就可以增加本發明之金屬閘極電晶體的效能。
此外,根據其它的實施例,若是對於一般的多晶矽閘極電晶體,氟離子還可以在其它的時點植入,例如在形成多晶矽閘極之前將氟離子植入高介電常數層或閘極介電層,或者是在形成多晶矽閘極之後讓氟離子穿過多晶矽閘極植入高介電常數層或閘極介電層,然而,在氟離子植入之後,還需要形成源極/汲極摻雜區等製程,這些製程需要加熱,如此就會移動已植入的氟離子的位置,甚至使氟離子離開高介電常數層或閘極介電層進入基底,導至後續電晶體的電性問題。
本發明是針對金屬閘極電晶體所使用的製程,在移除虛置閘極後才將氟離子植入高介電常數層和閘極介電層中,由於在移除虛置閘極之前,一些加熱製程如源極/汲極摻雜區的驅入(drive in)製程都已經完成,所以氟離子植入之後就不會再遭受其它的加熱製程影響,如此就可以確保氟離子維持在高介電常數層和閘極介電層中,再者由於本發明的氟離子不需要穿過虛置閘極後才植入高介電常數層和閘極介電層,因此所使用的植入能量可以比較小,如此一來可以把氟離子植入的位置控制的較準確,不會植入過深。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10:基底 10a:基板 12:閘極介電層 14:高介電常數層 16:虛置閘極 18:上蓋層 20:襯墊層 22:側壁子 24:源極/汲極摻雜區 26:蝕刻停止層 28:層間介電層 30:溝渠 32:離子植入製程 34:金屬閘極 100:金屬閘極電晶體
第1圖至第5圖為根據本發明之一較佳實施例所繪示的金屬閘極電晶體的製作方法。 第6圖為根據本發明之一較佳實施例所繪示的鰭狀結構示意圖。
10:基底
12:閘極介電層
14:高介電常數層
20:襯墊層
22:側壁子
24:源極/汲極摻雜區
26:蝕刻停止層
28:層間介電層
30:溝渠
32:離子植入製程

Claims (6)

  1. 一種金屬閘極電晶體的製作方法,包含: 提供一基底,一層間介電層覆蓋該基底,一虛置閘極埋入該層間介電層,一高介電常數層位在該虛置閘極和該基底之間; 移除該虛置閘極以形成一溝渠,其中該高介電常數層由該溝渠曝露出來; 在移除該虛置閘極之後,進行一離子植入製程,將氟離子植入該高介電常數層;以及 在該離子植入製程之後,形成一金屬閘極填入該溝渠。
  2. 如請求項1所述之金屬閘極電晶體的製作方法,其中一閘極介電層設置於該高介電常數層和該基底之間。
  3. 如請求項2所述之金屬閘極電晶體的製作方法,其中在進行該離子植入製程時,該氟離子植入該閘極介電層。
  4. 如請求項2所述之金屬閘極電晶體的製作方法,其中該閘極介電層包含氧化矽、氮化矽、氮碳化矽、氮氧化矽或氮碳氧化矽。
  5. 如請求項1所述之金屬閘極電晶體的製作方法,其中該高介電常數層包含氧化鋁、氧化鋯、鈦酸鍶鋇、鋯鈦酸鉛、矽酸鋯、氧化矽鉿、氮氧化矽鉿或氧化鉭。
  6. 如請求項1所述之金屬閘極電晶體的製作方法,其中二個源極/汲極摻雜區分別設置在該虛置閘極兩側的該基底中。
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US17/402,608 US11652154B2 (en) 2019-11-05 2021-08-15 Method of fabricating metal gate transistor
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