TWI801962B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI801962B
TWI801962B TW110129744A TW110129744A TWI801962B TW I801962 B TWI801962 B TW I801962B TW 110129744 A TW110129744 A TW 110129744A TW 110129744 A TW110129744 A TW 110129744A TW I801962 B TWI801962 B TW I801962B
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Taiwan
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metal
film
semiconductor device
metal pad
layer
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TW110129744A
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English (en)
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TW202238921A (zh
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藤井光太郎
渡辺慎也
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日商鎧俠股份有限公司
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Publication of TW202238921A publication Critical patent/TW202238921A/zh
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    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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Abstract

實施形態提供一種可靠性提高之半導體裝置。 實施形態之半導體裝置具備：第1基板，其包含第1金屬層、及包圍第1金屬層之第1絕緣層；及第2基板，其包含與第1金屬層相接之第2金屬層、包圍第2金屬層且與第1絕緣層相接之第2絕緣層、及一部分設置於第2金屬層中且於自第2金屬層朝第1金屬層之第1方向延伸之第1導電體。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
貼合技術例如藉由將分別形成有電子電路之2片晶圓貼合，而實現高功能或高積體之半導體器件。例如，藉由切割將半導體晶圓分割成複數個晶片，而實現高功能或高積體之半導體記憶體，且上述半導體晶圓藉由將形成有記憶胞陣列之半導體晶圓、與形成有控制記憶胞陣列之控制電路之半導體晶圓貼合，其後施加熱處理接合而成。
於使用貼合技術製造之半導體器件中，期望提高可靠性。
本發明之實施形態提供一種可靠性提高之半導體裝置。
實施形態之半導體裝置具備：第1基板：其包含第1金屬層、及包圍上述第1金屬層之第1絕緣層；及第2基板，其包含與上述第1金屬層相接之第2金屬層、包圍上述第2金屬層且與上述第1絕緣層相接之第2絕緣層、及一部分設置於上述第2金屬層中且於自上述第2金屬層朝上述第1金屬層之第1方向延伸之第1導電體。
以下，參照圖式且說明本發明之實施形態。另，於以下之說明中，有對相同或類似之構件等標注相同符號，對已說明過一次之構件等適當省略其說明之情形。
又，本說明書中，為方便起見，有使用「上」或「下」等用語之情形。「上」或「下」例如係顯示圖式內之相對位置關係之用語。「上」或「下」等用語未必為規定相對於重力之位置關係之用語。
構成本說明書中之半導體裝置之構件之化學組成之定性分析及定量分析例如可藉由次級離子質譜分析(Secondary Ion Mass Spectrometry：SIMS)、能量分散型X射線光譜術(Energy Dispersive X-ray Spectroscopy：EDX)進行。又，對於構成半導體裝置之構件之厚度、構件間之距離等測定，可使用例如透過型電子顯微鏡(Transmission Electron Microscope：TEM)或掃描型電子顯微鏡(Scanning Electron Microscope：SEM)。
(第1實施形態) 第1實施形態之半導體裝置具備：第1基板，其包含第1金屬層、與包圍第1金屬層之第1絕緣層；及第2基板，其包含與第1金屬層相接之第2金屬層、包圍第2金屬層，與第1絕緣層相接之第2絕緣層、及一部分設置於第2金屬層中，於自第2金屬層朝第1金屬層之第1方向延伸之第1導電體。
第1實施形態之半導體裝置為非揮發性半導體記憶體100。非揮發性半導體記憶體100例如為將記憶胞3維配置之3維NAND快閃記憶體。
圖1係第1實施形態之半導體裝置之模式剖視圖。
第1實施形態之非揮發性半導體記憶體100包含記憶體晶片101與控制晶片102。記憶體晶片101為第1基板之一例。控制晶片102為第2基板之一例。
記憶體晶片101與控制晶片102由貼合面S(sticking interface)接合。記憶體晶片101與控制晶片102使用貼合技術接合。
記憶體晶片101具備第1半導體層10、複數個第1金屬焊墊11、第1層間絕緣層12、第1接觸插塞13a、第1配線層14、及記憶胞陣列15。
控制晶片102具備第2半導體層20、複數個第2金屬焊墊21、第2層間絕緣層22、第2接觸插塞23a、第2配線層24、及控制電路25。
第1金屬焊墊11為第1金屬層之一例。第1層間絕緣層12為第1絕緣層之一例。第1接觸插塞13a為第2導電體之一例。
第2金屬焊墊21為第2金屬層之一例。第2層間絕緣層22為第2絕緣層之一例。第2接觸插塞23a為第1導電體之一例。第2配線層24為導電層之一例。
第1半導體層10例如為單晶矽。
記憶胞陣列15設置於第1半導體層10與控制晶片102之間。記憶胞例如3維配置於記憶胞陣列15。
第1金屬焊墊11電性連接於記憶胞陣列15。第1金屬焊墊11經由第1接觸插塞13a及第1配線層14電性連接於記憶胞陣列15。
第1層間絕緣層12設置於第1半導體層10與控制晶片102之間。第1層間絕緣層12例如具有確保記憶胞陣列15內之配線、或記憶體晶片101內之配線之電性絕緣之功能。第1層間絕緣層12例如包含氧化矽。
第2半導體層20例如為單晶矽。
控制電路25設置於第2半導體層20與記憶體晶片101之間。控制電路25包含複數個電晶體等半導體元件、及將半導體元件間電性連接之多層配線層。控制電路25具有控制記憶胞陣列15之功能。
第2金屬焊墊21電性連接於控制電路25。第2金屬焊墊21經由第2接觸插塞23a及第2配線層24電性連接於記憶胞陣列15。
第2層間絕緣層22設置於第2半導體層20與記憶體晶片101之間。第2層間絕緣層22例如具有確保控制電路25內之半導體元件、或多層配線層中之配線之電性絕緣之功能。第2層間絕緣層22例如包含氧化矽。
第2金屬焊墊21由貼合面S與第1金屬焊墊11相接。第2金屬焊墊21電性連接於第1金屬焊墊11。
記憶體晶片101與控制晶片102經由第1金屬焊墊11與第2金屬焊墊21電性連接。
以下，將由貼合面S連接第1金屬焊墊11與第2金屬焊墊21之附近區域(圖1中之X)稱為連接區域。
圖2係第1實施形態之半導體裝置之連接區域之模式剖視圖。
非揮發性半導體記憶體100之連接區域之記憶體晶片101側之部分包含第1金屬焊墊11、第1層間絕緣層12、第1接觸插塞13a、第1配線層14、第1障壁金屬膜16、第1抗擴散膜17a、及第1抗擴散膜17b。
非揮發性半導體記憶體100之連接區域之控制晶片102側之部分包含第2金屬焊墊21、第2層間絕緣層22、第2接觸插塞23a、第2配線層24、第2障壁金屬膜26、第2抗擴散膜27a、及第2抗擴散膜27b。
第1金屬焊墊11為第1金屬層之一例。第1層間絕緣層12為第1絕緣層之一例。第1接觸插塞13a為第2導電體之一例。
第2金屬焊墊21為第2金屬層之一例。第2層間絕緣層22為第2絕緣層之一例。第2接觸插塞23a為第1導電體之一例。第2配線層24為導電層之一例。第2障壁金屬膜26為導電膜之一例。
將自第2金屬焊墊21朝第1金屬焊墊11之方向、及自第1金屬焊墊11朝第2金屬焊墊21之方向定義為第1方向。將垂直於第1方向之方向定義為第2方向。
第1金屬焊墊11由第1層間絕緣層12包圍。第1金屬焊墊11為金屬。第1金屬焊墊11例如包含銅(Cu)。第1金屬焊墊11例如為銅(Cu)。
第1配線層14位於第1金屬焊墊11之第1方向。第1配線層14由第1層間絕緣層12包圍。第1配線層14於與第1金屬焊墊11之間，夾著第1接觸插塞13a。
第1配線層14為導電體。第1配線層14例如為金屬。第1配線層14例如包含銅(Cu)或鎢(W)。
第1接觸插塞13a設置於第1金屬焊墊11與第1配線層14之間。第1接觸插塞13a於第1方向延伸。第1接觸插塞13a例如為柱狀。第1接觸插塞13a例如為圓柱形狀或圓錐梯形形狀。第1接觸插塞13a將第1金屬焊墊11與第1配線層14電性連接。
第1接觸插塞13a為導電體。第1接觸插塞13a例如為金屬。第1接觸插塞13a例如包含鎢(W)。第1接觸插塞13a例如為鎢(W)。
第1障壁金屬膜16設置於第1金屬焊墊11與第1層間絕緣層12之間。第1障壁金屬膜16設置於第1金屬焊墊11與第1接觸插塞13a之間。第1障壁金屬膜16例如具有抑制第1金屬焊墊11所含之金屬向第1層間絕緣層12擴散之功能。
第1障壁金屬膜16為導電體。第1障壁金屬膜16例如為金屬或金屬氮化物。
第1障壁金屬膜16例如包含選自由鈦(Ti)、鉭(Ta)、錳(Mn)、及鈷(Co)所組成之群之至少一種金屬元素。第1障壁金屬膜16為例如鈦膜、氮化鈦膜、或氮化鉭膜。
第1障壁金屬膜16之厚度例如為10 nm以上且30 nm以下。
第1抗擴散膜17a設置於第1層間絕緣層12中。第1抗擴散膜17b設置於第1層間絕緣層12中。第1抗擴散膜17a及第1抗擴散膜17b例如具有防止第1金屬焊墊11或第1配線層14所含之金屬向第1層間絕緣層12擴散之功能。
第2金屬焊墊21由第2層間絕緣層22包圍。第2金屬焊墊21由貼合面S與第1金屬焊墊11相接。
第2金屬焊墊21為金屬。第2金屬焊墊21例如包含銅(Cu)。第2金屬焊墊21例如為銅(Cu)。
第2配線層24位於第2金屬焊墊21之第1方向。第2配線層24由第2層間絕緣層22包圍。第2配線層24於與第2金屬焊墊21之間，夾著第2接觸插塞23a。
第2配線層24為導電體。第2配線層24例如為金屬。第2配線層24例如包含銅(Cu)或鎢(W)。
第2接觸插塞23a設置於第2金屬焊墊21與第2配線層24之間。第2接觸插塞23a於第1方向延伸。第2接觸插塞23a例如為柱狀。第2接觸插塞23a例如為圓柱形狀或圓錐梯形形狀。第2接觸插塞23a將第2金屬焊墊21與第2配線層24電性連接。
第2接觸插塞23a之一部分設置於第2金屬焊墊21中。第2接觸插塞23a之第1金屬焊墊11側之端部設置於第2金屬焊墊21中。第2接觸插塞23a之一部分由第2金屬焊墊21包圍。第2接觸插塞23a之第1金屬焊墊11側之端部由第2金屬焊墊21包圍。
第2接觸插塞23a與第1金屬焊墊11於第1方向上分開。於第2接觸插塞23a與第1金屬焊墊11之間，設置第2金屬焊墊21。
第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離(圖2中之d1)小於第2金屬焊墊21之第1方向上之厚度(圖2中之t)。第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離d1例如為第2金屬焊墊21之第1方向上之厚度t之2分之1以下。
第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離d1較第1層間絕緣層12及第2層間絕緣層22之界面與第2接觸插塞23a之間之第2方向上之距離(圖2中之d2)小。
第2接觸插塞23a為導電體。第2接觸插塞23a例如為金屬。第2接觸插塞23a例如包含鎢(W)。第2接觸插塞23a例如為鎢(W)。
第2障壁金屬膜26設置於第2金屬焊墊21與第2層間絕緣層22之間。第2障壁金屬膜26設置於第2金屬焊墊21與第2接觸插塞23a之間。
第2障壁金屬膜26包圍第2金屬焊墊21中之第2接觸插塞23a。於第2金屬焊墊21中之第2接觸插塞23a之側面及上表面設置第2障壁金屬膜26。
第2障壁金屬膜26例如具有抑制第2金屬焊墊21所含之金屬向第2層間絕緣層22擴散之功能。
第2障壁金屬膜26為導電體。第2障壁金屬膜26例如為金屬或金屬氮化物。
第2障壁金屬膜26例如包含選自由鈦(Ti)、鉭(Ta)、錳(Mn)、及鈷(Co)所組成之群之至少一種金屬元素。第2障壁金屬膜26例如為鈦膜、氮化鈦膜、或氮化鉭膜。
第2障壁金屬膜26之厚度例如為10 nm以上且30 nm以下。
第2抗擴散膜27a設置於第2層間絕緣層22中。第2抗擴散膜27b設置於第2層間絕緣層22中。第2抗擴散膜27a及第2抗擴散膜27b例如具有防止第2金屬焊墊21或第2配線層24所含之金屬向第2層間絕緣層22擴散之功能。
接著，對第1實施形態之半導體裝置之製造方法之一例進行說明。圖3～13係顯示第1實施形態之半導體裝置之製造方法之模式剖視圖。
以下，著眼於非揮發性半導體記憶體100之連接區域X說明製造方法。
首先，對連接區域X之記憶體晶片101側之部分之製造方法進行說明。
於氧化矽膜51中形成鎢層52。接著，於氧化矽膜51及鎢層52上形成氮化矽膜53及氧化矽膜54(圖3)。
氧化矽膜51及氧化矽膜54最終成為第1層間絕緣層12之一部分。氮化矽膜53最終成為第1抗擴散膜17b。鎢層52最終成為第1配線層14。
接著，蝕刻氧化矽膜54及氮化矽膜53，形成到達鎢層52之接觸孔。接著，以鎢膜55嵌入所形成之接觸孔(圖4)。鎢膜55最終成為第1接觸插塞13a。
接著，於氧化矽膜54及鎢膜55上，形成氮化矽膜56及氧化矽膜57(圖5)。氮化矽膜56最終成為第1抗擴散膜17a。氧化矽膜57最終成為第1層間絕緣層12之一部分。
接著，蝕刻氧化矽膜57及氮化矽膜56，形成開口部58(圖6)。於開口部58之底部，鎢膜55露出。
接著，於開口部58中，形成鈦膜59及銅膜60(圖7)。銅膜60之表面例如藉由化學機械研磨法(Chemical Mechanical Polishing法：CMP法)平坦化。
鈦膜59最終成為第1障壁金屬膜16。又，銅膜60最終成為第1金屬焊墊11。
藉由以上製造方法形成連接區域X之記憶體晶片101側之部分。
接著，對連接區域X之控制晶片102側之部分之製造方法進行說明。
於氧化矽膜61中形成鎢層62。接著，於氧化矽膜61及鎢層62上形成氮化矽膜63、氧化矽膜64、氮化矽膜66、及氧化矽膜67(圖8)。
氧化矽膜61、氧化矽膜64、及氧化矽膜67最終成為第2層間絕緣層22之一部分。氮化矽膜63及氮化矽膜66最終成為第1抗擴散膜17b及第1抗擴散膜17a。鎢層62最終成為第2配線層24。
接著，蝕刻氧化矽膜67、氮化矽膜66、氧化矽膜64、及氮化矽膜63，形成到達鎢層62之接觸孔。接著，由鎢膜65嵌入形成之接觸孔(圖9)。鎢膜65最終成為第2接觸插塞23a。
接著，於氧化矽膜67及鎢膜65上形成氧化矽膜68(圖10)。氧化矽膜68最終成為第2層間絕緣層22之一部分。
接著，蝕刻氧化矽膜68、氧化矽膜67、及氮化矽膜66，形成開口部69(圖11)。成為於開口部69中，鎢膜65之上部突出之形狀。
接著，於開口部69中形成鈦膜70及銅膜71(圖12)。銅膜71之表面例如藉由CMP法平坦化。成為於銅膜71中，鎢膜65之上部突出之形狀。
鈦膜70最終成為第2障壁金屬膜26。此外，銅膜71最終成為第2金屬焊墊21。
藉由以上製造方法形成連接區域X之控制晶片102側之部分。
其後，將連接區域X之控制晶片102側之部分與連接區域X之記憶體晶片101側之部分以第2金屬焊墊21與第1金屬焊墊11相向之方式貼合(圖13)。將連接區域X之控制晶片102側之部分與連接區域X之記憶體晶片101側之部分藉由機械壓力貼合。其後，進行熱處理，藉此使連接區域X之控制晶片102側之部分與連接區域X之記憶體晶片101側之部分接合。
藉由以上製造方法，可製造非揮發性半導體記憶體100之連接區域X。
接著，對第1實施形態之半導體裝置之作用及效果進行說明。以下，以第1金屬焊墊11及第2金屬焊墊21之材料為銅(Cu)，第1障壁金屬膜16及第2障壁金屬膜26為鈦膜之情形，即，第1障壁金屬膜16及第2障壁金屬膜26所含之金屬元素為鈦(Ti)之情形為例進行說明。
圖14及15係第1實施形態之半導體裝置之作用及效果之說明圖。圖14係比較例之半導體裝置之連接區域之模式剖視圖。比較例之連接區域於未將第1導電體設置於第2金屬層中之點上，與第1實施形態之非揮發性半導體記憶體100之連接區域X不同。
比較例之連接區域不將第2接觸插塞23a設置於第2金屬焊墊21中。比較例之連接區域藉由以與第1實施形態之非揮發性半導體記憶體100之連接區域X之記憶體晶片101側之部分同樣之方法形成連接區域之控制晶片102側之部分而可製造。
如圖14所示，於製造連接區域後，有於第1金屬焊墊11與第2金屬焊墊21之間之貼合面S產生氣孔80(空隙)之情形。若於第1金屬焊墊11與第2金屬焊墊21之間之貼合面S產生氣孔80，則有連接區域之電遷移抗性降低之虞。氣孔80因電遷移而生長，有第1金屬焊墊11與第2金屬焊墊21之間之接觸電阻增大、或第1金屬焊墊11與第2金屬焊墊21之間出現斷線之虞。因連接區域之電遷移抗性降低，故非揮發性半導體記憶體100之可靠性降低。
考慮藉由使第1障壁金屬膜16及第2障壁金屬膜26所含之鈦擴散至氣孔80或貼合面S進行偏析，而提高連接區域之電遷移抗性。考慮藉由使鈦原子存在於銅(Cu)之晶界而可抑制銅原子之移動。
圖15係半導體裝置之連接區域之模式剖視圖。
於第1實施形態之非揮發性半導體記憶體100之連接區域X中，第2接觸插塞23a之一部分設置於第2金屬焊墊21中。於第2接觸插塞23a與第2金屬焊墊21之間，設置包含鈦(Ti)之第2障壁金屬膜26。
藉由將第2接觸插塞23a之一部分設置於第2金屬焊墊21中，而於第1金屬焊墊11與第2金屬焊墊21之間之貼合面S之附近，設置鈦(Ti)之供給源。因此，與比較例之連接區域相比，向氣孔80或貼合面S供給之鈦量增加。因此，連接區域X之電遷移抗性提高，非揮發性半導體記憶體100之可靠性提高。
第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離(圖2中之d1)較佳為第2金屬焊墊21之第1方向上之厚度(圖2中之t)之2分之1以下，更佳為3分之1以下，進而更佳為4分之1以下。藉由使第2接觸插塞23a與第1金屬焊墊11之間之第2障壁金屬膜26接近貼合面S，向氣孔80或貼合面S供給之鈦量增加，連接區域X之電遷移抗性進而提高。
第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離d1較佳為較第1層間絕緣層12與第2層間絕緣層22之界面與第2接觸插塞23a之間之第2方向上之距離(圖2中之d2)小。藉由使第2接觸插塞23a與第1金屬焊墊11之間之第2障壁金屬膜26較第2層間絕緣層22與第1金屬焊墊11之間之第2障壁金屬膜26更接近貼合面S，向氣孔80或貼合面S供給之鈦量增加，連接區域X之電遷移抗性進而提高。
另，第1障壁金屬膜16及第2障壁金屬膜26所含之金屬元素不限於鈦(Ti)。例如，認為即便金屬元素為鉭(Ta)、錳(Mn)、或鈷(Co)，亦可獲得與鈦(Ti)同樣之作用及效果。
以上，根據第1實施形態，可提供電遷移抗性提高，可靠性提高之半導體裝置。
(第2實施形態) 第2實施形態之半導體裝置於第1基板進而包含至少一部分設置於第1金屬層中，且於第1方向延伸之第2導電體之點上，與第1實施形態之半導體裝置不同。以下，有對與第1實施形態重複之內容，省略一部分記述之情形。
圖16係第2實施形態之半導體裝置之連接區域之模式剖視圖。
第2實施形態之非揮發性半導體記憶體之連接區域之記憶體晶片101側之部分包含第1金屬焊墊11、第1層間絕緣層12、第1接觸插塞13a、第1配線層14、第1障壁金屬膜16、第1抗擴散膜17a、及第1抗擴散膜17b。
第2實施形態之非揮發性半導體記憶體之連接區域之控制晶片102側之部分包含：第2金屬焊墊21、第2層間絕緣層22、第2接觸插塞23a、第2配線層24、第2障壁金屬膜26、第2抗擴散膜27a、及第2抗擴散膜27b。
第1金屬焊墊11係第1金屬層之一例。第1層間絕緣層12係第1絕緣層之一例。第1接觸插塞13a係第2導電體之一例。
第2金屬焊墊21係第2金屬層之一例。第2層間絕緣層22係第2絕緣層之一例。第2接觸插塞23a係第1導電體之一例。第2配線層24係導電層之一例。第2障壁金屬膜26係導電膜之一例。
第1接觸插塞13a之一部分設置於第1金屬焊墊11中。第1接觸插塞13a之第2金屬焊墊21側之端部設置於第1金屬焊墊11中。第1接觸插塞13a之一部分由第1金屬焊墊11包圍。第1接觸插塞13a之第2金屬焊墊21側之端部由第1金屬焊墊11包圍。
第1接觸插塞13a與第2金屬焊墊21於第1方向上分開。於第1接觸插塞13a與第2金屬焊墊21之間，設置第1金屬焊墊11。
第1接觸插塞13a與第2金屬焊墊21之間之第1方向上之距離較第1金屬焊墊11之第1方向之厚度小。第1接觸插塞13a與第2金屬焊墊21之間於第1方向上之距離例如為第1金屬焊墊11之第1方向上之厚度之2分之1以下。
根據第2實施形態之連接區域，藉由將第1接觸插塞13a之一部分設置於第1金屬焊墊11中，與第1實施形態之連接區域X相比，向氣孔80或貼合面S供給之鈦量進而增加。因此，連接區域之電遷移抗性進而提高。
以上，根據第2實施形態，可提供電遷移抗性提高，且可靠性提高之半導體裝置。
(第3實施形態) 第3實施形態之半導體裝置於第2基板進而包含至少一部分設置於第2金屬層中，且自第2金屬層於第1方向延伸之第3導電體之點上，與第2實施形態之半導體裝置不同。以下，有對與第1或第2實施形態重複之內容，省略一部分記述之情形。
圖17係第3實施形態之半導體裝置之連接區域之模式剖視圖。
第3實施形態之非揮發性半導體記憶體之連接區域之記憶體晶片101側之部分包含第1金屬焊墊11、第1層間絕緣層12、第1接觸插塞13a、第1接觸插塞13b、第1接觸插塞13c、第1配線層14、第1障壁金屬膜16、第1抗擴散膜17a、及第1抗擴散膜17b。
第3實施形態之非揮發性半導體記憶體之連接區域之控制晶片102側之部分包含第2金屬焊墊21、第2層間絕緣層22、第2接觸插塞23a、第2接觸插塞23b、第2接觸插塞23c、第2配線層24、第2障壁金屬膜26、第2抗擴散膜27a、及第2抗擴散膜27b。
第1金屬焊墊11係第1金屬層之一例。第1層間絕緣層12係第1絕緣層之一例。第1接觸插塞13a係第2導電體之一例。
第2金屬焊墊21係第2金屬層之一例。第2層間絕緣層22係第2絕緣層之一例。第2接觸插塞23a係第1導電體之一例。第2接觸插塞23b係第3導電體之一例。第2配線層24係導電層之一例。第2障壁金屬膜26係導電膜之一例。
第1接觸插塞13a之一部分設置於第1金屬焊墊11中。第1接觸插塞13b之一部分設置於第1金屬焊墊11中。第1接觸插塞13c之一部分設置於第1金屬焊墊11中。
第2接觸插塞23a之一部分設置於第2金屬焊墊21中。第2接觸插塞23b之一部分設置於第2金屬焊墊21中。第2接觸插塞23c之一部分設置於第2金屬焊墊21中。
根據第3實施形態之連接區域，第1金屬焊墊11中之第1接觸插塞之數量為3個。又，第2金屬焊墊21中之第2接觸插塞之數量為3個。因此，與第2實施形態之連接區域X相比，向氣孔80或貼合面S供給之鈦量進而增加。因此，連接區域之電遷移抗性進而提高。
另，第1金屬焊墊11中之第1接觸插塞之數量可為2個，亦可為4個以上。又，第2金屬焊墊21中之第2接觸插塞之數量可為2個，亦可為4個以上。
以上，根據第3實施形態，可提供電遷移抗性提高且可靠性提高之半導體裝置。
(第4實施形態) 第4實施形態之半導體裝置就第1導電體之另一部分設置於第1金屬層中之點，與第1實施形態之半導體裝置不同。以下，對於與第1實施形態重複之內容，有時省略一部分之記述。
圖18係第4實施形態之半導體裝置之連接區域之模式剖視圖。
第4實施形態之非揮發性半導體記憶體之連接區域之記憶體晶片101側之部分包含第1金屬焊墊11、第1層間絕緣層12、第1接觸插塞13a、第1配線層14、第1障壁金屬膜16、第1抗擴散膜17a、及第1抗擴散膜17b。
第4實施形態之非揮發性半導體記憶體之連接區域之控制晶片102側之部分包含第2金屬焊墊21、第2層間絕緣層22、第2接觸插塞23a、第2配線層24、第2障壁金屬膜26、第2抗擴散膜27a、及第2抗擴散膜27b。
第1金屬焊墊11為第1金屬層之一例。第1層間絕緣層12為第1絕緣層之一例。第1接觸插塞13a為第2導電體之一例。
第2金屬焊墊21為第2金屬層之一例。第2層間絕緣層22為第2絕緣層之一例。第2接觸插塞23a為第1導電體之一例。第2配線層24為導電層之一例。第2障壁金屬膜26為導電膜之一例。
第2接觸插塞23a之一部分設置於第2金屬焊墊21中。又，第2接觸插塞23a之另一部分設置於第1金屬焊墊11中。第2接觸插塞23a之第1金屬焊墊11側之端部設置於第1金屬焊墊11中。
第2接觸插塞23a之一部分由第2金屬焊墊21包圍。第2接觸插塞23a之另一部分由第1金屬焊墊11包圍。第2接觸插塞23a之第1金屬焊墊11側之端部由第1金屬焊墊11包圍。
第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離為零。因此，第2接觸插塞23a與第1金屬焊墊11之間之第1方向上之距離較第2金屬焊墊21之第1方向上之厚度小。
根據第4實施形態之連接區域，第2接觸插塞23a之另一部分設置於第1金屬焊墊11中，藉此，與第1實施形態之連接區域X相比，向氣孔80或貼合面S供給之鈦量進而增加。因此，連接區域之電遷移抗性進而提高。
以上，根據第4實施形態，可提供一種電遷移抗性提高，且可靠性提高之半導體裝置。
於第1實施形態至第4實施形態中，定義貼合面S。於非揮發性半導體記憶體之最終製品中，有無法明確視認記憶體晶片101及控制晶片102之貼合面S之位置之情形。但，例如，根據第1金屬焊墊11與第2金屬焊墊21之位置偏移，可確定貼合面S之位置。
於第1實施形態至第4實施形態中，已以具備記憶體晶片101作為第1基板之一例，具備控制晶片102作為第2基板之一例之非揮發性半導體記憶體為例進行說明。但，本發明之半導體裝置不限定於具備記憶體晶片101與控制晶片102之非揮發性半導體記憶體。例如，亦可對具備像素晶片作為第1基板，具備控制晶片作為第2基板之光感測器應用本發明。
以上，已說明本發明之若干實施形態，但該等實施形態係作為例而提示者，並未意圖限定發明之範圍。該等新穎的實施形態可由其它各種方式實施，於不脫離發明主旨之範圍內，可進行各種省略、置換、變更。例如，可將一實施形態之構成要件與其它實施形態之構成要件置換或變更。該等實施形態或其變化包含於發明範圍或主旨內，且包含於申請專利範圍所記述之發明與其均等之範圍內。
[相關申請案] 本申請案享受日本專利申請案第2021-42893號(申請日：2021年3月16日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
10:第1半導體層 11:第1金屬焊墊(第1金屬層) 12:第1層間絕緣層(第1絕緣層) 13a:第1接觸插塞(第2導電體) 13b:第1接觸插塞 13c:第1接觸插塞 14:第1配線層 15:記憶胞陣列 16:第1障壁金屬膜 17a:第1抗擴散膜 17b:第1抗擴散膜 20:第2半導體層 21:第2金屬焊墊(第2金屬層) 22:第2層間絕緣層(第2絕緣層) 23a:第2接觸插塞(第1導電體) 23b:第2接觸插塞(第3導電體) 23c:第2接觸插塞 24:第2配線層(導電層) 25:控制電路 26:第2障壁金屬膜(導電膜) 27a:第2抗擴散膜 27b:第2抗擴散膜 51:氧化矽膜 52:鎢層 53:氮化矽膜 54:氧化矽膜 55:鎢膜 56:氮化矽膜 57:氧化矽膜 58:開口部 60:銅膜 61:氧化矽膜 62:鎢層 63:氮化矽膜 64:氧化矽膜 65:鎢膜 66:氮化矽膜 67:氧化矽膜 68:氧化矽膜 69:開口部 70:鈦膜 71:銅膜 100:非揮發性半導體記憶體(半導體裝置) 101:記憶體晶片(第1基板) 102:控制晶片(第2基板) d1:距離 d2:距離 S:貼合面 t:厚度 X:連接區域
圖1係第1實施形態之半導體裝置之模式剖視圖。 圖2係第1實施形態之半導體裝置之連接區域之模式剖視圖。 圖3～13係顯示第1實施形態之半導體裝置之製造方法之模式剖視圖。 圖14、15係第1實施形態之半導體裝置之作用及效果之說明圖。 圖16係第2實施形態之半導體裝置之連接區域之模式剖視圖。 圖17係第3實施形態之半導體裝置之連接區域之模式剖視圖。 圖18係第4實施形態之半導體裝置之連接區域之模式剖視圖。
11:第1金屬焊墊(第1金屬層)
12:第1層間絕緣層(第1絕緣層)
13a:第1接觸插塞(第2導電體)
14:第1配線層
16:第1障壁金屬膜
17a:第1抗擴散膜
17b:第1抗擴散膜
21:第2金屬焊墊(第2金屬層)
22:第2層間絕緣層(第2絕緣層)
23a:第2接觸插塞(第1導電體)
24:第2配線層(導電層)
26:第2障壁金屬膜(導電膜)
27a:第2抗擴散膜
27b:第2抗擴散膜
101:記憶體晶片(第1基板)
102:控制晶片(第2基板)
d1:距離
d2:距離
S:貼合面
t:厚度

Claims (14)

  1. 一種半導體裝置，其具備：第1基板，其包含第1絕緣層；及第2基板，其包含與上述第1絕緣層相接之第2絕緣層，且與上述第1基板貼合；金屬層，其設置於上述第1基板與上述第2基板之貼合面，第1部分被上述第1絕緣層包圍，第2部分被上述第2絕緣層包圍；第1導電體，其一部份設置於上述第1部分之中，且延伸於自上述第2部分朝向上述第1部分之方向；及導電膜，其設置於上述第1導電體與上述第2部分之間、及上述第2部分與上述第2絕緣層之間；在上述金屬層，構成上述導電膜之第1元素所在偏於上述貼合面附近。
  2. 如請求項1之半導體裝置，其中上述第1導電體與上述第1金屬層之間之上述第1方向之距離為上述第2金屬層之上述第1方向之厚度的2分之1以下。
  3. 如請求項1或2之半導體裝置，其中上述第1導電體與上述第1金屬層之間之上述第1方向之距離，小於上述第1絕緣層與上述第2絕緣層之界面與上述第1導電體之間之與上述第1方向垂直之第2方向之距離。
  4. 如請求項1或2之半導體裝置，其中上述第1金屬層包含銅(Cu)，上述第2金屬層包含銅(Cu)。
  5. 如請求項1或2之半導體裝置，其中上述第1導電體包含鎢(W)。
  6. 如請求項1之半導體裝置，其中上述第1元素係鈦(Ti)。
  7. 如請求項6之半導體裝置，其中上述導電膜包含選自由鈦(Ti)、鉭(Ta)、錳(Mn)、及鈷(Co)所組成之群之至少一種金屬元素。
  8. 如請求項1或2之半導體裝置，其中上述第2基板進而包含：導電層，其於與上述第2金屬層之間夾著上述第1導電體，且電性連接於上述第1導電體。
  9. 如請求項1或2之半導體裝置，其中上述第1導電體與上述第1金屬層於上述第1方向上分開。
  10. 如請求項1或2之半導體裝置，其中上述第1導電體之另一部分設置於上述第1金屬層中。
  11. 如請求項1或2之半導體裝置，其中上述第1基板進而包含：第2導電體，其至少一部分設置於上述第1金屬層中，且於上述第1方向延伸。
  12. 如請求項1或2之半導體裝置，其中上述第2基板進而包含：第3導電體，其至少一部分設置於上述第2金屬層中，且於上述第1方向延伸。
  13. 如請求項1或2之半導體裝置，其中上述第1基板進而包含記憶胞陣列，且上述第2基板進而包含控制上述記憶胞陣列之控制電路。
  14. 如請求項13之半導體裝置，其中上述第1金屬層電性連接於上述記憶胞陣列，上述第2金屬層電性連接於上述控制電路。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201806106A (zh) * 2016-08-05 2018-02-16 南亞科技股份有限公司 半導體結構及其製造方法
TW202036826A (zh) * 2019-03-15 2020-10-01 日商東芝記憶體股份有限公司 半導體裝置及其製造方法
CN112292757A (zh) * 2018-08-24 2021-01-29 铠侠股份有限公司 半导体装置及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201806106A (zh) * 2016-08-05 2018-02-16 南亞科技股份有限公司 半導體結構及其製造方法
CN112292757A (zh) * 2018-08-24 2021-01-29 铠侠股份有限公司 半导体装置及其制造方法
TW202036826A (zh) * 2019-03-15 2020-10-01 日商東芝記憶體股份有限公司 半導體裝置及其製造方法

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