CN115084071A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN115084071A
CN115084071A CN202110942197.0A CN202110942197A CN115084071A CN 115084071 A CN115084071 A CN 115084071A CN 202110942197 A CN202110942197 A CN 202110942197A CN 115084071 A CN115084071 A CN 115084071A
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Prior art keywords
metal
metal pad
metal layer
semiconductor device
layer
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CN202110942197.0A
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Inventor
藤井光太郎
渡边慎也
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Kioxia Corp
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Kioxia Corp
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Publication of CN115084071A publication Critical patent/CN115084071A/zh
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Abstract

实施方式提供一种可靠性提高的半导体装置。实施方式的半导体装置具备：第1衬底，包含第1金属层、与包围第1金属层的第1绝缘层；及第2衬底，包含与第1金属层相接的第2金属层、包围第2金属层，且与第1绝缘层相接的第2绝缘层、及一部分设置在第2金属层中，沿从第2金属层朝第1金属层的第1方向延伸的第1导电体。

Description

半导体装置
相关申请
本申请享受日本专利申请第2021-42893号(申请日：2021年3月16日)为基础申请的优先权。本申请通过参考所述基础申请而包含基础申请的所有内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
贴合技术例如通过将分别形成着电子电路的2片晶圆贴合，而实现高功能或高集成的半导体设备。例如，利用切割将半导体晶圆分割成多个晶片，而实现高功能或高集成的半导体存储器，且所述半导体晶圆通过将形成着存储器单元阵列的半导体晶圆、与形成着控制存储器单元阵列的控制电路的半导体晶圆贴合，之后施加热处理接合而成。
在使用贴合技术制造的半导体设备中，期望提高可靠性。
发明内容
本发明的实施方式提供一种可靠性提高的半导体装置。
实施方式的半导体装置具备：第1衬底：包含第1金属层、与包围所述第1金属层的第1绝缘层；及第2衬底，包含与所述第1金属层相接的第2金属层、包围所述第2金属层，且与所述第1绝缘层相接的第2绝缘层、及一部分设置在所述第2金属层中，沿从所述第2金属层朝所述第1金属层的第1方向延伸的第1导电体。
附图说明
图1是第1实施方式的半导体装置的示意剖视图。
图2是第1实施方式的半导体装置的连接区域的示意剖视图。
图3～13是表示第1实施方式的半导体装置的制造方法的示意剖视图。
图14、15是第1实施方式的半导体装置的作用及效果的说明图。
图16是第2实施方式的半导体装置的连接区域的示意剖视图。
图17是第3实施方式的半导体装置的连接区域的示意剖视图。
图18是第4实施方式的半导体装置的连接区域的示意剖视图。
具体实施方式
以下，参考附图且说明本发明的实施方式。另外，在以下的说明中，有对相同或类似的部件等标注相同符号，对已说明过一次的部件等适当省略它的说明的情况。
另外，本说明书中，为方便起见，有使用“上”或“下”等用语的情况。“上”或“下”例如是表示附图内的相对位置关系的用语。“上”或“下”等用语未必为规定相对于重力的位置关系的用语。
构成本说明书中的半导体装置的部件的化学组成的定性分析及定量分析例如能通过次级离子质量分析法(Secondary Ion Mass Spectrometry：SIMS)、能量分散型X射线分光法(Energy Dispersive X-ray Spectroscopy：EDX)进行。另外，对于构成半导体装置的部件的厚度、部件间的距离等测定，能使用例如穿透型电子显微镜(TransmissionElectron Microscope：TEM)或扫描型电子显微镜(Scanning Electron Microscope：SEM)。
(第1实施方式)
第1实施方式的半导体装置具备：第1衬底，包含第1金属层、与包围第1金属层的第1绝缘层；及第2衬底，包含与第1金属层相接的第2金属层、包围第2金属层，且与第1绝缘层相接的第2绝缘层、及一部分设置在第2金属层中，沿从第2金属层朝第1金属层的第1方向延伸的第1导电体。
第1实施方式的半导体装置为非易失性半导体存储器100。非易失性半导体存储器100例如为将存储器单元3维配置的3维NAND闪存。
图1是第1实施方式的半导体存储装置的示意剖视图。
第1实施方式的非易失性半导体存储器100包含存储器晶片101与控制晶片102。存储器晶片101为第1衬底的一个例子。控制晶片102为第2衬底的一个例子。
存储器晶片101与控制晶片102由贴合面S(sticking interface)接合。存储器晶片101与控制晶片102使用贴合技术接合。
存储器晶片101具备第1半导体层10、多个第1金属焊垫11、第1层间绝缘层12、第1接触插塞13a、第1布线层14、及存储器单元阵列15。
控制晶片102具备第2半导体层20、多个第2金属焊垫21、第2层间绝缘层22、第2接触插塞23a、第2布线层24、及控制电路25。
第1金属焊垫11为第1金属层的一个例子。第1层间绝缘层12为第1绝缘层的一个例子。第1接触插塞13a为第2导电体的一个例子。
第2金属焊垫21为第2金属层的一个例子。第2层间绝缘层22为第2绝缘层的一个例子。第2接触插塞23a为第1导电体的一个例子。第2布线层24为导电层的一个例子。
第1半导体层10例如为单晶硅。
存储器单元阵列15设置在第1半导体层10与控制晶片102之间。例如存储器单元3维配置在存储器单元阵列15。
第1金属焊垫11电连接到存储器单元阵列15。第1金属焊垫11经由第1接触插塞13a及第1布线层14电连接到存储器单元阵列15。
第1层间绝缘层12设置在第1半导体层10与控制晶片102之间。第1层间绝缘层12例如具有确保存储器单元阵列15内的布线、或存储器晶片101内的布线的电绝缘的功能。第1层间绝缘层12例如包含氧化硅。
第2半导体层20例如为单晶硅。
控制电路25设置在第2半导体层20与存储器晶片101之间。控制电路25包含多个晶体管等半导体元件、及将半导体元件间电连接的多层布线层。控制电路25具有控制存储器单元阵列15的功能。
第2金属焊垫21电连接到控制电路25。第2金属焊垫21经由第2接触插塞23a及第2布线层24电连接到存储器单元阵列15。
第2层间绝缘层22设置在第2半导体层20与存储器晶片101之间。第2层间绝缘层22例如具有确保控制电路25内的半导体元件、或多层布线层中的布线的电绝缘的功能。第2层间绝缘层22例如包含氧化硅。
第2金属焊垫21由贴合面S与第1金属焊垫11相接。第2金属焊垫21电连接到第1金属焊垫11。
存储器晶片101与控制晶片102经由第1金属焊垫11与第2金属焊垫21电连接。
以下，将由贴合面S连接第1金属焊垫11与第2金属焊垫21的附近区域(图1中的X)称为连接区域。
图2是第1实施方式的半导体装置的连接区域的示意剖视图。
非易失性半导体存储器100在连接区域的存储器晶片101侧的部分包含第1金属焊垫11、第1层间绝缘层12、第1接触插塞13a、第1布线层14、第1势垒金属膜16、第1抗扩散膜17a、及第1抗扩散膜17b。
非易失性半导体存储器100在连接区域的控制晶片102侧的部分包含第2金属焊垫21、第2层间绝缘层22、第2接触插塞23a、第2布线层24、第2势垒金属膜26、第2抗扩散膜27a、及第2抗扩散膜27b。
第1金属焊垫11为第1金属层的一个例子。第1层间绝缘层12为第1绝缘层的一个例子。第1接触插塞13a为第2导电体的一个例子。
第2金属焊垫21为第2金属层的一个例子。第2层间绝缘层22为第2绝缘层的一个例子。第2接触插塞23a为第1导电体的一个例子。第2布线层24为导电层的一个例子。第2势垒金属膜26为导电膜的一个例子。
将从第2金属焊垫21朝第1金属焊垫11的方向、及从第1金属焊垫11朝第2金属焊垫21的方向定义为第1方向。将垂直于第1方向的方向定义为第2方向。
第1金属焊垫11由第1层间绝缘层12包围。第1金属焊垫11为金属。第1金属焊垫11例如包含铜(Cu)。第1金属焊垫11例如为铜(Cu)。
第1布线层14位于第1金属焊垫11的第1方向。第1布线层14由第1层间绝缘层12包围。第1布线层14在与第1金属焊垫11之间，隔着第1接触插塞13a。
第1布线层14为导电体。第1布线层14例如为金属。第1布线层14例如包含铜(Cu)或钨(W)。
第1接触插塞13a设置在第1金属焊垫11与第1布线层14之间。第1接触插塞13a沿第1方向延伸。第1接触插塞13a例如为柱状。第1接触插塞13a例如为圆柱形状或圆锥梯形形状。第1接触插塞13a将第1金属焊垫11与第1布线层14电连接。
第1接触插塞13a为导电体。第1接触插塞13a例如为金属。第1接触插塞13a例如包含钨(W)。第1接触插塞13a例如为钨(W)。
第1势垒金属膜16设置在第1金属焊垫11与第1层间绝缘层12之间。第1势垒金属膜16设置在第1金属焊垫11与第1接触插塞13a之间。第1势垒金属膜16例如具有抑制第1金属焊垫11所含的金属向第1层间绝缘层12扩散的功能。
第1势垒金属膜16为导电体。第1势垒金属膜16例如为金属或金属氮化物。
第1势垒金属膜16例如包含从由钛(Ti)、钽(Ta)、锰(Mn)、及钴(Co)所组成的群中选择的至少一种金属元素。第1势垒金属膜16为例如钛膜、氮化钛膜、或氮化钽膜。
第1势垒金属膜16的厚度例如为10nm以上且30nm以下。
第1抗扩散膜17a设置在第1层间绝缘层12中。第1抗扩散膜17b设置在第1层间绝缘层12中。第1抗扩散膜17a及第1抗扩散膜17b例如具有防止第1金属焊垫11或第1布线层14所含的金属向第1层间绝缘层12扩散的功能。
第2金属焊垫21由第2层间绝缘层22包围。第2金属焊垫21由贴合面S与第1金属焊垫11相接。
第2金属焊垫21为金属。第2金属焊垫21例如包含铜(Cu)。第2金属焊垫21例如为铜(Cu)。
第2布线层24位于第2金属焊垫21的第1方向。第2布线层24由第2层间绝缘层22包围。第2布线层24在与第2金属焊垫21之间，隔着第2接触插塞23a。
第2布线层24为导电体。第2布线层24例如为金属。第2布线层24例如包含铜(Cu)或钨(W)。
第2接触插塞23a设置在第2金属焊垫21与第2布线层24之间。第2接触插塞23a沿第1方向延伸。第2接触插塞23a例如为柱状。第2接触插塞23a例如为圆柱形状或圆锥梯形形状。第2接触插塞23a将第2金属焊垫21与第2布线层24电连接。
第2接触插塞23a的一部分设置在第2金属焊垫21中。第2接触插塞23a的第1金属焊垫11侧的端部设置在第2金属焊垫21中。第2接触插塞23a的一部分由第2金属焊垫21包围。第2接触插塞23a的第1金属焊垫11侧的端部由第2金属焊垫21包围。
第2接触插塞23a与第1金属焊垫11在第1方向上分开。在第2接触插塞23a与第1金属焊垫11之间，设置第2金属焊垫21。
第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离(图2中的d1)小于第2金属焊垫21在第1方向上的厚度(图2中的t)。第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离d1例如为第2金属焊垫21在第1方向上的厚度t的2分之1以下。
第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离d1比第1层间绝缘层12和第2层间绝缘层22的界面与第2接触插塞23a之间在第2方向上的距离(图2中的d2)小。
第2接触插塞23a为导电体。第2接触插塞23a例如为金属。第2接触插塞23a例如包含钨(W)。第2接触插塞23a例如为钨(W)。
第2势垒金属膜26设置在第2金属焊垫21与第2层间绝缘层22之间。第2势垒金属膜26设置在第2金属焊垫21与第2接触插塞23a之间。
第2势垒金属膜26包围第2金属焊垫21中的第2接触插塞23a。在第2金属焊垫21中的第2接触插塞23a的侧面及上表面设置第2势垒金属膜26。
第2势垒金属膜26例如具有抑制第2金属焊垫21所含的金属向第2层间绝缘层22扩散的功能。
第2势垒金属膜26为导电体。第2势垒金属膜26例如为金属或金属氮化物。
第2势垒金属膜26例如包含从由钛(Ti)、钽(Ta)、锰(Mn)、及钴(Co)所组成之群中选择的至少一种金属元素。第2势垒金属膜26例如为钛膜、氮化钛膜、或氮化钽膜。
第2势垒金属膜26的厚度例如为10nm以上且30nm以下。
第2抗扩散膜27a设置在第2层间绝缘层22中。第2抗扩散膜27b设置在第2层间绝缘层22中。第2抗扩散膜27a及第2抗扩散膜27b例如具有防止第2金属焊垫21或第2布线层24所含的金属向第2层间绝缘层22扩散的功能。
接着，对第1实施方式的半导体装置的制造方法的一例进行说明。图3～13是表示第1实施方式的半导体装置的制造方法的示意剖视图。
以下，着眼于非易失性半导体存储器100的连接区域X说明制造方法。
首先，对连接区域X的存储器晶片101侧的部分的制造方法进行说明。
在氧化硅膜51中形成钨层52。接着，在氧化硅膜51及钨层52上形成氮化硅膜53及氧化硅膜54(图3)。
氧化硅膜51及氧化硅膜54最终成为第1层间绝缘层12的一部分。氮化硅膜53最终成为第1抗扩散膜17b。钨层52最终成为第1布线层14。
接着，蚀刻氧化硅膜54及氮化硅膜53，形成到达钨层52的接触孔。接着，由钨膜55嵌入形成的接触孔(图4)。钨膜55最终成为第1接触插塞13a。
接着，在氧化硅膜54及钨膜55上，形成氮化硅膜56及氧化硅膜57(图5)。氮化硅膜56最终成为第1抗扩散膜17a。氧化硅膜57最终成为第1层间绝缘层12的一部分。
接着，蚀刻氧化硅膜57及氮化硅膜56，形成开口部58(图6)。在开口部58的底部，露出钨膜55。
接着，在开口部58中，形成钛膜59及铜膜60(图7)。铜膜60的表面例如通过化学机械抛光法(Chemical Mechanical Polishing法：CMP法)平坦化。
钛膜59最终成为第1势垒金属膜16。另外，铜膜60最终成为第1金属焊垫11。
通过以上制造方法形成连接区域X在存储器晶片101侧的部分。
接着，对连接区域X在控制晶片102侧的部分的制造方法进行说明。
在氧化硅膜61中形成钨层62。接着，在氧化硅膜61及钨层62上形成氮化硅膜63、氧化硅膜64、氮化硅膜66、及氧化硅膜67(图8)。
氧化硅膜61、氧化硅膜64及氧化硅膜67最终成为第2层间绝缘层22的一部分。氮化硅膜63及氮化硅膜66最终成为第1抗扩散膜17b及第1抗扩散膜17a。钨层62最终成为第2布线层24。
接着，蚀刻氧化硅膜67、氮化硅膜66、氧化硅膜64、及氮化硅膜63，形成到达钨层62的接触孔。接着，由钨膜65嵌入形成的接触孔(图9)。钨膜65最终成为第2接触插塞23a。
接着，在氧化硅膜67及钨膜65上形成氧化硅膜68(图10)。氧化硅膜68最终成为第2层间绝缘层22的一部分。
接着，蚀刻氧化硅膜68、氧化硅膜67、及氮化硅膜66，形成开口部69(图11)。成为在开口部69中，钨膜65的上部突出的形状。
接着，在开口部69中形成钛膜70及铜膜71(图12)。铜膜71的表面例如通过CMP法平坦化。成为在铜膜71中，钨膜65的上部突出的形状。
钛膜70最终成为第2势垒金属膜26。另外，铜膜71最终成为第2金属焊垫21。
通过以上制造方法形成连接区域X在控制晶片102侧的部分。
之后，将连接区域X在控制晶片102侧的部分与连接区域X在存储器晶片101侧的部分以第2金属焊垫21与第1金属焊垫11相向的方式贴合(图13)。将连接区域X在控制晶片102侧的部分与连接区域X在存储器晶片101侧的部分通过机械压力贴合。之后，进行热处理，由此使连接区域X在控制晶片102侧的部分与连接区域X在存储器晶片101侧的部分接合。
通过以上制造方法，能制造非易失性半导体存储器100的连接区域X。
接着，对第1实施方式的半导体装置的作用及效果进行说明。以下，以第1金属焊垫11及第2金属焊垫21的材料为铜(Cu)，且第1势垒金属膜16及第2势垒金属膜26为钛膜的情况，也就是第1势垒金属膜16及第2势垒金属膜26所含的金属元素为钛(Ti)的情况为例进行说明。
图14及15是第1实施方式的半导体装置的作用及效果的说明图。图14是比较例的半导体装置的连接区域的示意剖视图。比较例的连接区域在未将第1导电体设置在第2金属层中这点上，与第1实施方式的非易失性半导体存储器100的连接区域X不同。
比较例的连接区域不将第2接触插塞23a设置在第2金属焊垫21中。比较例的连接区域通过由与第1实施方式的非易失性半导体存储器100的连接区域X在存储器晶片101侧的部分同样的方法形成连接区域在控制晶片102侧的部分而制造。
如图14所示，在制造连接区域后，有在第1金属焊垫11与第2金属焊垫21之间的贴合面S上产生气孔80(空隙)的情况。如果在第1金属焊垫11与第2金属焊垫21之间的贴合面S产生气孔80，那么担心连接区域的电迁移耐性会降低。气孔80会因电迁移而生长，从而担心第1金属焊垫11与第2金属焊垫21之间的接触电阻增大，或第1金属焊垫11与第2金属焊垫21之间出现断线。因连接区域的电迁移耐性降低，非易失性半导体存储器100的可靠性降低。
考虑使第1势垒金属膜16及第2势垒金属膜26所含的钛扩散到气孔80或贴合面S而偏析，来提高连接区域的电迁移耐性。考虑能通过使钛原子在铜(Cu)的晶界处存在而抑制铜原子的移动。
图15是半导体装置的连接区域的示意剖视图。
在第1实施方式的非易失性半导体存储器100的连接区域X中，第2接触插塞23a的一部分设置在第2金属焊垫21中。在第2接触插塞23a与第2金属焊垫21之间，设置包含钛(Ti)的第2势垒金属膜26。
通过将第2接触插塞23a的一部分设置在第2金属焊垫21中，而在第1金属焊垫11与第2金属焊垫21之间的贴合面S的附近，设置钛(Ti)的供给源。因此，与比较例的连接区域相比，钛向气孔80或贴合面S的供给量增加。因此，连接区域X的电迁移耐性提高，非易失性半导体存储器100的可靠性提高。
第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离(图2中的d1)优选为第2金属焊垫21在第1方向上的厚度(图2中的t)的2分之1以下，更优选为3分之1以下，进一步优选为4分之1以下。通过使第2接触插塞23a与第1金属焊垫11之间的第2势垒金属膜26接近贴合面S，钛向气孔80或贴合面S的供给量增加，连接区域X的电迁移耐性进一步提高。
第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离d1优选为比第1层间绝缘层12和第2层间绝缘层22的界面与第2接触插塞23a之间在第2方向上的距离(图2中的d2)小。通过使第2接触插塞23a与第1金属焊垫11之间的第2势垒金属膜26比第2层间绝缘层22与第1金属焊垫11之间的第2势垒金属膜26更接近贴合面S，钛向气孔80或贴合面S的供给量增加，连接区域X的电迁移耐性进一步提高。
另外，第1势垒金属膜16及第2势垒金属膜26所含的金属元素不限于钛(Ti)。例如，认为即便金属元素为钽(Ta)、锰(Mn)、或钴(Co)，也能获得与钛(Ti)同样的作用及效果。
以上，根据第1实施方式，能提供电迁移耐性提高，可靠性提高的半导体装置。
(第2实施方式)
第2实施方式的半导体装置在第1衬底还包含至少一部分设置在第1金属层中，且沿第1方向延伸的第2导电体这点上，与第1实施方式的半导体装置不同。以下，有对与第1实施方式重复的内容，省略一部分记述的情况。
图16是第2实施方式的半导体装置的连接区域的示意剖视图。
第2实施方式的非易失性半导体存储器的连接区域在存储器晶片101侧的部分包含第1金属焊垫11、第1层间绝缘层12、第1接触插塞13a、第1布线层14、第1势垒金属膜16、第1抗扩散膜17a、及第1抗扩散膜17b。
第2实施方式的非易失性半导体存储器的连接区域在控制晶片102侧的部分包含：第2金属焊垫21、第2层间绝缘层22、第2接触插塞23a、第2布线层24、第2势垒金属膜26、第2抗扩散膜27a、及第2抗扩散膜27b。
第1金属焊垫11是第1金属层的一个例子。第1层间绝缘层12是第1绝缘层的一个例子。第1接触插塞13a是第2导电体的一个例子。
第2金属焊垫21是第2金属层的一个例子。第2层间绝缘层22是第2绝缘层的一个例子。第2接触插塞23a是第1导电体的一个例子。第2布线层24是导电层的一个例子。第2势垒金属膜26是导电膜的一个例子。
第1接触插塞13a的一部分设置在第1金属焊垫11中。第1接触插塞13a在第2金属焊垫21侧的端部设置在第1金属焊垫11中。第1接触插塞13a的一部分由第1金属焊垫11包围。第1接触插塞13a在第2金属焊垫21侧的端部由第1金属焊垫11包围。
第1接触插塞13a与第2金属焊垫21在第1方向上分开。在第1接触插塞13a与第2金属焊垫21之间，设置第1金属焊垫11。
第1接触插塞13a与第2金属焊垫21之间在第1方向上的距离比第1金属焊垫11在第1方向的厚度小。第1接触插塞13a与第2金属焊垫21之间在第1方向上的距离例如为第1金属焊垫11在第1方向上的厚度的2分之1以下。
根据第2实施方式的连接区域，通过将第1接触插塞13a的一部分设置在第1金属焊垫11中，与第1实施方式的连接区域X相比，钛向气孔80或贴合面S的供给量进一步增加。因此，连接区域的电迁移耐性进一步提高。
以上，根据第2实施方式，能提供电迁移耐性提高，且可靠性提高的半导体装置。
(第3实施方式)
第3实施方式的半导体装置在第2衬底还包含至少一部分设置在第2金属层中，且从第2金属层沿第1方向延伸的第3导电体这点上，与第2实施方式的半导体装置不同。以下，有对与第1或第2实施方式重复的内容，省略一部分记述的情况。
图17是第3实施方式的半导体装置的连接区域的示意剖视图。
第3实施方式的非易失性半导体存储器的连接区域在存储器晶片101侧的部分包含第1金属焊垫11、第1层间绝缘层12、第1接触插塞13a、第1接触插塞13b、第1接触插塞13c、第1布线层14、第1势垒金属膜16、第1抗扩散膜17a、及第1抗扩散膜17b。
第3实施方式的非易失性半导体存储器的连接区域在控制晶片102侧的部分包含第2金属焊垫21、第2层间绝缘层22、第2接触插塞23a、第2接触插塞23b、第2接触插塞23c、第2布线层24、第2势垒金属膜26、第2抗扩散膜27a、及第2抗扩散膜27b。
第1金属焊垫11是第1金属层的一个例子。第1层间绝缘层12是第1绝缘层的一个例子。第1接触插塞13a是第2导电体的一个例子。
第2金属焊垫21是第2金属层的一个例子。第2层间绝缘层22是第2绝缘层的一个例子。第2接触插塞23a是第1导电体的一个例子。第2接触插塞23b是第3导电体的一个例子。第2布线层24是导电层的一个例子。第2势垒金属膜26是导电膜的一个例子。
第1接触插塞13a的一部分设置在第1金属焊垫11中。第1接触插塞13b的一部分设置在第1金属焊垫11中。第1接触插塞13c的一部分设置在第1金属焊垫11中。
第2接触插塞23a的一部分设置在第2金属焊垫21中。第2接触插塞23b的一部分设置在第2金属焊垫21中。第2接触插塞23c的一部分设置在第2金属焊垫21中。
根据第3实施方式的连接区域，第1金属焊垫11中的第1接触插塞的数量变为3个。另外，第2金属焊垫21中的第2接触插塞的数量变为3个。因此，与第2实施方式的连接区域X相比，钛向气孔80或贴合面S的供给量进一步增加。因此，连接区域的电迁移耐性进一步提高。
另外，第1金属焊垫11中的第1接触插塞的数量可为2个，也可为4个以上。另外，第2金属焊垫21中的第2接触插塞的数量可为2个、也可为4个以上。
以上，根据第3实施方式，能提供电迁移耐性提高，且可靠性提高的半导体装置。
(第4实施方式)
第4实施方式的半导体装置在第1导电体的另外一部分设置在第1金属层中这点上与第1实施方式的半导体装置不同。以下，有对与第1实施方式重复的内容，省略一部分记述的情况。
图18是第4实施方式的半导体装置的连接区域的示意剖视图。
第4实施方式的非易失性半导体存储器的连接区域在存储器晶片101侧的部分包含第1金属焊垫11、第1层间绝缘层12、第1接触插塞13a、第1布线层14、第1势垒金属膜16、第1抗扩散膜17a、及第1抗扩散膜17b。
第4实施方式的非易失性半导体存储器的连接区域在控制晶片102侧的部分包含第2金属焊垫21、第2层间绝缘层22、第2接触插塞23a、第2布线层24、第2势垒金属膜26、第2抗扩散膜27a、及第2抗扩散膜27b。
第1金属焊垫11为第1金属层的一个例子。第1层间绝缘层12为第1绝缘层的一个例子。第1接触插塞13a为第2导电体的一个例子。
第2金属焊垫21为第2金属层的一个例子。第2层间绝缘层22为第2绝缘层的一个例子。第2接触插塞23a为第1导电体的一个例子。第2布线层24为导电层的一个例子。第2势垒金属膜26为导电膜的一个例子。
第2接触插塞23a的一部分设置在第2金属焊垫21中。另外，第2接触插塞23a的另外一部分设置在第1金属焊垫11中。第2接触插塞23a在第1金属焊垫11侧的端部设置在第1金属焊垫11中。
第2接触插塞23a的一部分由第2金属焊垫21包围。第2接触插塞23a的另外一部分由第1金属焊垫11包围。第2接触插塞23a在第1金属焊垫11侧的端部由第1金属焊垫11包围。
第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离为零。因此，第2接触插塞23a与第1金属焊垫11之间在第1方向上的距离比第2金属焊垫21在第1方向上的厚度小。
根据第4实施方式的连接区域，第2接触插塞23a的另外一部分设置在第1金属焊垫11中，由此，与第1实施方式的连接区域X相比，钛向气孔80或贴合面S的供给量进一步增加。因此，连接区域的电迁移耐性进一步提高。
以上，根据第4实施方式，能提供一种电迁移耐性提高，且可靠性提高的半导体装置。
在第1实施方式到第4实施方式中，定义了贴合面S。在非易失性半导体存储器的最终制品中，有无法明确观察到存储器晶片101及控制晶片102的贴合面S的位置的情况。但是，例如，根据第1金属焊垫11与第2金属焊垫21的位置偏移，能确定贴合面S的位置。
在第1实施方式到第4实施方式中，以具备存储器晶片101作为第1衬底的一个例子，具备控制晶片102作为第2衬底的一个例子的非易失性半导体存储器为例进行了说明。但是，本发明的半导体装置不限定于具备存储器晶片101与控制晶片102的非易失性半导体存储器。例如，也可对具备像素晶片作为第1衬底，具备控制晶片作为第2衬底的光传感器应用本发明。
以上，说明了本发明的若干个实施方式，但这些实施方式是作为例子而提示的，未意图限定发明的范围。这些新颖的实施方式能由其它各种方式实施，在不脱离发明主旨的范围内，能进行各种省略、置换、变更。例如，能将一个实施方式的构成要素与其它实施方式的构成要素置换或变更。这些实施方式或其变化包含在发明范围或主旨内，同时包含在权利要求范围记述的发明与其均等的范围内。
[符号说明]
11 第1金属焊垫(第1金属层)
12 第1层间绝缘层(第1绝缘层)
13a 第1接触插塞(第2导电体)
15 存储器单元阵列
21 第2金属焊垫(第2金属层)
22 第2层间绝缘层(第2绝缘层)
23a 第2接触插塞(第1导电体)
23b 第2接触插塞(第3导电体)
24 第2布线层(导电层)
25 控制电路
26 第2势垒金属膜(导电膜)
100 非易失性半导体存储器(半导体装置)
101 存储器晶片(第1衬底)
102 控制晶片(第2衬底)。

Claims (14)

1.一种半导体装置，具备：
第1衬底，包含：
第1金属层；及
第1绝缘层，包围所述第1金属层；及
第2衬底，包含：
第2金属层，与所述第1金属层相接；
第2绝缘层，包围所述第2金属层，且与所述第1绝缘层相接；及
第1导电体，一部分设置在所述第2金属层中，且沿从所述第2金属层朝所述第1金属层的第1方向延伸。
2.根据权利要求1所述的半导体装置，其中所述第1导电体与所述第1金属层之间在所述第1方向上的距离为所述第2金属层在所述第1方向上的厚度的2分之1以下。
3.根据权利要求1或2所述的半导体装置，其中所述第1导电体与所述第1金属层之间在所述第1方向上的距离，比所述第1绝缘层与所述第2绝缘层的界面与所述第1导电体之间在垂直于所述第1方向的第2方向上的距离小。
4.根据权利要求1或2所述的半导体装置，其中所述第1金属层包含铜(Cu)，所述第2金属层包含铜(Cu)。
5.根据权利要求1或2所述的半导体装置，其中所述第1导电体包含钨(W)。
6.根据权利要求1或2所述的半导体装置，其中所述第2衬底还包含导电膜，设置在所述第1导电体与所述第2金属层之间、及所述第1导电体与所述第2绝缘层之间。
7.根据权利要求6所述的半导体装置，其中所述导电膜包含从由钛(Ti)、钽(Ta)、锰(Mn)、及钴(Co)所组成的群中选择的至少一种金属元素。
8.根据权利要求1或2所述的半导体装置，其中所述第2衬底还包含：导电层，在与所述第2金属层之间隔着所述第1导电体，且电连接到所述第1导电体。
9.根据权利要求1或2所述的半导体装置，其中所述第1导电体与所述第1金属层在所述第1方向上分开。
10.根据权利要求1或2所述的半导体装置，其中所述第1导电体的另外一部分设置在所述第1金属层中。
11.根据权利要求1或2所述的半导体装置，其中所述第1衬底还包含：第2导电体，至少一部分设置在所述第1金属层中，且沿所述第1方向延伸。
12.根据权利要求1或2所述的半导体装置，其中所述第2衬底还包含：第3导电体，至少一部分设置在所述第2金属层中，且沿所述第1方向延伸。
13.根据权利要求1或2所述的半导体装置，其中所述第1衬底还包含存储器单元阵列，且
所述第2衬底还包含控制所述存储器单元阵列的控制电路。
14.根据权利要求13所述的半导体装置，其中所述第1金属层电连接到所述存储器单元阵列，
所述第2金属层电连接到所述控制电路。
CN202110942197.0A 2021-03-16 2021-08-17 半导体装置 Pending CN115084071A (zh)

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