CN108807340B - 用于互连开口的衬垫取代 - Google Patents

用于互连开口的衬垫取代 Download PDF

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CN108807340B
CN108807340B CN201810386725.7A CN201810386725A CN108807340B CN 108807340 B CN108807340 B CN 108807340B CN 201810386725 A CN201810386725 A CN 201810386725A CN 108807340 B CN108807340 B CN 108807340B
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王允愈
D·P·斯坦博
杰弗里·布朗
K·K·H·王
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Abstract

本发明涉及用于互连开口的衬垫取代,其用于在互连结构中进行衬垫取代的结构,以及用于在互连结构中形成衬垫取代的方法。形成包括传导特征的敷金属阶。在该敷金属阶上形成介电层。该介电层包括穿过该介电层垂直延展至该传导特征的开口。在该传导特征受曝露于该开口的底座处的区域上形成黏附层。该黏附层具有与单层或单层一部分相等的厚度。可先在该黏附层上沉积不同组成(例如TiN)的另一层(例如阻障层),再以通过化学气相沉积所沉积的金属填充该开口。

Description

用于互连开口的衬垫取代
技术领域
本发明关于半导体装置制作及集成电路,并且更具体来说,关于用于在互连结构中进行衬垫取代的结构,以及用于在互连结构中形成衬垫取代的方法。
背景技术
可通过前段(FEOL)处理在基材上制作装置结构,并且可将通过中段(MOL)处理及后端(BEOL)处理所制作的互连结构用于连接该FEOL装置结构。互连结构的敷金属阶可包括形成于介电层中、并以金属填充用以形成导线与接触部的开口。
可先将衬垫涂敷至该等开口的表面上再沉积原初生金属。对于先进技术中的高深宽比开口,该衬垫可能无法在凭靠卤基反应剂的金属沉积程序期间适当地保护这些表面。举例而言,六氟化钨是一种常由化学气相沉积用于沉积钨的反应剂。沉积期间释放的氟可能与该衬垫金属起反应而形成金属-氟错合物。该金属-氟错合物保留于该装置结构中,并且随着时间,可能造成损坏,且甚至导致故障。
需要用于在互连结构中进行衬垫取代的改良型结构,以及用于在互连结构中形成衬垫取代的方法。
发明内容
在本发明的一具体实施例中,一种结构包括具有传导特征的敷金属阶以及位在该敷金属阶上的介电层。该介电层中包括垂直延展穿过该传导特征上该介电层的开口。该开口具有使该传导特征上的区域曝露的底座。在该第一传导特征的该区域上涂敷一层件。该层件由导体所构成,并且具有与单层或单层一部分相等的厚度。
在本发明的一具体实施例中,一种方法包括:形成包括传导特征的敷金属阶、在该敷金属阶上形成介电层、以及在该介电层中形成穿过该介电层垂直延展至该传导特征的开口。本方法更包括在该传导特征于该开口的底座处受曝露的区域上形成层件。该层件由导体所构成,并且该层件具有与单层或单层一部分相等的厚度。
附图说明
附图合并于本说明书的一部分并构成该部分,绘示本发明的各项具体实施例,并且连同上述对本发明的一般性说明及下文对具体实施例提供的详细说明,目的是为了阐释本发明的具体实施例。
图1至3根据本发明的具体实施例,为一种结构在处理方法的接续制作阶段时的截面图。
图1A为图1的一部分的放大图。
主要组件符号说明
10 互连结构
12 敷金属阶
13 敷金属阶
14 金属线
15 传导特征
16 衬垫
17 顶端表面
18 衬垫
20 介电层
21 顶端表面
22 开口
24 侧壁
26 底座
28 黏附层
29 层件
30 阻障层
31 层件
34 导体层
36 传导特征
37 晶界
38 晶粒。
具体实施方式
请参阅图1、1A,并且根据本发明的具体实施例,互连结构10包括可在完成FEOL处理后通过中段(MOL)或后端(BEOL)程序在基材上形成的代表性敷金属阶12。代表性敷金属阶12包括介电层(图未示)及嵌埋于该介电层中的传导特征15。可在敷金属阶12下面形成该互连结构的附加敷金属阶(图未示)。互连结构10的不同敷金属阶作用在于使集成电路的诸装置互连,并且可提供电路间连接,或可与输入及输出接端建立接触。
传导特征15包覆金属线14,该金属线由衬垫16包覆于下表面上,并且由衬垫18包覆于上表面上。金属线14可由通过沉积及消去性蚀刻、或通过镶嵌程序形成的导体所构成,诸如铝(Al)或铜(Cu)。衬垫16、18可由钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或这些材料通过物理气相沉积(PVD)沉积的分层组合(例如双层TiN/Ti)所构成。
介电层20涂敷于传导特征15的顶端表面17上,并且可构成互连结构10的上覆于敷金属阶12的敷金属阶13的一部分。介电层20可由电气绝缘介电材料所构成,诸如通过CVD所沉积的硅氧化物(例如二氧化硅(SiO2))或特征在于介电常数(即相对电容率)比二氧化硅(SiO2)的介电常数更小的低k介电材料。
介电层20中形成垂直穿透介电层20的开口22。在一具体实施例中,开口22可具有深度与宽度的高深宽比,诸如4:1的深宽比。开口22可通过蚀刻程序来形成,诸如反应性离子蚀刻(RIE),该蚀刻程序将蚀刻掩膜涂敷至介电层20的顶端表面21。
开口22可具有贯孔、接触孔、沟槽等的尺寸及形状特性。开口22具有自介电层20的顶端表面21起垂直延展而与传导特征15的顶端表面17交会的侧壁24。开口22的侧壁24可如代表性具体实施例中实质垂直对准,或具有顺着从介电层20的顶端表面21至传导特征15的顶端表面17的方向以更大距离会聚的锥度。开口22具有在各别交会转角处连接侧壁24的底端或底座26,并且由介电层20于其侧壁24处设立边界。开口22的底座26使传导特征15的顶端表面17上的区域曝露。
于传导特征15上,跨其顶端表面17上开口22的底座26处曝露的区域涂敷黏附层28与阻障层30作为层堆栈的组件。先形成层件28、30再以原初生导电体填充介电层20中的开口22,并且先形成黏附层28再形成阻障层30。层件29及31分别是由如同层件28及30的材料所构成,也都沉积在介电层20的顶端表面21上。
黏附层28设置成与传导特征15直接接触。阻障层30设置成与黏附层28直接接触。不同于开口22的侧壁24与开口22的底座26交会的转角处及附近,层件28、30都未与介电层20接触。否则,开口22的侧壁24没有层件28、30的各别材料,或沉积层件28、30时侧壁24上仅形成可忽略的厚度。
在一具体实施例中,黏附层28在受沉积时可由元素金属所构成,并且阻障层30可由化合物或合金所构成,其为二或更多种元素的固体混合物。在一具体实施例中,黏附层28可由通过诸如溅镀程序的物理气相沉积(PVD)等定向沉积技巧沉积的钛(Ti)所构成。至少部分因为沉积技巧选择的关系,黏附层28未沉积于侧壁24上,或仅沉积于厚度可忽略的侧壁24上。
阻障层30可由金属所构成,诸如在氮气体流动的环境下由钛的PVD所沉积、或在氮基反应剂的环境下由利用钛基反应剂的CVD所沉积的氮化钛(TiN)。至少部分因为沉积技巧选择的关系,阻障层30未沉积于侧壁24上,或仅沉积于厚度可忽略的侧壁24上。在一替代具体实施例中,阻障层30可由例如溅镀程序的物理气相沉积(PVD)沉积的钨(W)所构成。
图1A展示最清楚的是,阻障层30可包括穿过阻障层30的厚度垂直延展、并在相邻晶粒38之间包括晶界37的柱状晶粒38。柱状晶粒38为该沉积技巧用于形成阻障层30的结果。晶粒38的包括可能降低阻障层30包覆黏附层28的品质。阻障层30亦可能具有不均匀厚度,可能进一步降低阻障层30包覆黏附层28的品质。于开口22在侧壁24附近的底端转角处,阻障层30的包覆可能尤其不良,其可能降低阻障层30对例如氧与氟扩散作用为阻障物的能力。
传导特征15的顶端表面17上位于开口22的底座26处的区域上黏附层28的厚度t1小于跨相同区域的阻障层30的厚度t2。传导特征15的顶端表面上位于开口22的底座26处的区域上黏附层28的厚度可等于单层的一部分或单一单层(即0.5纳米至1.0纳米)。相比之下,阻障层30可更加厚很多,厚度范围例如为五(5)纳米至十(10)纳米。
介电层20的顶端表面21上沉积的层件29、31可比传导特征15上位于开口22的底座26处沉积的层件28、30更厚。厚度差异的原因至少部分可在于开口22具有高深宽比。在一具体实施例中,介电层20的顶端表面21上黏附层28的厚度可以是十(10)纳米的等级,而介电层20的顶端表面21上阻障层30的厚度可以是二十五(25)纳米至五十(50)纳米。
请参阅图2,其中相似的附图标记指图1中及后续制作阶段时相似的特征,沉积促成在开口22内侧形成传导特征36的导体层34。导体层34可由从一或多种在气相的反应剂通过化学气相沉积(CVD)程序在加热基材上沉积为固体材料的金属所构成,诸如钨(W)。在CVD期间当作反应剂用于将导体层34的金属沉积的先驱物来源可含有卤素,诸如氟(F),并且可与含有卤素的还原气体起反应。举例而言,钨可通过CVD使用由诸如六氟化钨(WF6)的卤化钨所构成的先驱物来源来沉积。导体层34的沉积可以是多步骤程序,其涉及在开口22内侧沉积成核层,后面跟着沉积主体填充层。导体层34亦过量填充开口22,并且在层件29、31上形成,将介电层20的顶端表面21包覆。传导特征36的位置为开口22内侧层件29的层阶处或下面的层阶。
请参阅图3,其中相似的附图标记指图2中及后续制作阶段时相似的特征,化学机械研磨(CMP)程序可用于将层件29、31、34从顶端表面21移除,并且用于平坦化导体层34。化学机械研磨程序期间的材料移除组合了磨擦、以及将层件29、31、34的靶材料研磨与移除的蚀刻效应。传导特征36留在开口22内侧,并且与传导特征15在开口22的底座26处耦接。黏附层28与阻障层30为置于传导特征36与传导特征15之间的中介结构15。
沉积导体层34之前,开口22的底座26处黏附层28中的金属与另一元素化学性结合,以使得黏附层28的金属并不自由且起化学反应。举例而言,可先使内含于黏附层28中的金属与从传导特征15上所吸收氧出来的氧结合,然后再使黏附层28沉积。举例而言,金属钛(Ti)对于氧具有高亲和性,从而黏附层28中的元素钛与开口22的底座26处传导特征15上所吸收的氧、或开口22的底座26处传导特征15上原生表面氧化物中存在的氧轻易地组合。黏附层28的反应性金属比习知的衬垫配置具有更小厚度,因此不含有可用于参与化学反应的自由金属钛。
诸如卤素(例如:氟)的反应副产物通过形成导体层34的CVD反应来产生及释放。黏附层28的化学惰性可操作成用以防止这些反应副产物的原子或分子在开口22的底座26处聚集,尤其是在底座26处开口22的转角位置累积。具体而言,黏附层28中的金属(例如:钛)与另一元素(例如:氧)的结合可防止该金属与源自于CVD反应的卤素(例如:氟)起反应。使导体层34沉积之前,与传导特征15介接处黏附层28中自由金属原子(例如:钛原子)的消除可防止形成含卤素化学错合物,诸如含氟的TiFx之类的化学错合物。与开口22的转角处相关联的含卤素化学错合物的不存在性、以及与传导特征15的介接可降低接触电阻,并且可降低因侵蚀而起的可靠度问题。
习知的阻障层的作用在于保护习知的黏附层免于在曝露至空气时起氧化作用,并且在于阻止氟穿透该阻障层与该黏附层中的钛起反应。在本发明的具体实施例中,黏附层28比习知的阻障层具有显著更小的厚度,缺乏可用于与通过CVD反应所产生的氟或另一卤素起反应的自由金属(例如:Ti)。氟或另一卤素受允许穿过阻障层30,但无法与黏附层28起反应。与习知的阻障层形成对比,阻障层30并非必须作用为防止氟穿透的阻障物。阻障层30的作用至少部分亦在于防止黏附层28进一步氧化,当与氧起反应时,超出其初始氧化状态,可使其电阻增加。
因为黏附层28是通过定向沉积程序所形成,而且出自黏附层28的材料未在沉积期间于开口22的侧壁24上形成,传导特征36的尺寸比在习知程序中更大,衬垫层在习知程序中是通过保形沉积程序所形成,会将开口22的侧壁24包覆。通过保形沉积程序所形成的层件具有大约固定且与涂布特征几何形状无关的厚度。层件28、30取代会将开口22的侧壁24包覆的习知衬垫。
在具体实施例中,黏附层28的存在可允许阻障层30以更低质量(例如:包覆范围更小)形成。举例而言,阻障层30可通过以柱状晶粒38形成膜件(图1A)的定向程序(例如:PVD)来沉积。类似于黏附层28,形成阻障层30的材料未于介电层20中开口22的侧壁24上形成,因为沉积阻障层30的定向沉积程序属于非保形。
本方法如以上所述用于制作集成电路芯片。产生的集成电路芯片可由制作商以空白晶圆形式(例如:作为具有多个未封装芯片的单一晶圆)、当作裸晶粒、或以封装形式来配送。在后例中,芯片嵌装于单芯片封装(例如:塑料载体,有导线黏贴至母板或其它更高层阶载体)中或多芯片封装(例如:具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。无论如何,芯片可与其它芯片、离散电路组件、及/或其它信号处理装置整合,作为中间产品或或最终产品的部分。
本文中对「垂直」、「水平」等用语的参照属于举例,并非限制,用来建立参考架构。「水平」一词于本文中使用时,定义为与半导体基材的习知平面平行的平面,与其实际三维空间方位无关。「垂直」与「正交」等词指垂直于水平的方向,如刚才的定义。「侧向」一词指水平平面内的方向。诸如「上面」及「下面」等词用于指出组件或结构彼此的相对位置,与相对高度截然不同。
「连接」或「耦接」至另一组件、或与该另一组件「连接」或「耦接」的特征可直接连接或耦接至其它组件,或者,反而可出现一或多个中介组件。如无中介组件,一特征可「直接连接」或「直接耦接」至另一组件。如有至少一个中介组件,一特征可「间接连接」或「间接耦接」至另一组件。
本发明的各项具体实施例的描述已为了说明目的而介绍,但用意不在于穷举或受限于所揭示的具体实施例。许多修改及变例对本领域技术人员将会显而易见,但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让本领域技术人员能够理解本文中所揭示的具体实施例而选择。

Claims (17)

1.一种半导体结构,包含:
包括第一传导特征的敷金属阶;
位在该敷金属阶上的介电层,该介电层包括垂直延展穿过该第一传导特征上该介电层的开口,并且该开口具有使该第一传导特征上的一区域曝露的底座;
位在该第一传导特征的该区域上的第一层,该第一层由包含钛与氧的导体所构成,并且该第一层具有与单层或单层一部分相等并在0.5纳米至1.0纳米的范围内的厚度;以及
位在该开口中的第二传导特征,该第二传导特征由钨所构成,
其中,该第一层垂直介于该第二传导特征与该第一传导特征之间。
2.如权利要求1所述的半导体结构,其中,该第一层与该敷金属阶中的该第一传导特征直接接触。
3.如权利要求1所述的半导体结构,其中,该开口由从该介电层的顶端表面延展至该第一传导特征的顶端表面的侧壁所约束,并且在该第一层与该介电层的该顶端表面之间的该开口的该侧壁没有该第一层,使得该第一层仅位于该第一传导特征的该区域上。
4.如权利要求1所述的半导体结构,更包含:
介于该第一层与该第二传导特征之间的第二层,
其中,该第二层具有比该第一层的该厚度更大的厚度。
5.如权利要求4所述的半导体结构,其中,该开口由从该介电层的顶端表面延展至该第一传导特征的顶端表面的侧壁所约束,并且在该第一层与该介电层的该顶端表面之间的该开口的该侧壁没有该第一层,使得该第一层仅位于该第一传导特征的该区域上。
6.如权利要求4所述的半导体结构,其中,该第二层由钨所构成。
7.如权利要求4所述的半导体结构,其中,该第二层由氮化钛所构成。
8.如权利要求1所述的半导体结构,其中,该开口由侧壁所约束,并且该第二传导特征于该开口的该侧壁处与该介电层直接接触。
9.如权利要求1所述的半导体结构,其中,该开口为接触开口。
10.一种形成半导体装置的方法,包含:
形成包括第一传导特征的敷金属阶;
在该敷金属阶上形成介电层;
在该介电层中形成穿过该介电层垂直延展至该第一传导特征的开口;
在该第一传导特征于该开口的底座处受曝露的区域上形成第一层,以及
在该开口中形成第二传导特征,
其中,该第一层由包含钛与氧的导体所构成,该第一层垂直介于该第二传导特征与该第一传导特征之间,该第二传导特征由钨所构成,并且该第一层具有与单层或单层一部分相等并在0.5纳米至1.0纳米的范围内的厚度。
11.如权利要求10所述的方法,其中,该开口由从该介电层的顶端表面延展至该第一传导特征的顶端表面的侧壁所约束,该第一层利用定向沉积程序所形成,使得在该第一层与该介电层的该顶端表面之间的该开口的该侧壁没有该第一层,并且该第一层仅位于该第一传导特征的该区域上。
12.如权利要求10所述的方法,其中,该第一层与该敷金属阶中的该第一传导特征直接接触。
13.如权利要求10所述的方法,更包含:
在该第一层与该第二传导特征之间形成第二层,
其中,该第二层具有比该第一层的该厚度更大的厚度。
14.如权利要求13所述的方法,其中,该开口由从该介电层的顶端表面延展至该第一传导特征的顶端表面的侧壁所约束,并且在该第一层与该介电层的该顶端表面之间的该开口的该侧壁没有该第一层,使得该第一层仅位于该第一传导特征的该区域上。
15.如权利要求13所述的方法,其中,该第二层由通过物理气相沉积进行沉积的氮化钛所构成。
16.如权利要求13所述的方法,其中,该第二层由通过物理气相沉积进行沉积的钨所构成。
17.如权利要求10所述的方法,其中,该开口由侧壁所约束,并且该第二传导特征于该开口的该侧壁处与该介电层直接接触。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW405223B (en) * 1998-07-28 2000-09-11 United Microelectronics Corp Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole
US6348402B1 (en) * 1999-03-18 2002-02-19 Kabushiki Kaisha Toshiba Method of manufacturing a copper interconnect
CN1373512A (zh) * 2001-02-28 2002-10-09 国际商业机器公司 具有精确导体的互连结构
CN101101872A (zh) * 2006-07-04 2008-01-09 株式会社半导体能源研究所 显示装置的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093645A (en) 1997-02-10 2000-07-25 Tokyo Electron Limited Elimination of titanium nitride film deposition in tungsten plug technology using PE-CVD-TI and in-situ plasma nitridation
US5926737A (en) 1997-08-19 1999-07-20 Tokyo Electron Limited Use of TiCl4 etchback process during integrated CVD-Ti/TiN wafer processing
US6176983B1 (en) * 1997-09-03 2001-01-23 Vlsi Technology, Inc. Methods of forming a semiconductor device
US6189209B1 (en) 1998-10-27 2001-02-20 Texas Instruments Incorporated Method for reducing via resistance in small high aspect ratio holes filled using aluminum extrusion
US6977437B2 (en) 2003-03-11 2005-12-20 Texas Instruments Incorporated Method for forming a void free via
US7476618B2 (en) * 2004-10-26 2009-01-13 Asm Japan K.K. Selective formation of metal layers in an integrated circuit
US7651934B2 (en) * 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US7432195B2 (en) * 2006-03-29 2008-10-07 Tokyo Electron Limited Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features
US7407875B2 (en) 2006-09-06 2008-08-05 International Business Machines Corporation Low resistance contact structure and fabrication thereof
US8288276B2 (en) * 2008-12-30 2012-10-16 International Business Machines Corporation Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW405223B (en) * 1998-07-28 2000-09-11 United Microelectronics Corp Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole
US6348402B1 (en) * 1999-03-18 2002-02-19 Kabushiki Kaisha Toshiba Method of manufacturing a copper interconnect
CN1373512A (zh) * 2001-02-28 2002-10-09 国际商业机器公司 具有精确导体的互连结构
CN101101872A (zh) * 2006-07-04 2008-01-09 株式会社半导体能源研究所 显示装置的制造方法

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