TWI781341B - 具有互鎖的金屬至金屬接合的電子裝置及製造具有互鎖的金屬至金屬接合的電子裝置的方法 - Google Patents

具有互鎖的金屬至金屬接合的電子裝置及製造具有互鎖的金屬至金屬接合的電子裝置的方法 Download PDF

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TWI781341B
TWI781341B TW108129317A TW108129317A TWI781341B TW I781341 B TWI781341 B TW I781341B TW 108129317 A TW108129317 A TW 108129317A TW 108129317 A TW108129317 A TW 108129317A TW I781341 B TWI781341 B TW I781341B
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metal
post
electronic device
copper
cavity
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TW108129317A
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TW201947720A (zh
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波拉 巴洛葛盧
可陸提斯 史溫格
駱 休莫勒
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美商艾馬克科技公司
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Abstract

本揭示內容提供一種用於在電子裝置中實施金屬至金屬接合的結構及方法。舉例來說，而且沒有任何限制意義，本揭示內容的各項觀點提供一種運用被配置成用以增強金屬至金屬接合的互鎖結構的結構及方法。

Description

具有互鎖的金屬至金屬接合的電子裝置及製造具有互鎖的金屬至金屬接合的電子裝置的方法
本發明關於具有互鎖的金屬至金屬接合的半導體產物及製造其之方法。
用於形成電氣連接的現有方法，舉例來說，在積體電路之中所使用的方法，皆有缺點。舉例來說，焊接雖然普遍；但是，焊料卻有相對低的熔點，其會對後續的處理步驟以及最終的產物造成溫度限制。另外，焊料原子還有沿著銅接點遷移的傾向，從而會在被焊接的接點老化時改變它們的電氣特性以及機械特性。直接金屬至金屬接合(舉例來說，銅至銅(Cu-Cu)接合、...等)雖然不需要用到焊料；但是，經過證實，因為高溫、高壓、以及冗長的停留時間(dwell time)的關係而使得組裝製程變得複雜、增加組裝製程的成本、並且增加組裝製程的延遲時間，所以，無法以節省成本的製程來大規模生產此些接合。
本發明所要解決的傳統金屬至金屬接合的技術問題有高溫、高壓和冗長的停留時間...等。本發明的金屬至金屬接合是具有製程步驟簡單、成本 低、停留時間短的優點的金屬至金屬接合。本揭示內容的各項觀點提供一種用於在電子裝置中實施金屬至金屬接合的結構及方法。舉例來說，而且沒有任何限制意義，本揭示內容的各項觀點提供一種運用被配置成用以增強金屬至金屬接合的互鎖結構的結構及方法。
100:金屬至金屬接合製程
110:基板
112:第一銅接點
120:基板
122:第二銅接點
150:金屬至金屬接合製程
200:金屬至金屬接合製程
210:基板
212:第一銅接點
220:基板
222:第二銅接點
250:金屬至金屬接合製程
300:金屬至金屬接合製程
310:基板
312:第一銅接點
320:基板
322:第二銅接點
400:金屬至金屬接合製程
412:第一銅接點
413:凸形表面
422:第二銅接點
423:凹形表面
432:第一接觸點
434:第二接觸點
495:深度
497:垂直向半途
500:金屬至金屬接合製程
512:第一銅接點
513:凸形表面
522:第二銅接點
523:凹形表面
551:區域
553:區域
561:周圍區域
562:接合區域
563:中心區域
D:高度
P:高度
600:金屬至金屬接合製程
612:第一銅接點
613:凸形表面
622:第二銅接點
623:凹形表面
651:中間區域
653:中間區域
655:中心區域
657:周圍區域
659:周圍區域
661:周圍區域
662:中間區域
663:中心區域
R1:曲率半徑
R2:曲率半徑
R3:曲率半徑
R4:曲率半徑
700:金屬至金屬接合製程
771:角邊區域
772:角邊區域
773:角邊區域
774:角邊區域
781:角邊區域
782:角邊區域
783:角邊區域
784:角邊區域
785:角邊區域
786:角邊區域
787:角邊區域
788:角邊區域
800A:金屬至金屬接合製程
800B:金屬至金屬接合製程
800C:金屬至金屬接合製程
800D:金屬至金屬接合製程
800E:金屬至金屬接合製程
810:基板
811:觸墊
812:介電層
813:底層凸塊金屬(UBM)晶種層
821:遮罩
831:底層凸塊金屬(UBM)
832:互連結構
900A:金屬至金屬接合製程
900B:金屬至金屬接合製程
900C:金屬至金屬接合製程
932:互連結構
圖1所示的係根據本揭示內容各項觀點的範例金屬至金屬接合以及接合方法。
圖2所示的係根據本揭示內容各項觀點的範例互鎖金屬至金屬接合以及接合方法。
圖3所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的透視圖。
圖4所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的剖視圖。
圖5所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的剖視圖。
圖6所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的透視圖。
圖7所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的透視圖。
圖8A至8E所示的係根據本揭示內容各項觀點之形成一互連結構的方法的各個階段的透視圖。
圖9A至9C所示的係根據本揭示內容各項觀點之形成一互連結構的方法的各 個階段的透視圖。
下面的討論藉由提供本揭示內容範例以提出本揭示內容的各項觀點。此些範例為非限制性，且因此，本揭示內容各項觀點的範疇不應該受限於本文所提供範例的任何特殊特徵。在下面的討論中，「舉例來說」、「示範性」等詞組為非限制性並且大體上和「舉例來說，但是沒有限制意義」同義。
如本文中的用法，「及/或」的意義為藉由「及/或」來連接的列表之中的項目的任何一或更多者。舉例來說，「x及/或y」的意義為三要素集合{(x)、(y)、(x,y)}之中的任何要素。換言之，「x及/或y」的意義為「x與y之中的一或兩者」。於另一範例中，「x、y、及/或z」的意義為七要素集合{(x)、(y)、(z)、(x,y)、(x,z)、(y,z)、(x,y,z)}之中的任何要素。換言之，「x、y、及/或z」的意義為「x、y、以及z之中的一或更多者」。
本文中所使用的術語僅係為達成說明特殊範例的目的而沒有限制本揭示內容的意圖。如本文中的用法，除非文中額外清楚提及，否則單數的形式亦希望包含複數形式。進一步要瞭解的係，當本說明書中使用到「包括」、「包含」、「具有」、以及類似用詞時係表明所述特徵圖樣、數字、步驟、操作、元件、及/或器件的存在，但是並不排除有一或多個其它特徵圖樣、數字、步驟、操作、元件、器件、及/或其群組的存在，甚至並不排除加入一或多個其它特徵圖樣、數字、步驟、操作、元件、器件、及/或其群組。
應該瞭解的係，雖然本文中可以使用「第一」、「第二」、...等用詞來說明各種元件；不過，此些元件並不應該受限於此些用詞。此些用詞僅係用來區分其中一個元件以及另一個元件。因此，舉例來說，下文所討論的第一元件、第一器件、或是第一區段亦可被稱為第二元件、第二器件、或是第二區 段，其並不會脫離本揭示內容的教示內容。同樣地，本文亦可能利用「上方」、「下方」、「側邊」、以及類似用詞以相對的方式來區分其中一個元件和另一個元件。然而，應該瞭解的係，器件可以不同的方式來配向，舉例來說，一半導體裝置可以向側邊翻轉，俾使得其「頂端」表面面向水平方向並且使得其「側邊」表面面向垂直方向，其並不會脫離本揭示內容的教示內容。除此之外，本文件中還使用「在...之上」來表示「在...之上」以及「直接在...之上」(舉例來說，沒有任何中間層)兩種意義。
在圖式中，為清楚解釋起見，各種維度(舉例來說，層厚度、寬度、...等)可能會被放大。除此之外，在各種範例的所有討論中，相同的元件符號則被用來表示相同的元件。
本文中的討論雖然大體上提供以銅至銅接合為背景的範例；然而，應該瞭解的係，本揭示內容的範疇並不受限於此。舉例來說，本揭示內容的各項觀點同樣適用於其它金屬至金屬接合(Au至Au金接合、Ag至Ag接合、...等)。另外，舉例來說，亦可以運用各種合金(舉例來說，銅合金、銀合金、金合金、、...等)。應該注意的係，金屬可能還包括各種程度的雜質。舉例來說，一銅柱基本上可以由100%的銅所形成；但是，亦可能具有特定百分比的雜質。
於本文中所提供的一範例施行方式中，一種製造半導體裝置的方法包括：提供一第一基板，其包括一第一銅接點結構，該第一銅接點結構包括一圓頂形狀末端；提供一第二基板，其包括一第二銅接點結構，該第二銅接點結構包括一碟狀末端，其具有一碟深度；配接該圓頂形狀末端以及該碟狀末端，俾使得該圓頂形狀末端會在該圓頂形狀末端之周長的多個點處接觸該碟狀末端，並且僅位在深入該碟狀凹腔之中介於該碟深度之5%與95%之間的距離處；以及將該已配接的圓頂形狀末端與碟狀末端擠壓在一起，用以形成一銅至銅接合。本文中還提供一種根據此範例方法所生產的電子裝置。
於本文中所提供的一範例施行方式中，一種製造半導體裝置的方法包括：提供一第一基板，其包括一由一金屬所製成的第一金屬接點結構，該第一金屬接點結構包括一凸形末端，該凸形末端包括一具有第一凸形曲率半徑的第一凸形部以及一具有第二凸形曲率半徑的第二凸形部；提供一第二基板，其包括一由該金屬所製成的第二金屬接點結構，第二金屬接點結構包括一凹形末端，該凹形末端包括一具有第一凹形曲率半徑的第一凹形部，其中，該第一凹形曲率半徑小於該第一凸形曲率半徑並且該第一凹形曲率半徑大於該第二凸形曲率半徑；配接該凸形末端以及該凹形末端，俾使得該第二凸形部會在該凹形末端之周長的多個點處接觸該凹形末端並且該第一凸形部不會接觸該凹形末端；以及將該已配接的凸形末端與凹形末端擠壓在一起，用以形成一由該金屬所製成的金屬至金屬接合。本文中還提供一種根據此範例方法所生產的電子裝置。
於本文中所提供的一範例施行方式中，一種製造半導體裝置的方法包括：提供一第一基板，其包括一由一金屬所製成的第一金屬接點結構，該第一金屬接點結構包括一凸形末端；提供一第二基板，其包括一由該金屬所製成的第二金屬接點結構，第二金屬接點結構包括一凹形末端，該凹形末端包括一中心點、一邊緣、以及一沿著介於該中心點與該邊緣之間的該凹形末端的一表面的中心至邊緣距離；配接該凸形末端以及該凹形末端，俾使得該凸形末端會在該凸形末端之周長的多個點處接觸該凹形末端並且僅位在和該中心點相隔大於該中心至邊緣距離之10%與90%的距離處；以及將該已配接的凸形末端與凹形末端擠壓在一起，用以形成一由該金屬所製成的金屬至金屬接合。本文中還提供一種根據此範例方法所生產的電子裝置。
圖1所示的係一範例金屬至金屬接合製程。如圖在符號100處所示，兩個基板110、120具有要被結合的第一銅接點112和第二銅接點122，於本 文中該些銅接點亦可被稱為接點。基板110與120可以包括任何各式各樣的特徵。舉例來說，該些基板110與120中的一或兩者可以包括一半導體晶粒(舉例來說，具有晶圓形式、具有平板形式、具有獨特切晶的形式、...等)。另外，舉例來說，該些基板110與120中的一或兩者可以包括一中介片(舉例來說，被形成在一載板之上(舉例來說，玻璃載板、金屬載板、矽載板、...等)，其會在該中介片形成之後被移除)。除此之外，舉例來說，該些基板110與120中的一或兩者可以包括一層疊基板(舉例來說，封裝基板、主機板、...等)。據此，本揭示內容的範疇不應該受限於任何特殊類型基板的特徵。
圖中所示的第一銅接點112與第二銅接點122雖然係為達成解釋的目的；但是，舉例來說，其可以包括任何各式各樣不同類型互連結構的特徵。舉例來說，此些第一銅接點112與第二銅接點122中的一或兩者可以包括一金屬柱體或杆體(舉例來說，具有大體上垂直的側表面)。另外，舉例來說，此些第一銅接點112與第二銅接點122中的一或兩者可以包括一金屬觸墊或線路。除此之外，舉例來說，此些第一銅接點112與第二銅接點122中的一或兩者亦可以包括一大於橫向寬度的縱向長度(或是高度)；及/或此些第一銅接點112與第二銅接點122中的一或兩者可以包括一大於縱向長度(或是高度)的橫向寬度。應該注意的係，於各種範例施行方式中，第一銅接點112以及第二銅接點122可以由相同的金屬(舉例來說，銅、...等)所形成；但是，情況未必為如此。於另一範例施行方式中，一中間金屬可以被形成在該第一銅接點112以及該第二銅接點122之間。
本文中所示的許多範例雖然以圓柱形狀來顯示此些第一銅接點112與第二銅接點122；不過，亦可以運用任何各式各樣的形狀。舉例來說，該些第一銅接點112與第二銅接點122中的一或兩者可以具有矩形剖面(舉例來說，垂直於一垂直軸所切割的剖面、垂直於一水平軸所切割的剖面、...等)。另外，舉例來說，該些第一銅接點112與第二銅接點122中的一或兩者可以具有一大體 上為多邊形(舉例來說，N邊，其中，N為整數)的剖面(舉例來說，垂直於一垂直軸所切割的剖面、垂直於一水平軸所切割的剖面、...等)。除此之外，舉例來說，該些第一銅接點112與第二銅接點122中的一或兩者可以具有一圓形或橢圓形剖面(舉例來說，垂直於一垂直軸所切割的剖面、垂直於一水平軸所切割的剖面、...等)。
進一步言之，本文中所示的許多範例雖然顯示第一銅接點112(舉例來說，柱體或杆體、長柱體或杆體、...等)的縱向長度(舉例來說，在圖中的垂直向)長於該第二銅接點122(舉例來說，觸墊或基座、短柱體或杆體、...等)；不過，應該瞭解的係，此些相對長度僅為解釋性而非限制性。舉例來說，該第一銅接點112與該第二銅接點122可以有相等長度、該第二銅接點122可以長過該該第一銅接點112、...等。另外，本文中大體上所示的第一銅接點112與第二銅接點122雖然具有相同或雷同的軸寬度(舉例來說，圖中的水平維度)；不過，應該瞭解的係，此些相對寬度僅為解釋性而非限制性。舉例來說，該第一銅接點112可以窄於該第二銅接點122、該第二銅接點122可以窄於該第一銅接點112、...等。另外，舉例來說，該第一銅接點112的寬度(舉例來說，在其最寬部分處的最大寬度)可以小於該第二銅接點122的寬度(舉例來說，在其最寬部分處的最大寬度)、該第二銅接點122的寬度(舉例來說，在其最寬部分處的最大寬度)可以小於該第一銅接點112的寬度(舉例來說，在其最寬部分處的最大寬度)、...等。
圖中雖然僅顯示其中一個配接的互連結構對；不過，應該瞭解的係，可以在該些基板上形成許多相同的結構。舉例來說，圖中所示的第一銅接點112與第二銅接點122可以為被用來電氣及/或機械性耦合基板110與120的數十個或數百個相同或雷同結構中的其中一者。舉例來說，此些接點可以相對緊密的分隔(舉例來說，間距為50微米或更小、30微米或更小、...等)。
於各種施行方式中，第一銅接點112及/或第二銅接點122可以任 何各式各樣的方式來形成。舉例來說，一金屬觸墊或線路可以被形成在一矽基板之上並且經由一介電層(或鈍化層)而露出。應該注意的係，此觸墊或線路可以為一多層信號分佈結構中的一部分。一或更多個晶種層及/或底層凸塊金屬(Under Bump Metal，UBM)層可以被沉積(舉例來說，濺鍍、電鍍、...等)在該觸墊或線路之上，並且舉例來說，該(些)接點可以經由一介電模板之中的開口被形成在此(些)晶種層及/或UBM層之上，該介電模板接著便可以被移除。於各種施行方式中，一焊帽雖然可以被形成在該接點之上；不過，根據本揭示內容的各項觀點，所形成的接點或是其尖端可以維持裸禿(舉例來說，沒有焊劑)。
據此，本揭示內容的範疇不應該受限於該些互連接點(舉例來說，第一銅接點112及/或第二銅接點122、...等)的特殊特徵或是受限於製造此些接點的任何特殊方式。
在符號150處，基板110、120會被結合(或是配接)在一起，以便讓第一銅接點112接觸第二銅接點122。為在該些第一銅接點112與第二銅接點122之間的介面處形成Cu-Cu接合，通常會施加高壓與高熱維持一段很長的停留時間。倘若該些第一銅接點112與第二銅接點122的兩個配接表面為乾淨(舉例來說，完全乾淨、...等)的話，那麼，隨機原子運動最終將會導致原子橫越該兩個表面之間的介面，因此會弄髒該介面，並且隨著時間經過，該介面可能完全消失。然而，因為原子運動通常為隨機(舉例來說，大部分為隨機或者完全隨機)，所以，這係一種緩慢的過程。舉例來說，範例壓力可以大於200個百萬帕斯卡(200MPa)；舉例來說，範例溫度可以大於300℃；以及舉例來說，範例停留時間的大小可以為一個小時至數個小時。
現在參考圖2，此圖所示的係根據本揭示內容各項觀點的一種範例互鎖金屬至金屬接合以及接合方法。圖2的範例結構及方法或是其任何部分可以和本文中所討論的其它類似結構或方法(舉例來說，針對圖1以及3至9)有共同 的任何或是所有特徵。
如符號200處所示，兩個基板210與220具有要被結合的第一銅接點212與第二銅接點222。如本文中的討論(舉例來說，針對圖1、...等)，該些基板210與220可以包括任何各式各樣的特徵及/或可以任何各式各樣的方式來形成。同樣如本文中的討論(舉例來說，針對圖1、...等)，該些第一銅接點212與第二銅接點222可以包括任何各式各樣的特徵及/或可以任何各式各樣的方式來形成。
如本文中所作的詳細討論，該第一銅接點212包括一凸形(舉例來說，圓頂形)末端，並且該第二銅接點222包括一凹形(舉例來說，碟狀)末端。
舉例來說，該第一銅接點212可以運用金屬電鍍操作來形成。該第一銅接點212的該末端(舉例來說，要接觸該第二銅接點222之對應末端的末端)的形狀可以被形成為具有凸形形狀。舉例來說，此形狀可以藉由調整各種電鍍製程參數而達成。舉例來說，於一範例施行方式中，一凸形末端可以藉由提高在電鍍製程中所運用的整平劑(leveler)的濃度而達成。舉例來說，藉由將被用來取得一大體上扁平末端的整平劑的濃度加倍可以達成大於該接點之整體高度的10%或15%的凸形末端(或是圓頂)高度。
舉例來說，該第二銅接點222可以運用金屬電鍍操作來形成。該第二銅接點222的該末端(舉例來說，要接觸該第一銅接點212之對應末端的末端)的形狀可以被形成為具有凹形形狀。舉例來說，此形狀可以藉由調整電鍍製程參數而達成。舉例來說，於一範例施行方式中，一凹形末端可以藉由降低在電鍍製程中所運用的整平劑的濃度而達成。舉例來說，藉由將被用來取得一大體上扁平末端的整平劑的濃度減半可以達成大於該接點之整體高度的10%或15%的凹形末端(或是碟狀體)深度。
於一範例施行方式中，在該些接點的該些末端中各點處的凸面及 /或凹面程度可以藉由調整單一電鍍製程之中的整平劑的濃度及/或藉由調整複數個連續電鍍製程之中的整平劑的濃度來調整。應該注意的係，於包含複數個連續電鍍製程的範例施行方式中，每一個電鍍製程並不需要覆蓋完全相同的面積，因而可以很有彈性地塑形該些接點的末端。
在符號250處，如同在圖1的符號150處，基板210、220會被結合(或是配接)在一起，以便讓第一銅接點212接觸第二銅接點222。為在該些第一銅接點212與第二銅接點222之間的介面處形成Cu-Cu接合，可以施加壓力與熱量維持一段停留時間。倘若該些第一銅接點212與第二銅接點222的兩個配接表面為乾淨(舉例來說，完全乾淨、...等)的話，那麼，隨機原子運動最終將會導致原子橫越該兩個表面之間的介面，因此會弄髒該介面，並且隨著時間經過，該介面可能完全消失。然而，倘若第一銅接點212與第二銅接點222的配接介面確切地匹配的話，那麼，這仍可能係一種緩慢的過程，通常如同圖1的範例方法，因為原子運動通常為隨機(舉例來說，大部分為隨機或者完全隨機)。因此，根據本揭示內容的各項觀點，如本文中的討論，該些配接表面可能會刻意不匹配，用以增強金屬至金屬接合。
根據本揭示內容的各項觀點，一底層填充層可以被形成在該些基板210與220之間。舉例來說，在該些第一銅接點212與第二銅接點222之間進行附接之後，一底層填充層可以被形成在該些基板210與220之間及/或包圍該些第一銅接點212與第二銅接點222(舉例來說，藉由毛細管底層填充、模製底層填充、...等)。於另一範例中，在該些第一銅接點212與第二銅接點222之間進行附接之前，可以在該些基板210與220的一或更多者之上形成一前置塗敷的底層填充層(舉例來說，利用非導電膏(Non-Conductive Paste，NCP)、...等)。舉例來說，此底層填充層形成製程可以在該些第一銅接點212與第二銅接點222的配接之前先被實施而不會污染它們的配接末端。
參考圖3，此圖所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的透視圖300。圖3的範例結構及方法或是其任何部分可以和本文中所討論的其它類似結構或方法(舉例來說，針對圖2以及4至9)有共同的任何或是所有特徵。
如本文中的討論，該些互連結構的末端可以被形成用以進行不完美配接。圖4所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的透視圖。圖4的範例結構及方法或是其任何部分可以和本文中所討論的其它類似結構或方法(舉例來說，針對圖1至3以及5至9)有共同的任何或是所有特徵。
第一(或頂端)銅接點412包括一凸形表面413，並且第二(或底部)銅接點422包括一面向該凸形表面413的凹形表面423。圖式400為當第一銅接點412以及第二銅接點422沿著一縱軸對齊排列時沿著貫穿此些接點的該縱軸所取得的剖視圖。在剖視圖400之中所示的凸形表面413在第一接觸點432處以及第二接觸點434處接觸凹形表面423。如本文中的討論，此接點可以在三個維度中延伸圍繞該凸形表面413(舉例來說，形成一個圓、...等)。
凹形表面423包括一介於該凹形表面423的頂端周圍邊緣以及該凹面的一底部點(舉例來說，位在凹形表面423的中心點、...等)之間的深度495。圖中所示的第一接觸點432以及第二接觸點434約略在該頂端周圍邊緣以及該底部點之間的垂直向半途497處。於各種範例施行方式中，接觸點432以及434的垂直向位置可以在從該頂端周圍邊緣的垂直水平處進入該凹形區(舉例來說，該碟狀區、...等)達到該深度495的25%至75%。於各種其它範例施行方式中，接觸點432以及434的垂直向位置可以在從該頂端周圍邊緣的垂直水平處進入該凹形凹面達到該深度495的10%至90%，或者，從該頂端周圍邊緣的垂直水平處進入該凹形區達到該深度495的5%至95%，或者，從該頂端周圍邊緣的垂直水平處進入該凹形區達到該深度495的0%至95%。
舉例來說，第一接觸點432以及第二接觸點434亦可以位於凹形表面423中從該底部(或中心)點至該頂端周圍邊緣的距離的25%與75%之間。於另一範例施行方式中，舉例來說，第一接觸點432以及第二接觸點434亦可以位於凹形表面423中從該底部點至該頂端周圍邊緣的距離的10%與90%之間，或者，位於凹形表面423中從該底部點至該頂端周圍邊緣的距離的5%與95%之間，或者，位於凹形表面423中大於從該底部點至該頂端周圍邊緣的距離的5%或10%(舉例來說，其可以一直延伸至該頂端周圍邊緣)。
如圖4中所示，總作用力FT可以被施加用以將第一銅接點412以及第二銅接點422擠壓在一起。因為在接觸點432以及434處，凸形表面413以及凹形表面423以沒有正交於該作用力FT之方向的某個角度彼此接觸，所以，作用力FT會有一個擠壓作用力FC分量，其會操作用以將凸形表面413以及凹形表面423直接擠壓在一起(舉例來說，以正交的方式作用於接觸點432以及434處的介面)。於本文中，此作用力FC亦可以被稱為正向作用力。此作用力FT還可以有一個剪力作用力FS分量，其會沿著凸形表面413以及凹形表面423之間的介面以正切的方式操作在接觸點432以及434處。
擠壓作用力FC和剪力作用力FS的結合會操作在第一銅接點412以及第二銅接點422的金屬上(舉例來說，銅、...等)，導致塑性變形(plastic deformation)。接著，此塑性變形可能會提高凸形表面413以及凹形表面423之間的原子擴散的程度。接著，此經提高的擴散程度可以導致用以在第一銅接點412以及第二銅接點422之間創造有效的銅至銅接合所需要的壓力數額、溫度、及/或停留時間的整體下降。
端視凸形表面413以及凹形表面423的變形量而定，在該金屬至金屬(舉例來說，銅至銅、...等)接合已經完成之後，在凸形表面413以及凹形表面423的個別部分之間可能會有間隙。應該注意的係，情況未必如此。舉例來說， 在接合製程期間，凸形表面413及/或凹形表面423可能會發生足量的變形而消弭凸形表面413以及凹形表面423之間的一部分或全部間隙。
圖5所示的係根據本揭示內容各項觀點的範例互鎖結構的剖視圖。圖5的範例結構及方法或是其任何部分可以和本文中所討論的其它類似結構或方法(舉例來說，針對圖1至4以及6至9)有共同的任何或是所有特徵。舉例來說，圖5的上半部為沿著該縱軸(舉例來說，本文中的範例圖示中的上/下方向)所切割的剖視圖，並且舉例來說，圖5的下半部為靠近該些金屬至金屬接合的區域的俯視圖。
如本文中所提及，即使在該金屬至金屬接合製程之後，在凸形表面513以及凹形表面523的不同個別部分之間可能會有間隙。範例圖式500提供此些間隙的解釋性範例。舉例來說，為達清楚解釋起見，此些間隙的的尺寸可能被放大。
範例500包括一中間區域562，其對應於凸形表面513及/或凹形表面523的塑性變形以及第一銅接點512與第二銅接點522之間的金屬至金屬接合。舉例來說，該中間區域562包括區域551與區域553，如上方剖視圖之中所示。於一範例施行方式中，該中間區域562形成一環體，其圍繞凸形表面513並且在凹形表面523裡面。另外，舉例來說，在凸形表面513(舉例來說，其尖端或是中心)以及凹形表面523的底部(或是中心)之間的高度(舉例來說，最大高度)D的中心區域563中會有一間隙。除此之外，舉例來說，在凸形表面513(舉例來說，其周圍邊緣)以及凹形表面523的周圍邊緣之間的高度(舉例來說，最大高度)P的周圍區域561中也會有一間隙。
不過，如本文中的解釋，凸形表面513及/或凹形表面523的變形雖然可能足以消弭此些表面之間的間隙；但是，情況未必如此。舉例來說，凸形表面513以及凹形表面523可以彼此接觸並且在中心區域563之中及/或在周圍 區域561之中彼此金屬至金屬接合。如果此些接合存在的話，舉例來說，它們強度可能會弱於接合區域562之中的接合；但是，情況未必如此。舉例來說，於一範例施行方式中，位於凸形表面513以及凹形表面523之間的中心區域563之中及/或在周圍區域561之中的介面線在該接合製程之後可能會比中間區域562之中的介面線更為顯見(舉例來說，比較看得見、...等)。
圖5的範例500雖然大體上被圖解為具有對稱的特徵；不過，此對稱性並非必要。舉例來說，第一接點512及/或第二接點522可以為不對稱。接著，此不對稱可能會導致第一接點512及第二接點522被接合的區域之中的不對稱。舉例來說，參考圖5的接合區域562，此接合區域562可能會相對於第一接點512及/或第二接點522的中心為偏離中心(或者偏移)(舉例來說，偏離接點寬度的至少5%或10%、偏離至少大於製造公差的某個百分比、...等)。另外，舉例來說，接合區域562的其中一側可以薄於另一側(舉例來說，區域551可以短於區域553，反之亦可)，舉例來說，薄於任一區域寬度的至少5%或10%、薄於至少大於製造公差的某個百分比、...等。除此之外，舉例來說，接合區域562的其中一側可以該中心為基準以不同於另一側的方式被定位(舉例來說，區域551可以該中心為基準被偏移，而區域553則沒有被偏移或是被偏移不同的數額)。進一步舉例來說，圖5的左側處所示的間隙P可以不同於圖5的右側處的類似間隙(舉例來說，為間隙P寬度的至少5%或10%、為大於製造公差的某個百分比、...等。)
各種範例凸形表面以及凹形表面的形狀亦可以一或更多個曲率半徑來描述。此特徵的非限制性範例提供在圖6處，圖6所示的係根據本揭示內容各項觀點的範例互鎖結構以及接合方法的透視圖。圖6的範例結構及方法或是其任何部分可以和本文中所討論的其它類似結構或方法(舉例來說，針對圖1至5以及7至9)有共同的任何或是所有特徵。
在範例圖式600中，第一金屬接點612包括一凸形表面613。舉例 來說，該凸形表面613在一中心區域655之中的一部分可以具有R2的曲率半徑。另外，舉例來說，該凸形表面613在中間區域651與653之中的一部分可以具有R3的曲率半徑。除此之外，舉例來說，該凸形表面613在周圍區域657與659之中的一部分可以具有R4的曲率半徑。
另外，在範例圖式600中，第二金屬接點622包括一凹形表面623，其具有R1的曲率半徑。應該注意的係，圖中所示的凹形表面623雖然有單一曲率半徑；不過，此特徵係為清楚解釋起見。舉例來說，凹形表面623的複數個部分可以各自包括一不同的個別曲率半徑。於該範例圖式600中，R2>R1以及R3<R1。除此之外，R3<R4<R1。於另一範例施行方式中，R4=R3。
應該注意的係，在接合製程期間，由於凸形表面613及/或凹形表面623的變形的關係，該曲率半徑在進行該金屬至金屬接合的區域之中通常會變為相同。於一第一範例施行方式中，其中，金屬至金屬接合僅發生在中間區域662之中(舉例來說，其包含中間區域651與653)，在中心區域663之中以及周圍區域661之中在凸形表面613及凹形表面623之間仍然有一間隙。於此範例施行方式中，由於變形的關係，凸形表面613及凹形表面623的曲率半徑會在中間區域662之中變成大體上相同，R2將仍然大於R1，並且R4將仍然小於R1。
於金屬至金屬接合最後會發生在中心區域663以及中間區域662之中的範例施行方式中，舉例來說，由於變形的關係，凸形表面613及凹形表面623的曲率半徑會在中心區域663以及中間區域662之中變成大體上相同。於金屬至金屬接合最後會發生在周圍區域661以及中間區域662之中的範例施行方式中(除了發生在中心區域663之中之外，或者不會發生在中心區域663之中)，舉例來說，由於變形的關係，凸形表面613及凹形表面623的曲率半徑會在周圍區域661以及中間區域662之中變成大體上相同。
如本文中的討論(舉例來說，針對圖5)，圖6的範例600雖然大體 上被圖解為具有對稱的特徵；但是，此特徵並非必要。舉例來說，第一接點612及/或第二接點622可以為不對稱。接著，此不對稱可能會導致第一接點612及第二接點622被接合的區域之中的不對稱。舉例來說，參考圖6的接合區域662，此接合區域662可能會相對於第一接點612及/或第二接點622的中心為偏離中心(或者偏移)(舉例來說，偏離接點寬度的至少5%或10%、偏離至少大於製造公差的某個百分比、...等)。另外，舉例來說，接合區域662的其中一側可以薄於另一側(舉例來說，中間區域651可以短於中間區域653，反之亦可)，舉例來說，薄於任一區域寬度的至少5%或10%、薄於至少大於製造公差的某個百分比、...等。除此之外，舉例來說，接合區域662的其中一側可以該中心為基準以不同於另一側的方式被定位(舉例來說，中間區域651可以該中心為基準被偏移，而中間區域653則沒有被偏移或是被偏移不同的數額)。進一步舉例來說，圖6的左側處所示的R3(及/或R4)可以不同於圖6的右側處所示的R3(及/或R4)(舉例來說，為R3(及/或R4)的至少5%或10%、為大於製造公差的某個百分比、...等。)。
如本文中的討論，該些金屬接點可以為圓柱形、矩形、大體上多邊形、、...等。於各種範例施行方式中，在該凸形表面及該凹形表面之間雖然並不需要一連續的接合線或區域；但是，於其它範例施行方式中亦可能有一連續的接合線或區域。圖7所示的係根據本揭示內容各項觀點的範例互鎖結構的透視圖。於此些範例中，該些金屬至金屬接合區域完全分開，而並非連續。
舉例來說，於圖7的符號700處的範例圖式中，一具有正方形剖面的接點可能變形並且在四個角邊區域771、772、773、以及774處接合。另外，舉例來說，於圖7的符號750處的範例圖式中，一具有八角形剖面的接點可能變形並且在八個角邊區域781至788處接合。應該注意的係，如本文中的討論，由於接合製程期間該些接點的變形的關係，即使於該些第一金屬接點與第二金屬接點之間的初始接觸僅發生在完全分開的點處的情況中，當該些凸形表面及/或 凹形表面變形時，此接觸仍然可能展開而創造多個連續耦合的接合區域，並且甚至會展開而在整個凸形表面及/或凹形表面上方創造一全面性的接合區域。
如本文中所提及，於該些範例中雖然僅大體上圖解與討論一個配接的互連結構對；不過，應該瞭解的係，亦可以在該些基板上形成許多個完全相同的結構。舉例來說，圖中所示的接點可以為被用來電氣及/或機械性耦合該些基板的數十個或數百個相同或雷同結構中的其中一者。舉例來說，此些接點可以被排列成一陣列、一實心矩陣、一方形或矩形排列、一直線、多條平行直線、...等。應該瞭解的係，所有該些接點雖然可能雷同於本文中所討論的接點；不過，所有該些接點並不需要相同。舉例來說，於一具有複數個該些接點的電子器件的範例施行方式中，該些接點中的第一部分可以不同於該些接點中的第二部分。另外，舉例來說，該些接點中的第一部分可以為如本文中的討論，而第二部分則可以具有實質上扁平的末端。除此之外，舉例來說，該些接點中的第一部分可以為不對稱，而第二部分可以為對稱。進一步舉例來說，該些接點中的第一部分可以具有第一高度、寬度、或是間距，而該些接點中的第二部分則可以具有不同於第一高度、寬度、或是間距的第二高度、寬度、或是間距。
如本文中所提及，該基板可以為各種形式，其包含晶圓形式。因此，本揭示內容的範疇包含晶圓級凸塊(舉例來說，銅柱晶圓級凸塊)。凸塊製程的範例(舉例來說，晶圓級凸塊製程、...等)會提供在圖8與9之中。
圖8A至8E所示的係根據本揭示內容各項觀點之形成一互連結構的方法的各個階段的透視圖。圖8A至8E中所示的範例結構及/或方法或是其任何部分可以和本文中所示的其它類似結構及/或方法(舉例來說，針對圖1至7以及9)有共同的任何或是所有特徵。圖中雖然顯示僅形成一個晶圓級凸塊；不過，應該瞭解的係，此形成製程可以在單一晶圓上重複數百次或數千次。另外應該注意的係，本揭示內容的範疇並不受限於晶圓級操作。舉例來說，此處所揭示的 任何或所有操作皆可以在單獨晶粒、晶粒面板、晶粒晶圓上被實施。
在圖8A處表現一包括一觸墊811(舉例來說，一I/O觸墊、一接合觸墊、...等)的基板810。應該注意的係，雖然可以有任何數量的觸墊；不過，為清楚解釋起見，此處僅顯示一個觸墊。舉例來說，基板810可以包括一半導體晶粒(舉例來說，一矽半導體晶粒、一半導體晶粒的有作用側、一電氣連接至前側的半導體晶粒的背側、...等)。
舉例來說，一接合觸墊811可以被形成用以在多個接點位置處覆蓋基板810的頂端部分。舉例來說，觸墊811可以包括任何各式各樣的導體材料(舉例來說，銅、鋁、銀、金、鎳、它們的合金、...等)。
一介電層812(其亦可被稱為鈍化層)會被形成在該基板810之上，舉例來說，用以覆蓋基板810的頂端側。舉例來說，該介電層812可以覆蓋該接合觸墊811的側表面及/或該接合觸墊811的頂端表面的外周圍。該介電層812可以包括任何各式各樣類型的材料，舉例來說，無機材料(舉例來說，氮化矽(Si3N4)、氧化物(SiO2)、SiON、...等)及/或有機材料(舉例來說，聚醯亞胺(PI)、環苯丁烯(BCB)、聚苯并噁唑纖維(PBO)、雙馬來醯亞胺-三氮雜苯(BT)、酚系樹脂、環氧樹脂、...等)；但是，本揭示內容的範疇並不受限於此。舉例來說，介電層812可以藉由任何各式各樣的製程來形成(舉例來說，旋塗、印刷、噴塗、燒結、熱氧化、物理氣相沉積(Physical Vapor Deposition，PVD)、化學氣相沉積(Chemical Vapor Deposition，CVD)、原子層沉積(Atomic Layer Deposition，ALD)、...等)。舉例來說，該介電層812可以包括一孔徑，經由該孔徑露出觸墊811的一部分。
一UBM晶種層813可以被形成在該介電層812的上方及/或經由該介電層812中的孔徑而露出的觸墊811部分的上方。舉例來說，該UBM晶種層813可以包括任何各式各樣的導體材料(舉例來說，銅、金、銀、金屬、...等)。該UBM 晶種層813可以任何各式各樣的方式來形成(舉例來說，濺鍍、無電極電鍍、CVD、PVD、ALD、...等)。
如圖8B中所示，一遮罩821(或是模板)會被形成及/或圖樣化在UBM晶種層813的上方，用以定義一要於其中形成一UBM及/或互連結構(舉例來說，金屬柱體、...等)的區域。舉例來說，該遮罩821可以包括一光阻(PhotoResist，PR)材料或是其它材料，其可以被圖樣化用以覆蓋要於其中形成一UBM及/或互連結構的區域以外的區域。
如圖8C中所示，UBM 831係被形成在經由遮罩821露出的UBM晶種層813之上。該UBM 831可以包括任何各式各樣的材料(舉例來說，鈦、鉻、鋁、鈦/鎢、鈦/鎳、銅、它們的合金、...等)。該UBM 831可以任何各式各樣的方式被形成在UBM晶種層813之上(舉例來說，電鍍、無電極電鍍、濺鍍、CVD、PVD、原子層沉積(ALD)、...等)。
同樣如圖8C中所示，互連結構832係被形成在UBM 831之上。該互連結構832可以包括任何各式各樣的特徵。舉例來說，該互連結構832可以和本文中所討論的任何或所有互連結構(舉例來說，第一銅接點212、312、422、512、612、第二銅接點222、322、422、522、622、...等)具有共同的任何或所有特徵。舉例來說，該互連結構832可以包括銅(舉例來說，純銅、有某些雜質的銅、...等)、銅合金、鎳、...等。
如本文中的討論，互連結構832可以被形成為具有一凸形(或是圓頂形)末端，舉例來說，藉由調整整平劑濃度。舉例來說，藉由將被用來取得一大體上扁平末端的整平劑的濃度加倍可以達成大於該互連結構832之整體高度的10%或15%的凸形末端(或是圓頂)高度。
如圖8D處所示(舉例來說，對照於圖8C)，遮罩821(舉例來說，光阻、...等)會被剝除。遮罩821可以任何各式各樣的被移除(舉例來說，化學剝除、 灰化、...等)。如圖8E處所示(舉例來說，對照於圖8D)，UBM晶種層813(舉例來說，至少沒有被互連結構832覆蓋的部分)會被移除(舉例來說，化學蝕刻、...等)。應該注意的係，在該晶種層813的蝕刻期間，舉例來說，至少該UBM晶種層813的一橫向邊緣部分會被蝕刻。舉例來說，此蝕刻可以在互連結構832及/或UBM 831底下造成一下切量。
如本文中的討論，一互連結構可被形成為具有一凹形(或是碟狀)末端，取代凸形(或是圓頂形)末端。此形成製程的一範例顯示在圖9A至9C之中。
圖9A至9C所示的係根據本揭示內容各項觀點之形成一互連結構的方法的各個階段的透視圖。舉例來說，圖9中所示的方法可以和圖8中所示的方法有共同的任何或是所有特徵。因此，本討論將大體上聚焦在差異處。圖9A至9C中所示的範例結構及/或方法或是其任何部分可以和本文中所示的其它類似結構及/或方法(舉例來說，針對圖1至8)有共同的任何或是所有特徵。圖中雖然顯示僅形成一個晶圓級凸塊；不過，應該瞭解的係，此形成製程可以在單一晶圓上重複數百次或數千次。另外應該注意的係，本揭示內容的範疇並不受限於晶圓級操作。舉例來說，此處所揭示的任何或所有操作皆可以在單獨晶粒、晶粒面板、晶粒晶圓上被實施。
如圖9A中所示，如同圖8C，UBM 831係被形成在經由遮罩821露出的UBM晶種層813之上。該UBM 831可以包括任何各式各樣的材料(舉例來說，鈦、鉻、鋁、鈦/鎢、鈦/鎳、銅、它們的合金、...等)。該UBM 831可以任何各式各樣的方式被形成在UBM晶種層813之上(舉例來說，電鍍、無電極電鍍、濺鍍、CVD、PVD、原子層沉積(ALD)、...等)。
同樣如圖9A中所示，如同圖8C的互連結構832，該互連結構832係被形成在UBM 831之上。該互連結構832可以包括任何各式各樣的特徵。舉例來說，該互連結構832可以和本文中所討論的任何或所有互連結構(舉例來說，第 一銅接點212、312、412、512、612、第二銅接點222、322、422、522、622、...等)具有共同的任何或所有特徵。舉例來說，該互連結構832可以包括銅(舉例來說，純銅、有某些雜質的銅、...等)、銅合金、鎳、...等。
如本文中的討論，互連結構932可以被形成為具有一凹形(或是碟狀)末端(不同於圖8的範例互連結構832)，舉例來說，藉由調整整平劑濃度。舉例來說，於一範例施行方式中，藉由降低在電鍍製程之中所運用的整平劑的濃度可以取得凹形末端。舉例來說，藉由將被用來取得一大體上扁平末端的整平劑的濃度減半可以達成大於該互連結構932之整體高度的10%或15%的凹形末端(或是碟狀體)深度。
如圖9B處所示(舉例來說，對照於圖9A)，遮罩821(舉例來說，光阻、...等)會被剝除。遮罩821可以任何各式各樣的被移除(舉例來說，化學剝除、灰化、...等)。如圖9C處所示(舉例來說，對照於圖9B)，UBM晶種層813(舉例來說，至少沒有被互連結構832覆蓋的部分)會被移除(舉例來說，化學蝕刻、...等)。應該注意的係，在該晶種層813的蝕刻期間，舉例來說，至少該UBM晶種層813的一橫向邊緣部分會被蝕刻。舉例來說，此蝕刻可以在互連結構832及/或UBM 831底下造成一下切量。
總結來說，本揭示內容的各項觀點提供一種用於在電子裝置中實施金屬至金屬接合的結構及方法。舉例來說，而且沒有任何限制意義，本揭示內容的各項觀點提供一種運用被配置成用以增強金屬至金屬接合的互鎖結構的結構及方法。前文雖然已經參考特定觀點及範例作說明；不過，熟習本技術的人士便會瞭解，可以進行各種改變並且以等效例來取代，其並不會脫離本揭示內容的範疇。此外，亦可以進行許多修正，以便讓一特殊情況或材料適應於本揭示內容的教示內容，而沒有脫離其範疇。所以，本揭示內容並不希望受限於已揭的特殊範例；確切地說，本揭示內容涵蓋落在隨附申請專利範圍之範疇裡 面的所有範例。
100:金屬至金屬接合製程
110:基板
112:第一銅接點
120:基板
122:第二銅接點
150:金屬至金屬接合製程

Claims (20)

  1. 一種電子裝置，其包括：上基板；金屬柱體，其包含第一金屬，所述金屬柱體包括耦接到所述上基板的上柱體末端、下柱體末端以及在所述上柱體末端和所述下柱體末端之間的柱體側壁；下基板；金屬接觸結構，其包含第二金屬，所述第二金屬是與所述第一金屬相同類別的金屬，所述金屬接觸結構包括耦接到所述下基板的下側以及包含凹腔的上側；以及在所述下柱體末端和所述金屬接觸結構的所述上側之間的金屬至金屬接合，其中所述金屬至金屬接合被定位在所述凹腔之中的接合區域之中，但是不在所述凹腔之中的周圍區域之中；以及所述接合區域位於所述凹腔中的與所述周圍區域相比不同的深度處。
  2. 如請求項第1項所述的電子裝置，其中在所述凹腔之中的所述周圍區域包含橫向間隙，所述橫向間隙環繞所述金屬柱體。
  3. 如請求項第2項所述的電子裝置，其中所述橫向間隙沒有導體材料。
  4. 如請求項第1項所述的電子裝置，其中所述接合區域在所述凹腔內是比所述周圍區域還深。
  5. 如請求項第1項所述的電子裝置，其中：在所述凹腔之中的中心區域沒有所述金屬至金屬接合，所述接合區域在所述周圍區域和所述中心區域之間；並且沿著所述金屬柱體的中心線，所述中心區域包括在所述第一金屬和所述第 二金屬之間的垂直間隙。
  6. 如請求項第1項所述的電子裝置，其中所述柱體側壁包含垂直的側壁，所述垂直的側壁沒有延伸到所述凹腔之中。
  7. 如請求項第6項所述的電子裝置，其中所述柱體側壁包含垂直的側壁，所述垂直的側壁沒有接合到所述金屬接觸結構。
  8. 如請求項第1項所述的電子裝置，其中：在垂直橫截面中，所述金屬至金屬接合的至少一部份是彎曲狀的；並且所述金屬至金屬接合包括直接銅至銅接合。
  9. 如請求項第1項所述的電子裝置，其中在垂直橫截面中，所述下柱體末端是彎曲狀的並且具有包含多個不同曲率半徑的輪廓。
  10. 如請求項第1項所述的電子裝置，其中所述上基板包含矽並且所述下基板包含矽。
  11. 一種電子裝置，其包括：上基板；金屬柱體，其包含第一金屬，所述金屬柱體包括耦接到所述上基板的上柱體末端、下柱體末端以及在所述上柱體末端和所述下柱體末端之間的柱體側壁；下基板；金屬接觸結構，其包含第二金屬，所述第二金屬是與所述第一金屬相同類別的金屬，所述金屬接觸結構包括耦接到所述下基板的下側以及包含凹腔的上側；以及在所述下柱體末端和所述金屬接觸結構的所述上側之間的金屬至金屬接合，其中：所述金屬至金屬接合是無焊料的；所述金屬至金屬接合被定位在所述凹腔之中；並且 在垂直橫截面中，所述下柱體末端的至少一部份是彎曲狀的。
  12. 如請求項第11項所述的電子裝置，其中在垂直橫截面中，所述下柱體末端包含多個不同曲率半徑。
  13. 如請求項第11項所述的電子裝置，其中所述柱體側壁包含垂直的側壁，所述垂直的側壁沒有延伸到所述凹腔之中。
  14. 如請求項第11項所述的電子裝置，沿著所述金屬柱體的中心線，其包含在所述第一金屬和所述第二金屬之間的垂直間隙。
  15. 如請求項第11項所述的電子裝置，其中：在垂直橫截面中，所述金屬接觸結構的所述上側的至少一部份是彎曲狀的；所述第一金屬包含銅；所述第二金屬包含銅；並且所述金屬至金屬接合包含在所述第一金屬和所述第二金屬之間的直接銅至銅接合。
  16. 如請求項第11項所述的電子裝置，其中在垂直橫截面中，所述金屬接觸結構的所述上側的所述凹腔包含多個不同凸曲率半徑。
  17. 一種製造電子裝置的方法，所述方法包括：形成第一組件，其包含：上基板；以及包含第一金屬的金屬柱體，所述金屬柱體包括耦接到所述上基板的上柱體末端、下柱體末端以及在所述上柱體末端和所述下柱體末端之間的柱體側壁；形成第二組件，其包含：下基板；以及包含與所述第一金屬相同類型金屬的第二金屬的金屬接觸結構，所述 金屬接觸結構包括耦接到所述下基板的下側以及包含凹腔的上側；以及在所述下柱體末端和所述金屬接觸結構的所述上側之間形成金屬至金屬接合，其中：所述金屬至金屬接合被定位在所述凹腔之中的接合區域之中，但是不在所述凹腔之中的周圍區域之中；以及所述接合區域位於所述凹腔中的與所述周圍區域相比不同的深度處。
  18. 如請求項第17項所述的方法，其中在所述凹腔之中的所述周圍區域包含橫向間隙，所述橫向間隙環繞所述金屬柱體。
  19. 如請求項第17項所述的方法，其中所述柱體側壁包括垂直的側壁，所述垂直的側壁沒有延伸到所述凹腔之中。
  20. 如請求項第17項所述的方法，其中：在垂直橫截面中，所述金屬至金屬接合的至少一部份是彎曲狀的；並且所述金屬至金屬接合包括直接銅至銅接合。
TW108129317A 2016-01-06 2016-01-29 具有互鎖的金屬至金屬接合的電子裝置及製造具有互鎖的金屬至金屬接合的電子裝置的方法 TWI781341B (zh)

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6436531B2 (ja) * 2015-01-30 2018-12-12 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US9559075B1 (en) * 2016-01-06 2017-01-31 Amkor Technology, Inc. Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof
KR20170098462A (ko) * 2016-02-22 2017-08-30 삼성전기주식회사 패키지 및 그의 제조방법
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US10096569B2 (en) * 2017-02-27 2018-10-09 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US10600755B2 (en) * 2017-08-10 2020-03-24 Amkor Technology, Inc. Method of manufacturing an electronic device and electronic device manufactured thereby
CN108091633A (zh) * 2017-12-13 2018-05-29 广东工业大学 纳米多孔铜互连层结构及其制备方法
EP3747043A4 (en) * 2018-02-01 2022-02-23 Hrl Laboratories, Llc INTEGRATED CIRCUIT WITH METALLIC LATCHING STRUCTURE
CN110246801B (zh) * 2018-03-07 2021-07-16 长鑫存储技术有限公司 连接结构及其制造方法、半导体器件
TWI697078B (zh) * 2018-08-03 2020-06-21 欣興電子股份有限公司 封裝基板結構與其接合方法
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) * 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
JP7319808B2 (ja) * 2019-03-29 2023-08-02 ローム株式会社 半導体装置および半導体パッケージ
US11063011B1 (en) * 2020-02-20 2021-07-13 Nanya Technology Corporation Chip and wafer having multi-layered pad
US11742253B2 (en) 2020-05-08 2023-08-29 Qualcomm Incorporated Selective mold placement on integrated circuit (IC) packages and methods of fabricating
FR3129622B1 (fr) * 2021-11-26 2023-10-27 Nelumbo Digital Système pour déformer une structure utile

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5558271A (en) * 1993-04-30 1996-09-24 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US6355504B1 (en) * 1998-02-27 2002-03-12 Micron Technology, Inc. Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive
US6674647B2 (en) * 2002-01-07 2004-01-06 International Business Machines Corporation Low or no-force bump flattening structure and method
US20080314627A1 (en) * 2006-04-07 2008-12-25 Murata Manufacturing Co., Ltd. Electronic component and method for manufacturing the same
TW200919678A (en) * 2007-06-18 2009-05-01 Elpida Memory Inc Implementation structure of semiconductor package

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6469394B1 (en) * 2000-01-31 2002-10-22 Fujitsu Limited Conductive interconnect structures and methods for forming conductive interconnect structures
JP3735526B2 (ja) 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
JP3972813B2 (ja) * 2002-12-24 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
WO2008126812A1 (ja) * 2007-04-06 2008-10-23 Taisei Plas Co., Ltd. 銅合金複合体とその製造方法
KR20090047776A (ko) * 2007-11-08 2009-05-13 삼성전자주식회사 반도체 소자 및 그 형성 방법
US11134598B2 (en) * 2009-07-20 2021-09-28 Set North America, Llc 3D packaging with low-force thermocompression bonding of oxidizable materials
TWI394247B (zh) 2010-01-26 2013-04-21 Powertech Technology Inc 免用焊料之金屬柱晶片連接構造與方法
KR101185454B1 (ko) 2010-09-27 2012-10-02 앰코 테크놀로지 코리아 주식회사 칩 적층형 반도체 패키지
JP2012248732A (ja) * 2011-05-30 2012-12-13 Elpida Memory Inc 半導体チップ、半導体装置および半導体装置の製造方法
KR101324105B1 (ko) 2012-03-28 2013-10-31 광주과학기술원 피형 산화아연 박막의 제조방법
US8796849B2 (en) 2012-10-22 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Metal bump joint structure
US9670377B2 (en) * 2014-03-04 2017-06-06 Namics Corporation Underfill composition for encapsulating a bond line
US9559075B1 (en) * 2016-01-06 2017-01-31 Amkor Technology, Inc. Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5558271A (en) * 1993-04-30 1996-09-24 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US6355504B1 (en) * 1998-02-27 2002-03-12 Micron Technology, Inc. Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive
US6674647B2 (en) * 2002-01-07 2004-01-06 International Business Machines Corporation Low or no-force bump flattening structure and method
US20080314627A1 (en) * 2006-04-07 2008-12-25 Murata Manufacturing Co., Ltd. Electronic component and method for manufacturing the same
TW200919678A (en) * 2007-06-18 2009-05-01 Elpida Memory Inc Implementation structure of semiconductor package

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