CN101897013A - 互连结构及其制造方法 - Google Patents

互连结构及其制造方法 Download PDF

Info

Publication number
CN101897013A
CN101897013A CN200880120776XA CN200880120776A CN101897013A CN 101897013 A CN101897013 A CN 101897013A CN 200880120776X A CN200880120776X A CN 200880120776XA CN 200880120776 A CN200880120776 A CN 200880120776A CN 101897013 A CN101897013 A CN 101897013A
Authority
CN
China
Prior art keywords
head
interconnection structure
post portion
base portion
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200880120776XA
Other languages
English (en)
Other versions
CN101897013B (zh
Inventor
黄志权
冯福来
樊伟
吕海晶
陆汶庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agency for Science Technology and Research Singapore
Nanyang Technological University
Original Assignee
Agency for Science Technology and Research Singapore
Nanyang Technological University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency for Science Technology and Research Singapore, Nanyang Technological University filed Critical Agency for Science Technology and Research Singapore
Publication of CN101897013A publication Critical patent/CN101897013A/zh
Application granted granted Critical
Publication of CN101897013B publication Critical patent/CN101897013B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00095—Interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

互连结构，用于将第一和第二组件互连的互连结构，用于将多组件堆叠结构和基底互连的互连结构，以及制造互连结构的方法。互连结构包括：基部，形成在第一组件的安装表面上；柱部，从基部起与安装表面基本垂直地延伸；和头部，形成在柱部上并且具有比柱部大的横向尺寸，其中，基部和柱部由同种材料一体地形成。

Description

互连结构及其制造方法
技术领域
本发明概括地涉及互连结构，涉及用于将第一和第二组件互连的互连结构，涉及用于将多组件堆叠结构和基底互连的互连结构，涉及互连结构的制造方法。
背景技术
接合的线、焊料凸点和金属柱是形成在通常在硅晶片上制造的微型器件上的常见微型结构。引线接合(wire bonding)是用于电子器件互连的最早技术。热超声引线接合是普遍使用的技术。传统的引线接合允许输入/输出(I/O)焊盘接合仅位于靠近芯片边缘的芯片周边上。可以在多个芯片和基底之间接合低型面且柔软的长环线。但是，长线互连需付出的代价是高阻抗以及寄生电感和电容。引线接合通常不适合于高频和RF应用。而且，在硅芯片的有源部分上的引线接合可以损坏在其下面的灵敏电路。这个约束限制了最优的功率分布和芯片尺寸收缩的设计。
倒装芯片(flip chip)技术是微电子工业的重要发展。优化的倒装芯片器件对于线焊器件提供了成本、可靠性和性能方面的提高。倒装芯片器件还具有更好的电气性能以及低阻抗、电感和电容。借助于焊料的自对准特征，使用焊料凸点的倒装芯片封装具有极好的产率。倒装芯片上的面阵列互连格式允许横跨芯片表面分布大量的I/O。这改善了间距和功率分布。由于在裸片上面没有附加的封装材料，倒装芯片具有最小可能的尺寸。随着倒装芯片阵列间距降低，倒装芯片上的互连焊料凸点直径相应地降低。
降低焊料凸点大小的一个不足是在互连接点中IMC对块材焊料的体积比增加。因为IMC是易碎的并且会降低焊料接点的疲劳寿命，所以焊料接点中更高百分比的IMC是不希望的。另一劣势是随着焊料凸点大小的降低，电流密度增加。随着电流密度增加，电迁移将成为封装互连中需要考虑的可靠性问题。
图1示出典型的焊料凸点互连100的示意图。典型的焊料凸点互连100包括凸点下合金(UBM)102、焊料凸点104和匹配基底接合焊盘106。但是，典型的焊料凸点互连100具有几个内在缺点。在回熔焊接期间，焊料凸点104将塌下并且当凝固时变成桶形。这限制了焊料接点的高度和间距以及焊料凸点互连100在高密度的小型化封装中的应用。此外，焊料凸点104的截顶球形末端108是主要的负载承受点，高压力集中发生在这些球形末端108处。UBM 102与焊料凸点104相互作用并且使焊料接点变弱。IMC-焊料界面110处的脆化和这些IMC-焊料界面110中的热膨胀系数(CTE)失配产生了裂纹开裂和裂纹扩展的节点。
与焊料凸点不同，铜(Cu)柱在回流焊接期间并不塌下。柱可以被更紧密地封装在一起，这增加了互连密度。如果直接在芯片金属焊盘上进行电镀，则可避免在芯片界面上形成金属间化合物(IMC)。还消除了焊料扩散和与芯片上的薄膜相互作用的问题。此外，因为铜的机械特性比焊料的要好得多，所以在芯片界面上不太可能发生失效。还可以对柱结构进行设计，使得焊料上的应力集中和剪应变降低。
图2a和2b示出分别具有更大柱直径和更小柱直径的传统柱互连设计200的示意图。传统的柱互连设计200的关键问题是，当柱202的直径变化时焊料体积204和其润湿表面206发生改变。与在图2a中所示具有更大直径的柱202相比，在图2b中所示具有更小直径的柱202增加顺应性。但是，当柱202的直径变得更小时，润湿表面206减小。润湿表面206的减小可能影响接点可靠性。此外，焊料凸点不可以被设置在具有变化柱直径的器件上，因为这将导致非平面性。
因此，需要提供可替换的互连结构，以及试图解决上面提到的问题至少其中之一的方法。
发明内容
依照本发明的第一方面，本发明提供了互连结构，包括：基部，形成在第一组件的安装表面上；柱部，从所述基部起与所述安装表面垂直基本地延伸；和头部，形成在所述柱部上并且具有比所述柱部大的横向尺寸，其中，所述基部和所述柱部由同种材料一体地形成。
所述基部可以具有比所述柱部大的横向尺寸。
所述基部、所述柱部和所述头部可以由所述同种材料一体地形成。
所述互连结构可以进一步包括在所述头部和所述柱部之间形成的中间层，所述中间层包括与所述同种材料不同的材料。
所述中间层可以包括TiW和Cu、Ti和Cu、或Cr和Cu。
所述基部可以形成在接触层上，所述接触层在所述第一组件的所述安装表面上形成。
所述接触层可以包括TiW和Cu、Ti和Cu或者Cr和Cu。
所述同种材料可以包括金属或者适合于电镀的导电材料。
所述金属可以包括由Cu、Ni和Au组成的组中的一种或多种。
所述柱部和所述头部可以具有相同的横截面形状。
所述柱部和所述头部可以具有不同的横截面形状。
所述柱部和所述基部可以具有相同的横截面形状。
所述柱部和所述基部可以具有不同的横截面形状。
所述头部和所述基部可以具有相同的横截面形状。
所述头部和所述基部可以具有不同的横截面形状。
所述头部可以具有被布置面向所述第一组件将被安装到的第二组件的表面。
所述表面可以是凸出的。
所述表面可以是平坦的。
介电或钝化层可以被沉积在所述第一组件上，使得所述柱部和所述基部或者被封装在内或者保持暴露。
所述基部、所述柱部和所述头部至少其中之一可以均匀地涂有或选择性地涂有从由润湿层、扩散阻挡层和抗氧化层组成的组中选择的一个或多个。
依照本发明的第二方面，本发明提供了用于将第一和件第二组件互连的互连结构，所述互连结构包括：基部，形成在所述第一组件的安装表面上；柱部，从所述基部起与所述安装表面基本垂直地延伸；和头部，形成在所述柱部上并且具有比所述柱部大的横向尺寸；接触焊盘，形成在所述第二组件的安装表面上；和连接部，用于把所述互连结构的所述头部连接到所述接触焊盘；其中，所述基部和所述柱部由同种材料一体地形成。
用于把所述互连结构的所述头部连接到所述接触焊盘的所述连接部可以包括由焊料、粘性接合、表面活化接合、压力接合和扩散接合组成的组中的一种或多种。
焊料凸点可以分别形成在所述头部和所述接触焊盘的面对表面之间。
所述头部和所述接触焊盘可以基本由焊料封装。
依照本发明的第三方面，本发明提供了用于互相连接多组件堆叠结构和基底的互连结构，所述互连结构包括：第一基部，形成在所述堆叠结构的第一组件的第一安装表面上；第一柱部，从所述第一基部起与所述第一安装表面基本垂直地延伸；和第二头部，形成在所述第二柱部上并且具有比所述第二柱部大的横向尺寸；第二基部，形成在所述堆叠结构的第二组件的第二安装表面上；第二柱部，从所述第二基部起与所述第二安装表面基本垂直地延伸；和第二头部，形成在所述第二柱部上并且具有比第二柱部大的横向尺寸；第一和第二接触焊盘，形成在所述基底的安装表面上；和连接部，用于分别把所述头部连接到各个的接触焊盘；其中，所述基部和所述柱部由同种材料柱一体地形成，所述第一柱部比所述第二柱部高。
所述互连结构可以进一步包括布置在所述堆叠结构的所述第一和第二组件之间的间隔物。
用于把所述互连结构的所述头部连接到所述接触焊盘的所述连接部可以包括由焊料、粘性接合、表面活化接合、压力接合和扩散接合组成的组中的一种或多种。
依照本发明的第四方面，本发明提供了制造互连结构的方法，所述方法包括：在第一组件的安装表面上形成基部；形成柱部，所述柱部从所述基部起与所述安装表面基本垂直地延伸；以及在所述柱部上形成头部，所述头部具有比所述柱部大的横向尺寸；以及用同种材料一体地形成所述基部和所述柱部。
所述方法可以进一步包括在光刻过程中使用不同的掩模形成所述柱部和所述头部。
形成所述柱部和所述头部的步骤可以包括压印过程。
用于所述压印过程的模具可以被构图并且可以包括聚合物、复合材料或金属材料。
所述方法可以进一步包括在所述头部和所述柱部之间形成中间层。
附图说明
通过仅为示例性的以下书面描述并且结合附图，本领域技术人员将更好地理解和明白本发明的实施方式，其中：
图1示出了典型的焊料凸点互连的示意图；
图2a和图2b示出了分别具有更大和更小柱直径的传统柱互连设计的示意图；
图3a示出了根据一个示例实施方式的微型器件芯片和基底的组装体的示意图，微型器件芯片和基底由钉-头(pin-head)互连结构和焊料凸点连接；
图3b示出带有钉-头互连结构的组装体的示意图，该钉-头互连结构具有与图3a中示出的钉-头互连结构相比更小的直径；
图4a示出图3的钉-头互连的示意图；
图4b和图4c示出图4a的钉-头互连的变体的示意图；
图4d示出图4b的钉-头互连的变体的示意图；
图4e到图4g示出具有水平部分的不同设计的钉-头互连的顶部截面图；
图5a到图5j示出根据一种示例实施方式使用光刻电镀制造钉-头互连的流程；
图6a到图6g示出来自于图5e的使用光刻电镀制造钉-头互连的流程的继续；
图7a到7g示出来自于图5e的使用光刻电镀制造钉-头互连的流程的可替换继续；
图8a到图8j示出根据一种示例实施方式使用低成本的压印电镀流程制造钉-头互连的流程；
图9a示出连接到微型器件的钉-头互连的示意图；
图9b示出连接到微型器件的平坦化的钉-头互连的示意图；
图10a到图10c示出使用包含本发明的不同互连结构互连至基底的一个微型器件的示意图；
图11a和图11b示出使用包含本发明的不同互连结构互连至基底的两个微型器件的示意图。
具体实施方式
本发明描述的实施方式提供了互连结构，以克服焊料凸点互连中的固有弱点。实施方式还提供了改进的互连结构，以克服金属互连和焊料凸点在微型设备封装或集成方面当前具有的限制。
图3a示出微型器件芯片302和基底304的组装体300的示意图，它们是由钉-头互连结构306和焊料凸点308连接的。微型器件芯片302的基材可以是(例如但是不限于)半导体材料，例如，硅、陶瓷、玻璃或聚合物材料等等。微型器件芯片302的基材可以被钝化有介电材料，被涂有金属层，被加工图案和被环绕有沟道、金属迹线和焊盘。钉-头互连306包括基本竖直的柱部310和基本水平的头部312。头部312布置在柱部310的一端。钉-头互连306的柱部310的另一端(即，与具有头部312的端相对的端)与微型器件芯片302接触。焊料凸点308被设置在头部312和基底304的金属焊盘314之间。钉-头互连306的柱部310和头部312由同种金属制成。同种金属的一个实例是铜。优选的是，焊料凸点308是无铅的。基底304可以由任何聚合物、复合材料或无机材料制成，例如聚酰亚胺、环氧树脂玻璃、陶瓷或硅等等。本领域的技术人员将理解，在其它实施方式中其它材料可以用于微型器件芯片302、钉-头互连306、焊料凸点308和基底304。
图3b示出具有钉-头互连306的柱部310的组装体300的示意图，这个柱部310具有与图3a的柱部相比更小的宽度316。通过比较图3a和3b，可以注意到，当钉-头互连306的柱部310的宽度316减小时，焊料凸点308的大小不改变。而且，组装体300有利地允许钉-头互连306的柱部310的宽高比变化，以增加组装体300的顺应性而不改变焊料凸点大小。这有利地减小了由微型器件芯片302和基底304之间热膨胀系数(CTE)失配导致的互连上的局部剪应变。即使横跨微型器件芯片302的钉-头互连306的柱部310的宽度316变化，钉-头互连306也能够有利地允许在微型器件芯片302上使用标准的焊料焊盘和焊料凸点，从而在微型器件芯片302的不同位置处提供最佳的顺应性。
图4a示出图3的钉-头互连302的示意图。钉-头互连302包括基本圆形的柱部306。钉-头互连302还包括头部308和基本水平的基部402。头部308和基部402分别设置在柱部306的各个端处。图4b示出图4a的钉-头互连302的变化的示意图。在此实施方式中，钉-头互连302具有基本矩形的竖直部306。
在图4a和图4b的实施方式中，钉-头互连302的头部308和基部402具有比柱部306大的横向尺寸。头部308和基部402具有相同的横截面形状。柱部306具有与头部308和基部402的横截面不同的横截面形状。
图4c示出图4a的钉-头互连302的一种变体的示意图。图4d示出图4b的钉-头互连302的一种变体的示意图。在图4c和图4d的实施方式中，可以认为钉-头互连302包括具有与柱部306相同的横向尺寸和横截面形状的基部402。头部308具有比柱部306和基部402大的横向尺寸。头部308具有与柱部306和基部402的横截面相比不同的横截面形状。
图4e示出具有基本圆形柱部306、基本圆形基部402和基本圆形头部308的钉-头互连302的顶部截面图。图4f和4g示出具有圆形柱部306和圆形基部402但是头部308的不同设计的钉-头互连302的顶部截面图。在图4f中，头部308包括两个半圆形元件404。半圆形元件404被分隔开，并且被布置成使各个直立边406互相面对并且从一端到另一端对齐。在图4g中，头部308基本是十字形的。在图4e、4f和4g中，柱部306基本被布置在头部308的中央。
在图4e、4f和4g的实施方式中，柱部306具有与基部402相同的横向尺寸和横截面形状。头部308具有比柱部306和基部402大的横向尺寸。头部308具有与柱部306和基部402的横截面相比不同的横截面形状。如本领域的技术人员认识到的，钉-头互连302的柱部306、头部308和基部402的设计未被限制为上面描述的实施例。
现在将描述可以用来制造钉-头互连的两种示例方法，也就是光刻电镀和压印电镀。图5a到图5j示出使用光刻电镀制造钉-头互连的流程。图5a示出沉积在硅(Si)芯片504上的、具有粘合和籽晶层502形式的安装表面的示意图。在这个实施方式中，粘合层大约是100到1000埃，籽晶层大约是1000到5000埃。钨钛(TiW)和铜(Cu)用于粘合和籽晶层502。依芯片的基材而定，在其它实施方式中，Ti和Cu或铬(Cr)和Cu也可以用于粘合和籽晶层502。第一光刻胶(PR1)层506被沉积在粘合和籽晶层502上。带有图案的掩模(没有示出)被放置在PR1层506上面。在利用穿过有图案的掩模的紫外光(UV)对PR1层506进行曝光之后，如在图5b中所示形成构图的开口508。在图5c中示出通过例如电镀的方法在开口508中沉积铜层510。在这个实施方式中，铜层510的厚度大约是1.0微米到10微米。
在图5a到图5c中示出的形成铜层510的过程与形成传统芯片焊盘的过程类似。铜芯片焊盘510形成钉-头互连的基部。这有利地允许在铜芯片焊盘上直接对钉-头互连进行电镀。这有利地使得以晶圆级集成制造钉-头互连阵列更为容易。
图5d示出在PR1层506上沉积形成有开口514的第二光刻胶(PR2)层512的示意图。开口514由传统的光刻工艺形成在PR2层512中。通过例如电镀将铜层516沉积在开口514中，如在图5e中所示。铜层516形成钉-头互连的柱部。柱部的高度直径比优选地大约是0.5到4.0。通过例如电镀将具有凸出表面的铜层518沉积在开口514中，如在图5f中所示。由于在PR2层512上方的柱部516上的各向同性铜离子沉积的原因，形成凸出的铜层518。凸出的铜层518形成钉-头互连的头部。图5g示出在电镀之后形成由Cu制成的凸出钉-头互连520。PR1层506和PR2层512被移除。图5h示出移除了粘合和籽晶层502的延伸超出铜层510的部分。图5i示出介电或钝化层522被沉积在硅芯片504上。在这个实施方式中，苯并环丁烯(BCB)可以用于介电或钝化层522。介电或钝化层522把钉-头互连520的基部和部分的柱部封装在内。图5j示出了介电或钝化层522的一部分被移除。如果在这个实施方式中使用可感光成像的层522，则封装钉-头互连520的基部和部分的柱部的介电或钝化层522可以通过使用传统的光刻过程移除。
在其它实施方式中，可能在图5i处终止制造钉-头互连的过程。移除介电或钝化层522中的一些部分的步骤可以用来生产金属焊盘限定的互连结构。
可选地，在如图5e中所示把铜层516沉积在间隙514中之后，第三光刻胶(PR3)层602可以被沉积在PR2层512上(如在图6a中所示)，或者粘合和籽晶层702可以被沉积在PR2层512上(如在图7a中所示)。
参照图6a，第三光刻胶(PR3)层602被沉积在PR2层512上，用传统的光刻过程在PR3层602中形成开口604。具有突出表面的铜层606通过例如电镀被沉积在开口604中，如在图6b中所示。由于各向同性铜离子沉积，形成了铜层606的凸出表面。PR3层602根据构图的开口604来约束和限定凸出的铜层606的形成和生长。铜层606形成钉-头互连的头部。在移除PR3层602之前，可以使用化学的、机械的或化学-机械的方法使铜层606平坦化，以产生平的钉-头。
图6c示出在平坦化之后带有平坦化的铜层606的、由Cu制成的钉-头608。图6d示出移除了PR1层506、PR2层512和PR3层602。图6e示出移除了粘合和籽晶层502的、延伸超出铜层510的部分。图6f示出在硅芯片504上沉积的介电或钝化层610。在这个实施方式中，苯并环丁烯(BCB)用于介电或钝化层610。介电或钝化层610把钉-头互连608的基部和部分的柱部封装在内。图6g示出移除了把钉-头互连608的基部和部分的柱部封装在内的介电或钝化层610的一部分。如果在这个实施方式中使用可感光成像的层610，则介电或钝化层610可以通过使用传统的光刻过程移除。
在其它实施方式中，可能在步骤6f处结束制造钉-头互连的过程。移除介电或钝化层610中的一些部分的步骤可以用来产生金属焊盘限定的互连结构。
参考图7a，粘合和籽晶层702被沉积在PR2层512上，第三光刻胶(PR3)层704被沉积在层702上。钛钨(TiW)和铜(Cu)用于粘合和籽晶层702。依芯片的基材而定，Ti和Cu或铬(Cr)和Cu也可以用于其它实施方式中的粘合和籽晶层702。开口706用传统的光刻工艺形成在PR3层704中，如在图7b中所示。具有基本平坦表面的铜层708被沉积在开口706中，如在图7c中所示。图7d示出移除了PR1层506、PR2层512和PR3层704。移除了粘合和籽晶层702中的延伸超出铜层708的部分。粘合和籽晶层702和铜层708形成钉-头互连的头部710。图7e示出移除了粘合和籽晶层502中的延伸超出铜层510的部分。形成了由Cu制成的钉-头互连712。图7f示出在硅芯片504上沉积的介电或钝化层714。在这个实施方式中，苯并环丁烯(BCB)用于介电或钝化层714。介电或钝化层714把钉-头互连712的基部和部分的柱部封装在内。图7g示出了移除把钉-头互连712的基部和部分的柱部封装在内的、介电或钝化层714的一部分。如果在这个实施方式中使用可感光成像层714，则介电或钝化层714可以通过使用传统的光刻过程移除。
在其它实施方式中，可能在图7f处终止制造钉-头互连的过程。移除介电或钝化层714中的一些部分的步骤可以用来产生金属焊盘限定的互连结构。
图8a到图8j示出使用低成本的压印电镀过程制造钉-头互连的流程。图8a示出具有在硅(Si)芯片804上沉积的粘合和籽晶层802形式的安装表面的示意图。钛钨(TiW)和铜(Cu)用于粘合和籽晶层802。依芯片的基材而定，在其它实施方式中，Ti和Cu或铬(Cr)和Cu也可以用于粘合和籽晶层802。第一光刻胶(PR1)层806被沉积在粘合和籽晶层804上。用传统的光刻工艺在PR1层806中形成开口808，如在图8b中所示。可替换地，PR1层806可以是非光敏聚合物抗蚀剂，用有图案的模具和等离子体灰化对其进行压印来产生开口808。铜层810通过例如电镀被沉积在开口808中，如图8c所示。
在图8a到8c中示出的形成铜层810的过程与形成传统的芯片焊盘的过程类似。铜芯片焊盘810形成钉-头互连的基部。这有利地允许在铜芯片焊盘上直接对钉-头互连进行电镀。这有利地使得以晶圆级集成制造钉-头互连阵列更为容易。
图8d示出在PR1层806上沉积的第二聚合物光刻胶(PR2)层812的示意图。压印模具814用来形成在PR2层812中的腔816，如在图8e中所示。在这个实施方式中压印模具814由镍制成。在不同的实施方式中可以使用其它聚合物、复合材料或金属材料来制造模具814。在腔816的底部处的PR2层812的残留可以通过等离子体灰化以及接下来的湿法化学清洗移除。模具压印过程使得能够在厚的聚合物抗蚀剂上形成高深宽比的开口。如在图8e中所示，在一个压印步骤中可以形成具有复杂几何形状的腔。如在图8f中所示，通过例如电镀把铜沉积到腔816内，铜层818具有凸起的钉-头表面。由于各向同性的铜离子沉积，可形成铜层818的凸出表面。在这个实施方式中，铜层818形成钉-头互连的柱部和头部。在其它实施方式中，在移除PR2层812之前可以使用化学的、机械的或化学-机械的平坦化过程对凸出的钉-头进行平坦化。
图8g示出形成由Cu制成的钉-头互连820。移除了PR1层806和PR2层812。图8h示出移除了粘合和籽晶层802的延伸超出铜层810的部分。图8i示出在硅芯片804上沉积介电或钝化层822。在这个实施方式中，苯并环丁烯(BCB)用于介电或钝化层822。介电或钝化层822把钉-头互连820的基部和部分的柱部封装在内。图8j示出移除了把钉-头互连820的基部和部分的柱部封装在内的介电或钝化层822的一部分。如果在这个实施方式中使用可感光成像的层822，则介电或钝化层822可以通过使用传统的光刻过程移除。
在其它实施方式中，可能在图8i处终止制造钉-头互连的过程。移除介电或钝化层822中的一些部分的步骤可以用来产生金属焊盘限定的互连结构。
在上面描述的光刻电镀和压印电镀过程中，形成钉-头互连可以被视为形成改进的芯片互连结构。此外，互连结构的包括基部、柱部和头部的部分可以被均匀地或选择性地处理或涂敷，以提高它们的抗湿、抗扩散和抗氧化特性。例如，镍一般用作扩散阻挡层，金用作抗氧化层。这些金属可以通过溅射或电镀过程沉积在互连结构上。可以在晶圆级有利地制造钉-头互连结构。微型器件可以被组装在带有或不带有倒装封装的基底上。
此外，铜用来形成上面描述的钉-头互连的基部和柱部。在其它实施方式中，镍或金可以用来形成基部和柱部。在这种实施方式中，粘合和籽晶层可以包括镍或金。
在以上描述的光刻电镀和压印电镀过程中，钉-头互连首先形成在硅芯片上，然后使基底与钉-头互连接触。在其它实施方式中，钉-头互连首先形成在基底上，然后使硅芯片与钉-头互连接触。
图9a示出连接到微型器件904的钉-头互连902的示意图。微型器件904可以是具有电子、光学、流体或微机电功能或者这些功能的组合的任何器件。钉-头互连902包括基部906、柱部908和头部910。基部906和头部910分别布置在柱部908的各个端。微型器件904的钝化层914可以是可感光成像的或非感光成像的材料。
在这个实施方式中，基部906和头部910具有比柱部906大的横向尺寸。头部910具有比基部906大的横向尺寸。基部906、柱部908和头部910具有不同的横截面积。基部906的表面基本是平面的，头部910具有弯曲的表面。
图9b示出连接到微型器件904的图9a的钉-头互连902的另一实施例的示意图。钉-头互连902的头部912具有基本平坦的表面。
图10a、10b和10c示出互连到基底10的一个微型器件904的示意图。在图10a中，图9b的钉-头互连902使用例如焊料、粘合接合、间接接合或直接接合的方法连接到基底1004的金属焊盘1002。在图10b中，利用焊料凸点1006将图9b的钉-头互连902连接到基底1004的金属焊盘1002。在把钉-头互连902和基底1004接在一起之前，可以在钉-头互连902或者金属焊盘1002上预先形成焊料凸点1006。在图10c中，图9b的钉-头互连902通过焊料1008或像粘合接合、表面活化接合、压力接合或扩散接合的其它连接方法连接到基底1004的嵌入的金属焊盘1002。嵌入的金属焊盘1002形成在基底1012的腔内。钉-头互连902的头部912完全由焊料1008封装在内。可替换地，钉-头互连902的水平部912可以部分地由焊料1008封装在内。
钉-头互连可以用于连接、互连或支撑微型器件904，以便于封装和集成。图11a和图11b示出了互连到基底1004的两个微型器件904的示意图。在图11a中，使用例如焊料、粘合接合、表面活化接合、压力接合或扩散接合的方法，将钉-头互连902连接到基底1004的金属焊盘1002。在图11b中，利用焊料凸点1006，将钉-头互连902连接到基底1004的金属焊盘1002。间隔物1102在本实施方式中被布置在微型器件904之间。在其它实施方式中，多于两个微型器件904可以互连到基底1004。
使用在示例实施方式中的钉-头互连设计，可以有利地直接在用Cu金属化后的芯片焊盘上对铜钉-头互连进行电镀。因此，在芯片焊盘上不再需要UBM。因为仅在芯片侧上存在薄膜材料和有源器件相互作用的问题，所以在基底侧上设计和优化互连可靠性的复杂度较低。
高电流外加上需要减小封装尺寸导致在封装内产生高热量。在同一芯片上对于特定位置设计和构造Cu互连的能力可以有利地显著提高热性能。随着芯片大小变得更小和更密集，高温和电流密度促进电迁移这一问题受到了日益增加的关注。因为Cu的熔点是1083℃，其与大多数含铅的或无铅的焊接材料的熔点比高得多，所以Cu钉-头互连的原子扩散有利地比大多数的焊接材料慢得多。因此，在Cu钉-头互连中有利地降低了电迁移。
本领域的技术人员将理解，在没有背离概括地描述的本发明的精神或范围的条件下，可以如在特定实施方式中示出的那样对本发明进行多种改变和/或修改。因此，现有的实施方式在各个方面应被认为是说明性的而不是限制性的。
例如，可以理解的是，在不同实施方式中，柱结构的基部形成在基底的表面上，用于把柱头连接到芯片。更一般地，在不同实施方式中，互连结构可以被应用在待互相连接的两个组件或元件的安装表面之间，或者在多组件堆叠结构和基底之间。
此外，在不同实施方式中，用于互连结构的同种材料可以包括任何金属或适合于电镀的任何导电材料。
此外，在其它实施方式中，互连结构可以形成在为了形成互连结构而经受电镀的任何表面上。同样，如果将在不能经受电镀的表面上形成互连结构，可以沉积籽晶电镀层。如果籽晶层不能直接粘接到表面的基材上，可能需要附加的粘接层。
在多个实施方式中，可以由像镍或金的其它电镀金属制造互连结构。如果使用硅基底、玻璃基底或陶瓷基底，则粘合层可以是TiW、Ti或Cr，用于电镀的籽晶层可以是镍或金。对于像环氧玻璃纤维的其它材料，籽晶或电镀层可以被层压在基材上。

Claims (32)

1.一种互连结构，包括：
基部，形成在第一组件的安装表面上；
柱部，从所述基部起与所述安装表面基本垂直地延伸；和
头部，形成在所述柱部上并且具有比所述柱部大的横向尺寸；
其中，所述基部和所述柱部由同种材料一体地形成。
2.根据权利要求1所述的互连结构，其中，
所述基部具有比所述柱部大的横向尺寸。
3.根据权利要求1或权利要求2所述的互连结构，其中，
所述基部、所述柱部和所述头部由同种材料一体地形成。
4.根据权利要求1或权利要求2所述的互连结构，进一步包括：
在所述头部和所述柱部之间形成的中间层，所述中间层包括与所述同种材料不同的材料。
5.根据权利要求4所述的互连结构，其中，
所述中间层包括TiW和Cu、Ti和Cu、或者Cr和Cu。
6.根据权利要求1到权利要求5中任何一项所述的互连结构，其中，
所述基部形成在接触层上，所述接触层形成在所述第一组件的所述安装表面上。
7.根据权利要求6所述的互连结构，其中，
所述接触层包括TiW和Cu、Ti和Cu、或者Cr和Cu。
8.根据权利要求1到权利要求7中任何一项所述的互连结构，其中，
所述同种材料包括金属或适合于电镀的导电材料。
9.根据权利要求8所述的互连结构，其中，
所述金属包括由Cu、Ni和Au组成的组中的一种或多种。
10.根据权利要求1到权利要求9中任何一项所述的互连结构，其中，
所述柱部和所述头部具有相同的横截面形状。
11.根据权利要求1到权利要求9中任何一项所述的互连结构，其中，
所述柱部和所述头部具有不同的横截面形状。
12.根据权利要求1到权利要求11中任何一项所述的互连结构，其中，
所述柱部和所述基部具有相同的横截面形状。
13.根据权利要求1到权利要求11中任何一项所述的互连结构，其中，
所述柱部和所述基部具有不同的横截面形状。
14.根据权利要求1到权利要求13中任何一项所述的互连结构，其中，
所述头部和所述基部具有相同的横截面形状。
15.根据权利要求1到权利要求13中任何一项所述的互连结构，其中，
所述头部和所述基部具有不同的横截面形状。
16.根据权利要求1到权利要求15中任何一项所述的互连结构，其中，
所述头部具有表面，所述表面被设置为面向所述第一组件将被安装到的第二组件。
17.根据权利要求16所述的互连结构，其中，
所述表面是凸出的。
18.根据权利要求16所述的互连结构，其中，
所述表面是平坦的。
19.根据权利要求1到权利要求18中任何一项所述的互连结构，其中，
介电或钝化层被沉积在所述第一组件上，使得所述柱部和所述基部或者被封装在内或者保持暴露。
20.根据权利要求1到权利要求19中任何一项所述的互连结构，其中，
所述基部、所述柱部和所述头部至少其中之一均匀地涂有或者选择性地涂有从由润湿层、扩散阻挡层和抗氧化层组成的组中选择的一个或多个。
21.用于将第一和第二组件互连的互连结构，所述互连结构包括：
基部，形成在所述第一组件的安装表面上；
柱部，从所述基部起与所述安装表面基本垂直地延伸；和
头部，形成在所述柱部上并且具有比所述柱部大的横向尺寸；
接触焊盘，形成在所述第二组件的安装表面上；和
连接部，用于把所述互连结构的所述头部连接到所述接触焊盘；
其中，所述基部和所述柱部由同种材料一体地形成。
22.根据权利要求21所述的互连结构，其中，
用于把所述互连结构的所述头部连接到所述接触焊盘的所述连接部包括由焊料、粘合接合、表面活化接合、压力接合和扩散接合组成的组中的一种或多种。
23.根据权利要求21所述的互连结构，其中，
焊料凸点分别形成在所述头部和所述接触焊盘的面对表面之间。
24.根据权利要求21所述的互连结构，其中，
所述头部和所述接触焊盘基本由焊料封装。
25.一种用于将多组件堆叠结构和基底互连的互连结构，所述互连结构包括：
第一基部，形成在所述堆叠结构的第一组件的第一安装表面上；
第一柱部，从所述第一基部起与所述第一安装表面基本垂直地延伸；和
第二头部，形成在所述第二柱部上并且具有比所述第二柱部大的横向尺寸；
第二基部，形成在所述堆叠结构的第二组件的第二安装表面上；
第二柱部，从所述第二基部起与所述第二安装表面基本垂直地延伸；和
第二头部，形成在所述第二柱部上并且具有比所述第二柱部大的横向尺寸；
第一和第二接触焊盘，形成在所述基底的安装表面上；和
连接部，用于分别把所述头部连接到各个所述接触焊盘；
其中，所述基部和所述柱部由同种材料柱一体地形成，所述第一柱部比所述第二柱部高。
26.根据权利要求25所述的互连结构，进一步包括：
间隔物，布置在所述堆叠结构的所述第一和第二组件之间。
27.根据权利要求25所述的互连结构，其中，
用于把所述互连结构的所述头部连接到所述接触焊盘的所述连接部包括由焊料、粘合接合、表面活化接合、压力接合和扩散接合组成的组中的一种或多种。
28.一种制造互连结构的方法，所述方法包括：
在第一组件的安装表面上形成基部；
形成柱部，所述柱部从所述基部起与所述安装表面基本垂直地延伸；以及
在所述柱部上形成头部，所述头部具有比所述柱部大的横向尺寸；以及
用同种材料一体地形成所述基部和所述柱部。
29.根据权利要求28所述的方法，进一步包括：
在光刻过程中使用不同掩模形成所述柱部和所述头部。
30.根据权利要求28所述的方法，其中，
形成所述柱部和所述头部的步骤包括压印过程。
31.根据权利要求30所述的方法，其中，
用于所述压印过程的模具被构图并且包括聚合物、复合材料或金属材料。
32.根据权利要求28到31中任何一项所述的方法，进一步包括：
在所述头部和所述柱部之间形成中间层。
CN200880120776XA 2007-11-06 2008-10-21 互连结构及其制造方法 Expired - Fee Related CN101897013B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SG200717535-9A SG152101A1 (en) 2007-11-06 2007-11-06 An interconnect structure and a method of fabricating the same
SG200717535-9 2007-11-06
PCT/SG2008/000406 WO2009061282A1 (en) 2007-11-06 2008-10-21 An interconnect structure and a method of fabricating the same

Publications (2)

Publication Number Publication Date
CN101897013A true CN101897013A (zh) 2010-11-24
CN101897013B CN101897013B (zh) 2012-05-23

Family

ID=40626013

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880120776XA Expired - Fee Related CN101897013B (zh) 2007-11-06 2008-10-21 互连结构及其制造方法

Country Status (4)

Country Link
US (1) US8462516B2 (zh)
CN (1) CN101897013B (zh)
SG (1) SG152101A1 (zh)
WO (1) WO2009061282A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570871B (zh) * 2011-10-17 2017-02-11 史達晶片有限公司 半導體裝置以及形成具有擴大基底之傳導柱的方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110122592A1 (en) * 2009-11-24 2011-05-26 Sanka Ganesan First-level interconnects with slender columns, and processes of forming same
US8296940B2 (en) 2010-04-19 2012-10-30 General Electric Company Method of forming a micro pin hybrid interconnect array
US20110291153A1 (en) * 2010-05-31 2011-12-01 Yang ming-kun Chip submount, chip package, and fabrication method thereof
CN103229609B (zh) * 2010-09-28 2016-12-21 乔治亚技术研究公司 第二级互连结构及其制造方法
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
US10833033B2 (en) 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
TWI467718B (zh) * 2011-12-30 2015-01-01 Ind Tech Res Inst 凸塊結構以及電子封裝接點結構及其製造方法
US9564398B2 (en) * 2013-03-12 2017-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chemical direct pattern plating interconnect metallization and metal structure produced by the same
TWI501362B (zh) * 2013-08-16 2015-09-21 Powertech Technology Inc 多形體銅柱凸塊接合結構及其凸塊形成方法
US9418953B2 (en) * 2014-01-13 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging through pre-formed metal pins
US20150276945A1 (en) 2014-03-25 2015-10-01 Oy Ajat Ltd. Semiconductor bump-bonded x-ray imaging device
US10340206B2 (en) * 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
US10636758B2 (en) * 2017-10-05 2020-04-28 Texas Instruments Incorporated Expanded head pillar for bump bonds
US11276659B2 (en) * 2020-02-28 2022-03-15 Micron Technology, Inc. Methods for forming elements for microelectronic components, related conductive elements, and microelectronic components, assemblies and electronic systems incorporating such conductive elements
US20230068329A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
CN115295712B (zh) * 2022-10-08 2023-02-03 合肥本源量子计算科技有限责任公司 一种互连单元、芯片结构、倒装芯片及其对准方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2573016B2 (ja) * 1988-02-27 1997-01-16 アンプ インコーポレーテッド マイクロ入出力ピンおよびその製造方法
US5130779A (en) 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
KR920022482A (ko) * 1991-05-09 1992-12-19 가나이 쯔도무 전자부품 탑재모듈
US5334804A (en) 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
DE19524739A1 (de) 1994-11-17 1996-05-23 Fraunhofer Ges Forschung Kernmetall-Lothöcker für die Flip-Chip-Technik
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
US5773897A (en) * 1997-02-21 1998-06-30 Raytheon Company Flip chip monolithic microwave integrated circuit with mushroom-shaped, solder-capped, plated metal bumps
US5926731A (en) 1997-07-02 1999-07-20 Delco Electronics Corp. Method for controlling solder bump shape and stand-off height
US6110760A (en) * 1998-02-12 2000-08-29 Micron Technology, Inc. Methods of forming electrically conductive interconnections and electrically interconnected substrates
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
EP0971403A1 (en) * 1998-07-07 2000-01-12 Interuniversitair Microelektronica Centrum Vzw Method for forming copper-containing metal studs
JP2943805B1 (ja) * 1998-09-17 1999-08-30 日本電気株式会社 半導体装置及びその製造方法
JP3502776B2 (ja) 1998-11-26 2004-03-02 新光電気工業株式会社 バンプ付き金属箔及び回路基板及びこれを用いた半導体装置
US6300250B1 (en) 1999-08-09 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of forming bumps for flip chip applications
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6884707B1 (en) * 2000-09-08 2005-04-26 Gabe Cherian Interconnections
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7242099B2 (en) 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20060163729A1 (en) 2001-04-18 2006-07-27 Mou-Shiung Lin Structure and manufacturing method of a chip scale package
KR20040111395A (ko) 2002-03-12 2004-12-31 페어차일드 세미컨덕터 코포레이션 웨이퍼 레벨의 코팅된 구리 스터드 범프
US7135777B2 (en) * 2002-05-03 2006-11-14 Georgia Tech Research Corporation Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof
US7087458B2 (en) 2002-10-30 2006-08-08 Advanpack Solutions Pte. Ltd. Method for fabricating a flip chip package with pillar bump and no flow underfill
TW200423344A (en) 2002-12-31 2004-11-01 Texas Instruments Inc Composite metal column for mounting semiconductor device
TWI221335B (en) 2003-07-23 2004-09-21 Advanced Semiconductor Eng IC chip with improved pillar bumps
TWI254995B (en) * 2004-01-30 2006-05-11 Phoenix Prec Technology Corp Presolder structure formed on semiconductor package substrate and method for fabricating the same
JP4119866B2 (ja) * 2004-05-12 2008-07-16 富士通株式会社 半導体装置
TWI259572B (en) * 2004-09-07 2006-08-01 Siliconware Precision Industries Co Ltd Bump structure of semiconductor package and fabrication method thereof
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US20060223313A1 (en) * 2005-04-01 2006-10-05 Agency For Science, Technology And Research Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
TWI294677B (en) * 2006-03-31 2008-03-11 Ind Tech Res Inst Interconnect structure with stress buffering ability and the manufacturing method thereof
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
US7465089B2 (en) * 2007-01-04 2008-12-16 Battle Ronald K Protective coverings for radiological equipment
US20090108443A1 (en) * 2007-10-30 2009-04-30 Monolithic Power Systems, Inc. Flip-Chip Interconnect Structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570871B (zh) * 2011-10-17 2017-02-11 史達晶片有限公司 半導體裝置以及形成具有擴大基底之傳導柱的方法
US9824923B2 (en) 2011-10-17 2017-11-21 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming conductive pillar having an expanded base

Also Published As

Publication number Publication date
CN101897013B (zh) 2012-05-23
SG152101A1 (en) 2009-05-29
WO2009061282A1 (en) 2009-05-14
US20100246150A1 (en) 2010-09-30
US8462516B2 (en) 2013-06-11

Similar Documents

Publication Publication Date Title
CN101897013B (zh) 互连结构及其制造方法
US6756671B2 (en) Microelectronic device with a redistribution layer having a step shaped portion and method of making the same
CN207338349U (zh) 半导体装置
US7015590B2 (en) Reinforced solder bump structure and method for forming a reinforced solder bump
CN101728347B (zh) 封装结构及其制造方法
US6590295B1 (en) Microelectronic device with a spacer redistribution layer via and method of making the same
KR101266335B1 (ko) 플립 칩 장치를 제조하기 위한 구조 및 방법
US6564449B1 (en) Method of making wire connection in semiconductor device
US20070028445A1 (en) Fluxless bumping process
KR20080027161A (ko) 퓨즈형 ｉ／ｏ 상호연결 시스템 및 기판 장착 스터드범프를포함하는 플립칩 패키징 방법
US20060022320A1 (en) Semiconductor device and manufacturing method thereof
US6534874B1 (en) Semiconductor device and method of producing the same
US6933171B2 (en) Large bumps for optical flip chips
US10020263B2 (en) Semiconductor package and manufacturing method thereof
US9035455B2 (en) Semiconductor device
US20030129821A1 (en) Bump fabrication method
CN111293112B (zh) 半导体封装和其制造方法
CN114586145A (zh) 凸起结构的形成
CN101194361A (zh) 层序列及制造层序列的方法
TW201705366A (zh) 半導體裝置及製造其之方法
KR20180054397A (ko) 반도체 디바이스 및 그의 제조 방법
US8476760B2 (en) Electroplated posts with reduced topography and stress
US6884661B1 (en) Method of fabricating posts over integrated heat sink metallization to enable flip chip packaging of GaAs devices
US6646357B2 (en) Semiconductor device and method of production of same
US11973051B2 (en) Molded direct contact interconnect structure without capture pads and method for the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120523

Termination date: 20131021