TWI768851B - 半導體元件與其形成方法 - Google Patents

半導體元件與其形成方法 Download PDF

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TWI768851B
TWI768851B TW110115204A TW110115204A TWI768851B TW I768851 B TWI768851 B TW I768851B TW 110115204 A TW110115204 A TW 110115204A TW 110115204 A TW110115204 A TW 110115204A TW I768851 B TWI768851 B TW I768851B
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TW202217973A (zh
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邱詩航
吳仲強
洪若珺
王唯誠
劉冠廷
志安 徐
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台灣積體電路製造股份有限公司
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Abstract

揭露具有改善閘極電極結構之半導體元件及其形成方法。在實施例中,半導體元件包含在半導體基材之上之閘極結構,閘極結構包含高k值介電層;在高k值介電層上之n型功函數層;在n型功函數層上之抗反應層,抗反應層包含介電材料;在抗反應層之上之p型功函數層,p型功函數層覆蓋抗反應層的頂部表面;及在p型功函數層之上之導電覆蓋件層。

Description

半導體元件與其形成方法
本揭露是關於一種半導體元件與其形成方法。
半導體元件被使用於各種類的電子應用中,諸如,舉例而言,個人電腦、手機、數位相機、及其他電子設備。半導體元件通常藉由以下方式所產製:依序地在半導體基材之上沉積絕緣或介電層、導電層、及半導體層、及半導體材料層,並使用微影製程圖案化各種材料層以在其上形成電路組件及元素。
半導體產業藉由不斷減小最小特徵大小以不斷改善各種電子組件(例如,電晶體、二極管、電阻器、電容器等)的積體密度,此舉允許將更多的組件整合至給定的區域之中。
根據本揭露的實施例,半導體元件包含在半導體基 材之上之閘極結構,閘極結構包含高k值介電層;在高k值介電層上之n型功函數層;在n型功函數層上之抗反應層,抗反應層包含介電材料;在抗反應層之上之p型功函數層,p型功函數層覆蓋抗反應層的頂部表面;及在p型功函數層之上之導電覆蓋件層。
根據本揭露的另一些實施例,半導體元件包含在n型區的第一通道區;在p型區中之第二通道區;在第一通道區之上之第一閘極堆疊,第一閘極堆疊在第一通道區之上包含第一閘極介電層;在第一閘極介電層之上並與之接觸之n型金屬層,此n型金屬層包含鋁;在n型金屬層之上之介電層;在n型金屬層及介電層之上之第一p型金屬層;在第一p型金屬層之上之第一金屬覆蓋件層;在第二通道區之上之第二閘極堆疊,第二閘極堆疊在第二通道區之上包含第二閘極介電層;在第二閘極介電層之上並與第二閘極介電層接觸之第二p型金屬層;在第二p型金屬層之上之第二金屬覆蓋件層。
根據本揭露的另一些實施例,一種半導體元件的形成方法包含在半導體基材之上形成閘極堆疊,形成此閘極堆疊包含在半導體基材之上沉積n型功函數層;在n型功函數層之上沉積介電層;在介電層之上方形成第一遮罩層;回蝕n型功函數層及介電層;在n型功函數層及介電層之上沉積p型功函數層;及在p型功函數層之上選擇性地沉積金屬覆蓋件層。
A-A'~C-C':橫截面
20:分隔件
50:基材
50N:n型區
50P:p型區
51,51A,51B,51C:第一半導體層
52,52A,52B,52C:第一奈米結構
53,53A,53B,53C:第二半導體層
54,54A,54B,54C:第二奈米結構
55:奈米結構
64:多層堆疊
66:鰭狀結構
68:隔離區/STI區
70:虛設介電層
71:虛設閘極介電質
72:虛設閘極層
74:遮罩層
76:虛設閘極
78:遮罩
80:第一間隔件層
81:第一間隔件
82:第二間隔件層
83:第二間隔件
87:第一凹陷
88:側壁凹陷
90:第一內部間隔件
92:磊晶源極/汲極區
92A:第一半導體材料層
92B:第二半導體材料層
92C:第三半導體材料層
94:接觸蝕刻停止層/CESL
96:第一層間介電質/第一ILD
97:保護層
98:第二凹陷
100:閘極介電層
101:閘極介電層
102:第一導電材料
103:閘極電極
104:抗反應層
106:第一遮罩層
108:第二導電材料
110:第三凹陷
112:導電覆蓋件材料
114:第二層間介電質/第二ILD
116:第四凹陷
118:矽化物區
120:源極/汲極觸點
122:閘極觸點
A-A’,B-B’,C-C’:橫截面
D1,D2:距離
H1:高度
T1:高度
當與隨附圖式一起閱讀時,可由後文實施方式最佳地理解本揭露內容的態樣。注意到根據此產業中之標準實務,各種特徵並未按比例繪製。實際上,為論述的清楚性,可任意增加或減少各種特徵的尺寸。
第1圖為根據一些實施例,以三維視圖例示之奈米結構場效電晶體(奈米FET)的範例。
第2、3、4、5、6A、6B、6C、7A、7B、7C、8A、8B、8C、9A、9B、9C、10A、10B、11A、11B、11C、12A、12B、12C、12D、12E、13A、13B、14A、14B、15A、15B、16A、16B、17A、17B、18A、18B、19A、19B、20A、20B、20C、20D、21A、21B、21C、21D、22A、22B、22C、22D、22E、23A、23B、23C、23D、23E、23F、23G、23H、24A、24B、25A、25B、26A及26B圖為根據一些實施例,在奈米FET的製造中之中間階段的截面視圖。
後文揭露內容提供用於實行本揭露的不同特徵之許多不同實施例、或範例。後文描述組件及佈置之特定範例以簡化本揭露內容。當然,此等僅為範例且未意圖具限制性。舉例而言,在後文的描述中,在第二特徵之上或上之第一特徵的形成可包含以直接接觸方式形成第一特徵及第二特徵的實施例,且亦可包含在第一特徵與第二特徵間 形成額外特徵,使得第一特徵及第二特徵可不直接接觸之實施例。此外,在各種範例中,本揭露內容可能重複元件符號及/或字母。此重複係出於簡單及清楚的目的,且重複本身並不規範所論述的各種實施例及/或配置間之關係。
進一步地,為便於描述,本文中可使用諸如「在...之下」、「在...下方」、「較低」、「在...上方」、「較高」、及類似者的空間相對術語,以描述圖式中所例示之一個元件或特徵與另一元件(等)或特徵(等)的關係。除圖式中所描繪之定向之外,空間相對術語亦意圖涵蓋元件在使用或操作中之不同定向。設備能以其他方式定向(旋轉90度或以其他定向),且本文中使用之空間相對描述語可同樣以相應的方式解釋。
各種實施例提供用於形成用於半導體元件之改善的閘極電極之方法及藉由所述方法所形成之半導體元件。方法包含去除犧牲閘極堆疊層以形成開口,在開口中沉積閘極介電層,在閘極介電層之上沉積n型功函數層,並在n型功函數層之上沉積抗反應層(anti-reaction layer)。在抗反應層之上沉積諸如底部抗反射塗層(bottom anti-reflective coating;BARC)材料之光抗蝕劑材料,回蝕光抗蝕劑材料,並將光抗蝕劑材料用作遮罩以回蝕抗反應層及n型功函數層。去除BARC材料,並在n型功函數層、抗反應層、及閘極介電層之上沉積p型功函數層。回蝕p型功函數層,並在p型功函數層之上選擇性地沉積金屬覆蓋件層。抗反應層可被包含在n型閘極電極中 以提供閾值電壓(Vt)提升。抗反應層可阻礙金屬覆蓋件層的選擇性沉積。在抗反應層之上沉積p型功函數層,以允許在p型功函數層上選擇性地沉積金屬覆蓋件層。包含金屬覆蓋件層以減少閘極電阻。包含抗反應層及金屬覆蓋件層改善元件性能。
本文中所論述之一些實施例以包含奈米FET之裸晶的背景所描述。然而,可將各種實施例應用於包含其他類型的電晶體(例如,鰭狀結構場效電晶體(FinFET)、平面電晶體、或類似者)之裸晶,以取代奈米FET或與奈米FET組合。
第1圖為根據一些實施例,以三維視圖例示之奈米FET(例如,奈米線材FET、奈米片材FET、或類似者)的範例。奈米FET包括在基材50(例如,半導體基材)上之鰭狀結構66之上之奈米結構55(例如,奈米片材、奈米線材、或類似者),其中奈米結構55充當奈米FET之通道區。奈米結構55可包含p型奈米結構、n型奈米結構、或其等的組合。淺溝槽將隔離(shallow trench isolation;STI)區68設置於毗鄰鰭狀結構66間,此等鰭形結構可突出至相鄰的STI區68上方並從相鄰的隔離區間突出。儘管將隔離區68描述/例示為與基材50分離,但如本文所使用,術語「基材」可指代單獨的半導體基材或半導體基材及隔離區的組合。額外地,儘管將鰭狀結構66的底部部分例示為具有基材50之單一、連續材料,鰭狀結構66及/或基材50的底部部分可包括單一材料或複數種材料。在 此背景中,鰭狀結構66指代在相鄰STI區68間延伸之部分。
閘極介電層101沿著鰭狀結構66的頂部表面及側表面,並沿著奈米結構55的頂部表面、側表面、及底部表面延伸。閘極電極103在閘極介電層101之上。將磊晶源極/汲極區92設置於閘極介電層101及閘極電極103的相對側上之鰭狀結構66上。
第1圖進一步例示在後文圖式中所使用之參考橫截面。橫截面A-A'沿著閘極電極103的縱軸並在,舉例而言,垂直於奈米FET的磊晶源極/汲極區92間之電流方向之方向上。橫截面C-C'與橫截面A-A'平行,並延伸通過多個奈米FET的磊晶源極/汲極區92。橫截面B-B'垂直於橫截面A-A',且平行於奈米FET的鰭狀結構66的縱軸並在,舉例而言,奈米FET的磊晶源極/汲極區92間流動之電流方向上。為清楚起見,後續圖式指代此等參考橫截面。
在使用閘極最終(gate last)製程所形成之奈米FET的背景中,論述本文中之一些實施例。在其他實施例中,可使用閘極最初製程。再者,一些實施例考量在平面元件,諸如平面FET或鰭狀結構場效電晶體(FinFET)中,所使用之態樣。
第2至26B圖為根據一些實施例,奈米FET的製造中之中間階段的截面視圖。第2至5、6A、7A、8A、9A、10A、11A、12A、13A、14A、15A、16A、17A、 18A、19A、20A、20C、21A、21C、22A、22C、23A、23C、24A、25A、及26A圖例示第1圖中所例示之參考橫截面A-A'。第6B、7B、8B、9B、10B、11B、11C、12B、12E、13B、14B、15B、16B、17B、18B、19B、20B、20D、21B、21D、22B、22D、22E、23B、23D、23E、23F、23G、23H、24B、25B、及26B圖例示如第1圖中所例示之參考橫截面B-B'。第6C、7C、8C、9C、12C、及12D圖例示如第1圖中所例示之參考橫截面C-C'。
在第2圖中,提供基材50。基材50可為半導體基材,諸如塊狀半導體、絕緣體上半導體(SOI)、或類似者,此半導體基材可被(例如,採用p型或n型摻雜劑)摻雜或無摻雜。基材50可為晶圓,諸如矽晶圓。通常而言,SOI基材為在絕緣體層上所形成之半導體材料的層。絕緣體層可為,舉例而言,埋入的氧化物(BOX)層、氧化矽層、或類似者。將絕緣體層提供至(通常為矽或玻璃基材之)基材上。亦可使用其他基材,諸如多層或梯度基材。在一些實施例中,基材50的半導體材料可包含矽;鍺;包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦之複合半導體;包含矽鍺、磷化砷化鎵、鋁砷化銦、鋁砷化鎵、鎵砷化銦、鎵磷化銦、及/或鎵磷化砷化銦之合金半導體;或其等的組合。
基材50具有n型區50N及p型區50P。n型區50N可用於形成n型元件,諸如NMOS電晶體,例如,N 型奈米FET,而p型區50P可用於形成p型元件,諸如PMOS電晶體,例如,p型奈米FET。n型區50N可與p型區50P實體地分離(如藉由所例示之分隔件20),且可將任意數量的元件特徵(例如,其他有源元件、摻雜區、隔離結構,等)設置於n型區50N與p型區50P間。儘管例示一個n型區50N及一個p型區50P,可提供任意數量的n型區50N及p型區50P。
進一步在第2圖中,在基材50之上形成多層堆疊64。多層堆疊64包含第一半導體層51A至C(統稱作第一半導體層51)及第二半導體層53A至C(統稱作第二半導體層53)的交替層。為了例示的目的,並在後文所更詳細地論述,將去除第一半導體層51,且將圖案化第二半導體層53以在n型區50N及p型區50P中形成奈米FET的通道區。然而,在一些實施例中,可去除第一半導體層51並可圖案化第二半導體層53,以在n型區50N中形成奈米FET的通道區,且可去除第二半導體層53並可圖案化第一半導體層51,以在p型區50P中形成奈米FET的通道區。然而,在一些實施例中,可去除第一半導體層51並可圖案化第二半導體層53,以在n型區50N中形成奈米FET的通道區,且可去除第二半導體層53並可圖案化第一半導體層51,以在p型區50P中形成奈米FET的通道區。在一些實施例中,可去除第二半導體層53並可圖案化第一半導體層51,以在n型區50N及p型區50P二者中形成奈米FET的通道區。
用於例示性目的,將多層堆疊64例示為各包含三層第一半導體層51及第二半導體層53。在一些實施例中,多層堆疊64可包含任意數量的第一半導體層51及第二半導體層53。多層堆疊64的每個層皆可使用諸如化學氣相沉積(chemical vapor deposition;CVD)、原子層沉積(atomic layer deposition;ALD)、氣相磊晶術(vapor phase epitaxy;VPE)、分子束磊晶術(molecular beam epitaxy;MBE)、或類似者之製程,所磊晶地成長。在各種實施例中,可由第一半導體材料,諸如矽鍺或類似者,形成第一半導體層51,且可由第二半導體材料,諸如矽、矽碳、或類似者,形成第二半導體層53。用於例示性目的,將多層堆疊64例示為具有由第一半導體材料形成的最底部的半導體層。在一些實施例中,可形成多層堆疊64,使得最底部的層由第二半導體材料所形成。
第一半導體材料及第二半導體材料可為對彼此具有高蝕刻選擇性之材料。這樣,可在不顯著去除第二半導體材料的第二半導體層53的情況下,去除第一半導體材料的第一半導體層51,從而允許待圖案化之第二半導體層53形成奈米FET的通道區。類似地,在去除第二半導體層53並圖案化第一半導體層51以形成通道區的實施例中,可在不顯著去除第一半導體材料的第一半導體層51的情況下去除第二半導體材料的第二半導體層53,從而允許待圖案化之第一半導體層51以形成奈米FET的通道區。
現在參考第3圖,根據一些實施例,在基材50中形成鰭狀結構66並在多層堆疊64中形成奈米結構55。在一些實施例中,可分別藉由在多層堆疊64及基材50中蝕刻溝槽,在多層堆疊64及基材50中形成奈米結構55及鰭狀結構66。蝕刻製程可為任何可接受的蝕刻製程,諸如反應離子蝕刻(reactive ion etch;RIE)、中子束蝕刻(neutral beam etch;NBE)、類似製程、或其等的組合。蝕刻製程可為各向異性製程。藉由蝕刻多層堆疊64形成奈米結構55之製程,可進一步由第一半導體層51界定第一奈米結構52A至C(統稱作第一奈米結構52),並由第二半導體層53界定第二奈米結構54A至C(統稱作第二奈米結構54)。可將第一奈米結構52及第二奈米結構54進一步統稱作奈米結構55。
可藉由任何合適的方法圖案化鰭狀結構66及奈米結構55。舉例而言,可使用一個或更多個光微影製程,包含雙圖案化或多圖案化製程,以圖案化鰭狀結構66及奈米結構55。通常而言,雙圖案化或多圖案化製程結合光微影製程及自對準製程,而允許待創建之圖案化具有,舉例而言,比其他使用單一、直接光微影製程所能獲得之間距更小的間距。舉例而言,在一些實施例中,使用光微影製程,以在基材之上形成犠牲層並圖案化犠牲層。使用自對準製程,以在圖案化的犠牲層旁邊形成間隔件。接著去除犠牲層,且接著將其餘的間隔件用於圖案化鰭狀結構66。
用於例示性目的,第3圖例示n型區50N及p型 區50P中之鰭狀結構66為具有大致上相等的寬度。在一些實施例中,n型區50N中之鰭狀結構66的寬度可比p型區50P中之鰭狀結構66的寬度更大或更薄。進一步地,縱使每個鰭狀結構66及奈米結構55皆例示為整個具有一致的寬度,而在其他實施例中,鰭狀結構66及/或奈米結構55可具有錐形的側壁,使得每個鰭狀結構66及/或奈米結構55的寬度在朝向基材50之方向連續增加。在此等實施例中,每個奈米結構55可具具有不同寬度,且形狀為梯形。
在第4圖中,在鰭狀結構66毗鄰處形成STI區68。可藉由在基材50、鰭狀結構66及奈米結構55之上、及毗鄰的鰭狀結構66間沉積絕緣材料,以形成STI區68。絕緣材料可為氧化物,諸如氧化矽、氮化物、類似者、或其等的組合,且可藉由高密度電漿CVD(high-density plasma CVD;HDP-CVD)、可流動CVD(flowable CVD;FCVD)、類似製程、或其等的組合,形成絕緣材料。可使用藉由任何可接受的製程所形成之其他絕緣材料。在所例示的實施例中,絕緣材料是藉由FCVD製程所形成之氧化矽。一旦形成絕緣材料,即可進行退火製程。在一實施例中,可形成絕緣材料使得多餘絕緣材料覆蓋奈米結構55。儘管將絕緣材料例示為單一層,但一些實施例可利用多個層。舉例而言,在一些實施例中,可首先沿著基材50、鰭狀結構66、及奈米結構55的表面形成襯裡(並未另外例示)。此後,可在襯裡之上形成諸如前文所論述之填 充材料。
接著將去除製程應用於絕緣材料,以去除奈米結構55之上之多餘絕緣材料。在一些實施例中,可利用諸如化學機械拋光(chemical mechanical polish;CMP)、回蝕製程、其等的組合、或類似者之平坦化製程 平坦化製程暴露奈米結構55,其使得奈米結構55及絕緣材料的頂部表面在完成平坦化製程之後為齊平。
接著使絕緣材料凹陷以形成STI區68。使絕緣材料凹陷,使得n型區50N及p型區50P中之鰭狀結構66的奈米結構55及上部分從相鄰的STI區68間突出。進一步地,STI區68的頂部表面可具有如所例示之平坦表面、凸起狀表面、凹入狀表面(諸如凹碟狀)、或其等的組合。可藉由適當的蝕刻將STI區68的頂部表面形成平坦、凸起狀、及/或凹入狀。可使用可接受的蝕刻製程,諸如對絕緣材料(例如,以比鰭狀結構66及奈米結構55的材料更快的速率,蝕刻絕緣材料的材料)的材料具有選擇性之一個製程,使STI區68凹陷。舉例而言,可使用,舉例而言,使用稀釋的氫氟(dilute hydrofluoric acid;dHF)酸,去除氧化物。
去除前文參照第2至4圖所描述之製程僅為如何形成鰭狀結構66及奈米結構55之一個範例。在一些實施例中,可使用遮罩及磊晶成長製程形成鰭狀結構66及/或奈米結構55。舉例而言,可在基材50的頂部表面之上形成介電層,且可將溝槽蝕刻通過介電層以暴露下層的基材 50。可在溝槽中磊晶地成長磊晶結構,且可使介電層凹陷使得磊晶結構從介電層突出以形成鰭狀結構66及/或奈米結構55。磊晶結構可包括前文所論述之交替半導體材料,諸如第一半導體材料及第二半導體材料。在磊晶結構為磊晶地成長之一些實施例中,磊晶成長材料可在成長期間被原位摻雜,儘管可一起使用原位摻雜與植入製程,在成長期間被原位摻雜可免除之前及/或後續的植入製程。
額外地,僅用於例示性目的,在本文中將第一半導體層51(及所得第一奈米結構52)及第二半導體層53(及所得第二奈米結構54)例示及論述為在p型區50P及n型區50N中包括相同材料。藉此,在一些實施例中,第一半導體層51及第二半導體層53中的一者或兩者可為不同材料,或以不同順序在p型區50P及n型區50N中形成第一半導體層51及第二半導體層53中的一者或兩者。
進一步在第4圖中,可在鰭狀結構66、奈米結構55、及/或STI區68中形成適當的阱(並未另外例示)。在具有不同阱類型之實施例中,可使用光抗蝕劑或其他遮罩(並未另外例示),以實現n型區50N及p型區50P之不同植入步驟。舉例而言,可在n型區50N和p型區50P中之鰭狀結構66及STI區68之上形成光抗蝕劑。圖案化光抗蝕劑以暴露p型區50P。可藉由使用旋塗技術形成光抗蝕劑,並可使用可接受的光微影製程技術圖案化光抗蝕劑。一旦圖案化光抗蝕劑,在p型區50P中進行n型雜質植入,且光抗蝕劑可充當遮罩以大致地防止n型雜質被植 入至n型區50N中。n型雜質可為以自約1013原子/cm3至約1014原子/cm3範圍內之濃度,被植入至n型區50N中之磷、砷、銻、或類似物。在植入之後,(諸如藉由可接受的灰化製程)去除光抗蝕劑。
在p型區50P植入之後或之前,在p型區50P及n型區50N中之鰭狀結構66、奈米結構55、及STI區68之上形成光抗蝕劑或其他遮罩(並未另外例示)。圖案化光抗蝕劑以暴露n型區50N。可藉由使用旋塗技術形成光抗蝕劑,並可使用可接受的光微影製程技術圖案化光抗蝕劑。一旦圖案化光抗蝕劑,在n型區50N中進行n型雜質植入,且光抗蝕劑可充當遮罩以大致地防止p型雜質被植入至p型區50P中。p型雜質可為以自約1013原子/cm3至約1014原子/cm3範圍內之濃度,被植入至p型區50P中之硼、氟化硼、銦、或類似者。在植入之後,可(諸如藉由可接受的灰化製程)去除光抗蝕劑。
在n型區50N及p型區50P的植入之後,可進行退火以修復植入損壞並活化已植入之p型及/或n型雜質。在一些實施例中,可在成長期間原位摻雜磊晶鰭狀結構的成長材料,儘管可一起使用原位摻雜與植入製程,在成長期間原位摻雜可免除之前及/或之後的植入製程。
在第5圖中,在鰭狀結構66及/或奈米結構55上形成虛設介電層70。虛設介電層70可為,舉例而言,氧化矽、氮化矽、其等的組合、或類似物,且可根據可接受的技術,沉積或熱成長虛設介電層70。在虛設介電層 70之上形成虛設閘極層72,並在虛設閘極層72之上形成遮罩層74。可在虛設介電層70之上沉積虛設閘極層72,且接著,諸如藉由CMP,平坦化虛設閘極層72。可在虛設閘極層72之上沉積遮罩層74。虛設閘極層72可為導電或非導電材料,且可選自包含以下各者之群組:非晶矽、多晶矽、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物、及金屬。可藉由物理氣相沉積(physical vapor deposition;PVD)、CVD、濺鍍沉積、或其他用於沉積所選材料之技術,以沉積虛設閘極層72。虛設閘極層72可由相對於隔離區的蝕刻製程具有高蝕刻選擇性之其他材料所製成。遮罩層74可包含,舉例而言,氮化矽、氧氮化矽、或類似者。在此範例中,跨n型區50N及p型區50P形成單一虛設閘極層72及單一遮罩層74。僅用於例示性目的,注意到,圖示虛設介電層70僅覆蓋鰭狀結構66及奈米結構55。在一些實施例中,可沉積虛設介電層70使得虛設介電層70覆蓋STI區68,使得虛設介電層70在虛設閘極層72與STI區68間延伸。
第6A至26B圖例示實施例元件的製造中之各種額外步驟。第6A至26B圖例示在n型區50N亦或p型區50P中之特徵。在第6A至6C圖中,可使用可接受的光微影製程及蝕刻技術圖案化遮罩層74(參見第5圖)以形成遮罩78。接著可將遮罩78的圖案化轉移至虛設閘極層72及至虛設介電層70,以分別形成虛設閘極76及虛設閘極介電質71。虛設閘極76覆蓋鰭狀結構66的對應通道 區及第二奈米結構54之形成通道區的部分。可將遮罩78的圖案化用於使每個虛設閘極76與毗鄰的虛設閘極76實體地分離。虛設閘極76可具有垂直於鰭狀結構66中之對應鰭狀結構66的長度方向之長度方向。
在第7A至7C圖中,在第6A至6C圖中所例示之結構之上形成第一間隔件層80及第二間隔件層82。隨後圖案化第一間隔件層80及第二間隔件層82,以充當用於形成自對準源極/汲極區之間隔件。在第7A至7C圖中,在STI區68的頂部表面;鰭狀結構66、虛設閘極介電質71、及虛設閘極76的側面;奈米結構55及遮罩78的頂部表面及側面上形成第一間隔件層80。在第一間隔件層80之上沉積第二間隔件層82。可使用諸如熱氧化之技術,由氧化矽、氮化矽、氧氮化矽、或類似者,形成第一間隔件層80,或藉由CVD、ALD、或類似製程,沉積第一間隔件層80。可由具有與第一間隔件層80的材料不同蝕刻速率之材料,形成第二間隔件層82,諸如氧化矽、氮化矽、氧氮化矽、或類似者,並可藉由CVD、ALD、或類似製程,沉積第二間隔件層82。第一間隔件層80及第二間隔件層82可包括低k值介電材料。
在形成第一間隔件層80之後並在形成第二間隔件層82之前,可進行用於輕度摻雜源極/汲極(lightly doped source/drain;LDD)區(並未另外例示)之植入製程。在具有不同元件類型的實施例中,與前文第4圖中所論述之植入製程類似,在暴露p型區50P時,可在n型 區50N之上形成遮罩(諸如光抗蝕劑),並可將適當的類型之(例如,p型)雜質植入p型區50P中之暴露鰭狀結構66及奈米結構55之中。接著可去除遮罩。隨後,在暴露n型區50N時,可在p型區50P之上形成遮罩(諸如,光抗蝕劑),並可將適當的類型之(例如,n型)雜質植入至n型區50N中之暴露鰭狀結構66及奈米結構55中。接著可去除遮罩。n型雜質可為先前所論述之n型雜質中的任何雜質,且p型雜質可為先前所論述之p型雜質中的任何雜質。輕度摻雜源極/汲極區可具有在自約1x1015原子/cm3至約1x1019原子/cm3範圍內之濃度的雜質。可將退火用於修復植入損壞並活化植入的雜質。
在第8A至8C圖中,蝕刻第一間隔件層80及第二間隔件層82以分別形成第一間隔件81及第二間隔件83。在後文所更詳細地論述,第一間隔件81及第二間隔件83用於自對準隨後所形成的源極/汲極區,暨在後續處理期間保護鰭狀結構66及/或奈米結構55的側壁。可使用合適的蝕刻製程(諸如,各向同性蝕刻製程(例如,濕式蝕刻製程)、各向異性蝕刻製程(例如,乾式蝕刻製程)、或類似製程),以蝕刻第一間隔件層80及第二間隔件層82。在一些實施例中,第二間隔件層82的材料具有與第一間隔件層80的材料不同的蝕刻速率,使得當圖案化第二間隔件層82時,第一間隔件層80可充當蝕刻停止層。當圖案化第一間隔件層80時,第二間隔件層82可充當遮罩。舉例而言,可使用各向異性蝕刻製程蝕刻第二間隔件層82,其 中第一間隔件層80充當蝕刻停止層。第二間隔件層82的其餘部分形成第二間隔件83,如第8B及8C圖中所例示。接著,第二間隔件83充當遮罩,同時蝕刻形成第一間隔件81的第一間隔件層80的暴露部分,如第8B及8C圖中所例示。
如第8B圖中所例示,將第一間隔件81及第二間隔件83設置在遮罩78、虛設閘極76及虛設閘極介電質71的側壁上。在一些實施例中,可將第一間隔件81及第二間隔件83的頂部表面設置在遮罩78的頂部表面之下方。第一間隔件81及第二間隔件83的頂部表面可被設置為與遮罩78的頂部表面齊平或在遮罩的頂部表面之上方。在一些實施例中,可從毗鄰遮罩78、虛設閘極76、及虛設閘極介電質71之第一間隔件81之上去除第二間隔件83。如第8C圖中所例示,將第一間隔件81及第二間隔件83設置於鰭狀結構66及/或奈米結構55的側壁上。
應注意到,前文揭露內容總體上描述形成間隔件及LDD區的製程。可使用其他製程及順序。舉例而言,可利用更少或額外的間隔件,可利用不同順序的步驟(例如,可在沉積第二間隔件層82之前圖案化第一間隔件81,可形成並去除間隔件、及/或類似者。此外,可使用不同結構及步驟形成n型及p型元件。
在第9A至9C圖中,在鰭狀結構66、奈米結構55、及基材50中形成第一凹陷87。隨後在第一凹陷87中形成磊晶源極/汲極區。第一凹陷87可延伸通過第一奈 米結構52及第二奈米結構54,並進入基材50。在一些實施例中,STI區68的頂部表面可與第一凹陷87的底部表面齊平。在一些實施例中,STI區68的頂部表面可在第一凹陷87的底部面之上方或之下方。可使用各向異性蝕刻製程,諸如RIE、NBE、或類似製程,藉由蝕刻鰭狀結構66、奈米結構55、及基材50,形成第一凹陷87。在被使用於形成第一凹陷87之蝕刻製程期間,第一間隔件81、第二間隔件83、及遮罩78遮蔽鰭狀結構66的部分、奈米結構55、及基材50。可將單一蝕刻製程或多個蝕刻製程用於蝕刻奈米結構55及/或鰭狀結構66的每個層。在第一凹陷87達到符合需求的深度之後,可使用時間控制的蝕刻製程停止蝕刻。
在第10A及10B圖中,蝕刻藉由第一凹陷87所暴露之由第一半導體材料(例如,第一奈米結構52)所形成的多層堆疊64的層的側壁的部分,以形成側壁凹陷88。儘管在第10B圖中將毗鄰側壁凹陷88之第一奈米結構52的側壁例示為筆直,但側壁可為凹入狀或凸起狀。可使用各向同性蝕刻製程,諸如濕式蝕刻製程、或類似製程,以蝕刻此等側壁。在第一奈米結構52包含,例如,SiGe,且第二奈米結構54包含,例如,Si或SiC之實施例中,可使用採用氫氧化四甲基銨(tetramethylammonium hydroxide;TMAH)、氫氧化銨(NH4OH)之乾式蝕刻製程,或類似者蝕刻第一奈米結構52的側壁。
在第11A至11C圖中,在側壁凹陷88中形成第 一內部間隔件90。可藉由將內部間隔件層(並未另外例示)沉積在第10A及10B圖中所例示之結構之上,形成第一內部間隔件90。第一內部間隔件90充當隨後所形成的源極/汲極區及閘極結構間之隔離特徵。如將在以下所詳細地論述,將在第一凹陷87中形成源極/汲極區,而第一奈米結構52將被閘極結構替換。
可藉由似型沉積製程,諸如CVD、ALD、或類似製程沉積內部間隔件層。儘管可利用任何合適的材料,諸如,可具有小於約3.5之k值的低介電常數(低k值)材料,內部間隔件層可包括諸如氮化矽或氧氮化矽之材料。接著可各向異性地蝕刻內部間隔件層,以形成第一內部間隔件90。儘管將第一內部間隔件90的外側壁例示成與第二奈米結構54的側壁齊平,但第一內部間隔件90的外側壁可延伸超過第二奈米結構54的側壁或從第二奈米結構54的側壁凹陷。
此外,儘管在第11B圖中,將第一內部間隔件90的外部側壁例示為直的形狀,但第一內部間隔件90的外部側壁可為凹入狀或凸起狀。作為範例,第11C圖例示之實施例,其中第一奈米結構52的側壁為凹入狀、第一內部間隔件90的外部側壁為凹入狀、且第一內部間隔件90從第二奈米結構54的側壁凹陷。可藉由各向異性蝕刻製程,諸如RIE、NBE、或類似製程,蝕刻內部間隔件層。可將第一內部間隔件90使用於防止被後續蝕刻製程(諸如用於形成閘極結構之蝕刻製程),對隨後所形成的源極/汲極區(諸 如以下參照第12A至12E圖所論述之磊晶源極/汲極區92)的損壞。
在第12A至12E圖中,在第一凹陷87中形成磊晶源極/汲極區92。在一些實施例中,磊晶源極/汲極區92可在第二奈米結構54上施加應力,從而改善性能。如第12B圖中所例示,在第一凹陷87中形成磊晶源極/汲極區92,使得每個虛設閘極76被設置於磊晶源極/汲極區92的對應相鄰對間。在一些實施例中,將第一間隔件81及第二間隔件83使用於使磊晶源極/汲極區92以適當的橫向距離與虛設閘極76分離,且將第一內部間隔件90使用於使磊晶源極/汲極區92與第一奈米結構52以適當的橫向距離分離,以便磊晶源極/汲極區92不會與隨後所形成的所得奈米FET的閘極短路。
可藉由遮蔽p型區50P(例如,PMOS區),形成n型區50N(例如,NMOS區)中之磊晶源極/汲極區92。接著,在n型區50N中之第一凹陷87中,磊晶地成長磊晶源極/汲極區92。磊晶源極/汲極區92可包含任何適用於n型奈米FET之可接受的材料。舉例而言,若第二奈米結構54為矽,則磊晶源極/汲極區92可包含在第二奈米結構54上施加拉伸應變之材料,諸如矽、碳化矽、摻磷碳化矽、磷化矽、或類似者。磊晶源極/汲極區92可具有從奈米結構55的對應上表面凸起之表面且可具有刻面。
可藉由遮蔽n型區50N(例如,NMOS區),形成p型區50P(例如,PMOS區)中之磊晶源極/汲極區92。 接著,在p型區50P中之第一凹陷87中,磊晶地成長磊晶源極/汲極區92。磊晶源極/汲極區92可包含任何適用於p型奈米FET之可接受的材料。舉例而言,若第二奈米結構54為矽,則磊晶源極/汲極區92可包括在第二奈米結構54上施加壓縮應變之材料,諸如矽鍺、硼摻雜矽鍺、鍺、鍺錫、或類似者。磊晶源極/汲極區92亦可具有從奈米結構55的對應上表面凸起之表面且可具有刻面。
與先前所論述之用於形成輕度摻雜源極/汲極區之製程類似,可將摻雜劑植入磊晶源極/汲極區92,第一奈米結構52、第二奈米結構54、及/或基材50,以形成源極/汲極區,隨後進行退火。源極/汲極區可具有在約1x1019原子/cm3及約1x1021原子/cm3間的雜質濃度。用於源極/汲極區之n型及/或p型雜質可為先前所論述之任何雜質。在一些實施例中,可在成長期間原位摻雜磊晶源極/汲極區92。
由於被使用於在n型區50N和p型區50P中形成磊晶源極/汲極區92之磊晶術製程,磊晶源極/汲極區92的上表面具有刻面,此等刻面橫向地向外擴展超過奈米結構55的側壁。在一些實施例中,如第12C圖中所例示,此等刻面致使相同的奈米SFET的毗鄰磊晶源極/汲極區92合併。在一些實施例中,如第12D圖所例示,在完成磊晶術製程之後,毗鄰的磊晶源極/汲極區92保持分離。在第12C及12D圖中所例示之實施例中,可在STI區68的頂部表面之上形成第一間隔件81且第一間隔件81可阻 止磊晶成長。在一些實施例中,第一間隔件81可覆蓋奈米結構55的側壁的部分,而進一步阻止磊晶成長。在一些實施例中,可調整被使用於形成第一間隔件81之間隔件蝕刻,以去除間隔件材料,以允許磊晶源極/汲極區92延伸至STI區68的頂部表面。
磊晶源極/汲極區92可包括一個或更多個半導體材料層。舉例而言,磊晶源極/汲極區92可包括第一半導體材料層92A、第二半導體材料層92B、及第三半導體材料層92C。可將任意數量的半導體材料層用於磊晶源極/汲極區92。可由不同半導體材料形成第一半導體材料層92A、第二半導體材料層92B、及第三半導體材料層92C中之每個材料層,且以不同摻雜劑濃度,摻雜此等材料層。在一些實施例中,第一半導體材料層92A可具有小於第二半導體材料層92B及大於第三半導體材料層92C之摻雜劑濃度。在磊晶源極/汲極區92包括三個半導體材料層之實施例中,可沉積第一半導體材料層92A、可在第一半導體材料層92A之上沉積第二半導體材料層92B、且可在第二半導體材料層92B之上沉積第三半導體材料層92C。
第12E圖例示實施例,其中第一奈米結構52的側壁為凹入狀且第一內部間隔件90的外側壁為凹入狀。第一內部間隔件90從第二奈米結構54的側壁凹陷。如第12E圖中所例示,可將磊晶源極/汲極區92形成為與第一內部間隔件90接觸。磊晶源極/汲極區92可延伸超過第二奈米結構54的側壁。
在第13A及13B圖中,在第12A及12B圖中所例示之結構之上沉積第一層間介電質(interlayer dielectric;ILD)96。可由介電材料形成第一ILD 96,並可藉由任何合適的方法,諸如CVD、電漿加強CVD(plasma-enhanced CVD;PECVD)、或FCVD,沉積第一ILD96。介電材料可包含磷矽酸鹽玻璃(phospho-silicate glass;PSG)、硼矽酸鹽玻璃(boro-silicate glass;BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phospho-silicate glass;BPSG)、未摻雜矽酸鹽玻璃(un-doped silicate glass;USG)、或類似者。可使用藉由任何可接受的製程所形成之其他絕緣材料。在一些實施例中,將接觸蝕刻停止層(contact etch stop layer;CESL)94設置於第一ILD 96與磊晶源極/汲極區92、遮罩78、及第一間隔件81間。CESL94可包括諸如,氮化矽、氧化矽、氧氮化矽、或類似者之介電材料,此介電材料具有與上層的第一ILD 96的材料不同蝕刻速率。
在第14A及14B圖中,可進行平坦化製程,諸如CMP,以使第一ILD 96的頂部表面與虛設閘極76或遮罩78的頂部表面齊平。平坦化製程亦可去除虛設閘極76上之遮罩78,以及第一間隔件81沿著遮罩78的側壁的部分。在平坦化製程之後,虛設閘極76、第一間隔件81、及第一ILD 96的頂部表面在製程變量之內齊平。據此,通過第一ILD 96暴露虛設閘極76的頂部表面。在一些 實施例中,遮罩78可保留,在此種情況下,平坦化製程使第一ILD 96的頂部表面與遮罩78及第一間隔件81的頂部表面齊平。
進一步地,在第14A及14B圖中,回蝕第一ILD 96及CESL94,並在第一ILD 96及CESL94之上形成保護層97。可使用諸如RIE、NBE、或類似物之各向異性蝕刻製程或諸如濕式蝕刻製程之各向同性蝕刻製程回蝕第一ILD 96及CESL94。然後可使用CVD、PECVD、ALD、濺鍍、或類似物在所得結構之上沉積保護層97,並使用諸如CMP的製程將保護層平坦化。如第14A及14B圖中所例示,在保護層97的平坦化之後,保護層97的頂部表面可與第一間隔件81、第二間隔件83、及虛設閘極76的頂部表面齊平。保護層97可由諸如氮化矽、氧化矽、碳氧化矽、碳氮氧化矽、碳氮化矽、其等的組合或多個層、或類似者之材料所形成。可在第一ILD 96及CESL94之上形成保護層97,以保護第一ILD 96及CESL94免於後續的蝕刻製程。
在第15A及15B圖中,在一個或更多個蝕刻步驟中去除虛設閘極76及遮罩78(若存在時),以便形成第二凹陷98。亦去除在第二凹陷98中之部分的虛設閘極介電質71。在一些實施例中,藉由各向異性乾式蝕刻製程去除虛設閘極76及虛設閘極介電質71。舉例而言,蝕刻製程可包含使用反應氣體之乾式蝕刻製程,此(等)反應氣體以比保護層97、第一間隔件81、第二間隔件83、奈米結構 55、或STI區68更快的速率選擇性地蝕刻虛設閘極76。每個第二凹陷98暴露及/或覆壓部分的奈米結構55,在隨後所完成的奈米FET中,此奈米結構充當通道區。將充當通道區之部分的奈米結構55設置於磊晶源極/汲極區92的相鄰對間。在去除期間,當蝕刻虛設閘極76時,可將虛設閘極介電質71用於蝕刻停止層。在虛設閘極76的去除製程之後,可接著去除虛設閘極介電質71。
在第16A及16B圖中,去除第一奈米結構52而延伸第二凹陷98。可藉由使用對第一奈米結構52的材料具有選擇性之蝕刻劑進行諸如濕式蝕刻之各向同性蝕刻製程或類似者,以去除第一奈米結構52,而與第一奈米結構52相比較,第二奈米結構54、基材50、及STI區68保持相對未被蝕刻。在第一奈米結構52包含,例如SiGe,且第二奈米結構54A至54C包含,例如Si或SiC之實施例中,可將氫氧化四甲基銨(TMAH)、氫氧化銨(NH4OH)、或類似者用於去除n型區50N中之第一奈米結構52。
在第17A至23H圖中,形成閘極介電層及閘極電極以替換第二凹陷98中之閘極。在n型區50N中所形成之閘極電極包含抗反應層,此抗反應層提供閾值電壓(Vt)提升。在抗反應層之上形成n型功函數層,並在抗反應層及n型功函數層之上形成並覆蓋p型功函數層。接著在p型功函數層之上形成金屬覆蓋件層。形成覆蓋抗反應層之p型功函數層允許選擇性地沉積金屬覆蓋件層。金屬覆蓋件 層減少閘極電阻。因此可改善元件性能。
在n型區50N及p型區50P中之閘極介電層的形成可同時發生,使得每個區中之閘極介電質是由相同的材料所形成。閘極電極的形成可同時發生,使得每個區中之閘極電極是由相同的材料所形成。在一些實施例中,可藉由不同的製程形成每個區中之閘極介電層,使得閘極介電層可為不同的材料及/或可具有不同數量的層。可藉由不同的製程形成每個區中之閘極電極,使得閘極電極可為不同的材料及/或具有不同數量的層。當使用相異製程時,可將各種遮罩步驟用於遮蔽及暴露適當的區。在後文的描述中,單獨地形成至少部分的n型區50N的閘極電極及p型區50P的閘極電極。
在第17A及17B圖中,在n型區50N及p型區50P中之第二凹陷98中似型地沉積閘極介電層100。可在鰭狀結構66的頂部表面及側表面上及第二奈米結構54的頂部表面、側表面、及底部表面上形成閘極介電層100。亦可在保護層97,第二間隔件83、及STI區68的頂部表面上;在閘極區上;在第一間隔件81的頂部表面及側表面上;在第一內部間隔件90的側表面上沉積閘極介電層100。閘極介電層100包括一層或更多層的介電層,諸如氧化物、金屬氧化物、類似者、或其等的組合。在一些實施例中,閘極介電層100可包括在第一閘極介電層之上之第一閘極介電層(例如,包括氧化矽、或類似物)及第二閘極介電層(例如,包括金屬氧化物、或類似物)。在一些實 施例中,第二閘極介電層包含高k值介電材料。在此等實施例中,第二閘極介電層可具有大於約7.0之k值,並可包含鋯、鋁、鋯、鑭、錳、鋇、鈦、鉛、及其等組合的金屬氧化物或矽酸鹽。在一些實施例中,第一閘極介電可被稱作界面層,且第二閘極介電可被稱作高k值閘極介電。
在n型區50N及p型區50P中之閘極介電層100的結構可為相同或不同結構。舉例而言,在n型區50N中形成閘極介電層100的同時,可遮蔽或暴露p型區50P。在暴露p型區50P之實施例中,可在p型區50P中同時形成閘極介電層100。閘極介電層100的形成方法可包含分子束沉積(MBD)、ALD、PECVD、及類似方法。
在第18A及18B圖中,在n型區50N中之閘極介電層100之上似型地沉積第一導電材料102。在n型區50N中沉積第一導電材料102之同時,可遮罩p型區50P。在一些實施例中,第一導電材料102為n型功函數層,其可包括AlCu、TiAlC、TiAlN、TiAl、Al、TaAl、TaAlC、Ti、Al、Mg、Zn、其他合適的n型功函數材料、其等的組合、或類似物。在一些實施例中,第一導電材料102可包括鋁基的材料。可藉由ALD、CVD、PVD、或類似製程沉積第一導電材料102。可將第一導電材料102沉積至自約1奈米至約4奈米範圍之厚度。
在一些實施例中,可在沉積抗反應層104之前在第一導電材料102之上形成中間層(並未另外例示)。中間層可包含阻擋層、擴散層、黏附層、其等的組合或多個層、 或類似物。在一些實施例中,中間層可包括包含氯(Cl)、或類似物之材料。可藉由ALD、CVD、PVD、或類似製程沉積中間層。
進一步地,在第18A及18B圖中,在n型區50N中之第一導電材料102之上似型地沉積抗反應層104。當在n型區50N中沉積抗反應層104時,可遮蔽p型區50P。抗反應層104可保護第一導電材料102免受氧化。抗反應層104可由與第一導電材料102的材料不同的材料所形成。在一些實施例中,抗反應層104可包括介電材料。在一些實施例中,抗反應層104可包括矽基的材料。在一些實施例中,抗反應層104可包括矽(Si)、氧化矽(SiOx)、氮化矽(SiN)、氧氮化矽(SiON)、碳氮化矽(SiCN)、碳化矽(SiC)、其等的組合或多個層、或類似物。然而,可利用任何合適的材料。可藉由使用諸如ALD、CVD、PVD、或類似物之沉積製程,以形成抗反應層104。可將抗反應層104至沉積自約0.3奈米至約5奈米範圍之厚度。抗反應層104的厚度可在第一導電材料102的厚度的10%與50%間。此比值允許空間節省,同時仍有效地防止或減少第一導電材料102的氧化。
在一些實施例中,可在形成第一導電材料102之後原位(in situ)形成抗反應層104,而無需移動中間地形成的元件。因此,可在第一導電材料102上形成抗反應層104而不致破壞沉積工具或設備(諸如處理腔室)的真空。在一些實施例中,可在不破壞真空的情況下將中間地形成 的元件移動至同一工具之內之另一處理腔室。由於維持真空,所以可消除或顯著減少第一導電材料102的氧化。
包含抗反應層104為n型區50N中之閘極電極提供閾值電壓提升,此舉允許閾值電壓隨同第一導電材料102的更薄厚度適當地微調。此舉允許用於在其中沉積隨後所形成的金屬填充物之更大的空間。舉例而言,在一些實施例中,第一導電材料102的厚度及抗反應層104的厚度的組合可在第一導電材料的相同材料的厚度的50%至80%間,在無抗反應層104的情況下第一導電材料展現相同或類似的閾值電壓。
在第19A及19B圖中,在抗反應層104之上之第二凹陷98中形成第一遮罩層106。可藉由旋塗塗覆或類似者沉積第一遮罩層106。第一遮罩層106可包含聚合物材料,諸如聚(甲基)丙烯酸酯、聚(馬來酰亞腔)、線型酚醛清漆(novolacs)、聚(醚)、其等的組合、或類似物。在一些實施例中,第一遮罩層106可為底部抗反射塗層材料。如第19A及19B圖中所例示,第一遮罩層106可填充部分的第二凹陷98,此部分在第二奈米結構54的垂直毗鄰的第二奈米結構54間延伸,並在第二奈米結構54與鰭狀結構66間延伸。
在沉積第一遮罩層106之後,可回蝕第一遮罩層106,使得第一遮罩層106的頂部表面在保護層97的頂部表面之下方並在第二奈米結構54的頂部表面之上方。可藉由一個或更多個蝕刻製程,諸如各向同性蝕刻製程(例如, 濕式蝕刻製程)、各向異性蝕刻製程(例如,乾式蝕刻製程)、其等的組合、或類似者蝕刻第一遮罩層106。可使用對第一遮罩層106的材料具有選擇性(例如,以比抗反應層104的材料更快的速率蝕刻第一遮罩層106之材料)之蝕刻製程回蝕第一遮罩層106。可在第二奈米結構54C的頂部表面之上方,在自約5奈米至約20奈米範圍之距離D1,設置第一遮罩層106的頂部表面。可在第二奈米結構54C的頂部表面之上方,在自約25奈米至約120奈米範圍之距離D2,設置第一間隔件81、第二間隔件83、及保護層97的頂部表面。距離D1與距離D2的比值可在自約5至約24之範圍。
在第20A及20B圖中,蝕刻抗反應層104及第一導電材料102。可藉由一種或更多種蝕刻製程,諸如各向同性蝕刻製程(例如,濕式蝕刻製程)、各向異性蝕刻製程(例如,乾式蝕刻製程)、其等的組合、或類似物,以蝕刻抗反應層104及第一導電材料102。在一些實施例中,可藉由使用第一遮罩層106作為遮罩之第一蝕刻製程,以蝕刻抗反應層104。第一蝕刻製程可暴露第一導電材料102的頂部部分及側壁部分。接著可藉由使用抗反應層104及第一遮罩層106作為遮罩之第二蝕刻製程,以蝕刻第一導電材料102。在一些實施例中,第一蝕刻製程及第二蝕刻製程可為各向同性濕式蝕刻製程。在一些實施例中,可同時蝕刻抗反應層104及第一導電材料102。如第20B圖中所例示,可蝕刻抗反應層104及第一導電材料102, 使得抗反應層104及第一導電材料102的頂部表面與第一遮罩層106的頂部表面彼此齊平。在一些實施例中,可在不同的水平處置設置抗反應層104及第一導電材料102的頂部表面。
第20C及20D圖例示實施例,其中回蝕第一導電材料102及抗反應層104以形成毗鄰第一間隔件81及第二間隔件83之平面區。在一些實施例中,可在沉積抗反應層104之前回蝕第一導電材料102,可沉積抗反應層104,並可形成第一遮罩層106並將第一遮罩層106用於蝕刻抗反應層104。如第20C圖中所例示,抗反應層104的頂部表面可與第一遮罩層106的頂部表面齊平。如第20D圖所例示,第一導電材料102及抗反應層104的頂部表面可為平坦的,並可在閘極介電層100的相對側表面間延伸。可將抗反應層104的頂部表面設置在第一導電材料102的頂部表面上方。
在第21A及21B圖中,去除第一遮罩層106,且在n型區50N中的抗反應層104,第一導電材料102及閘極介電層100之上形成第二導電材料108。在第21C及21D圖中,在p型區50P中的閘極介電層100之上形成第二導電材料108。第21A及21B圖例示n型區50N,第21C及21D圖例示p型區50P。可藉由電漿灰化,諸如各向同性或各向異性蝕刻製程、或類似者之蝕刻製程去除第一遮罩層106。
第二導電材料108可填充第二凹陷98並在保護 層97上之閘極介電層100之上延伸。可藉由諸如ALD、CVD、PVD、或類似物之製程,似型地沉積第二導電材料108。在一些實施例中,第二導電材料108為p型功函數層,其可包括W、Cu、TiN、Ti、Pt、Ta、TaN、Co、Ni、TaC、TaCN、TaSiN、TaSi2、NiSi2、Mn、Zr、ZrSi2、TaN、Ru、Mo、MoSi2、WN、WCN、其他金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽酸鹽、金屬的氧氮化物、金屬鋁酸鹽、鋯矽酸鹽、鋁酸鋯、其他合適的n型功函數材料、其等的組合、或類似物。在填充第二凹陷98之後,可進行平坦化製程,諸如CMP,以去除第二導電材料108的多餘部分,多餘部分在保護層97、第一間隔件81、及第二間隔件83的頂部表面之上。在p型區50P中之第二導電材料108的頂部表面可與在n型區50N中之第一導電材料102的底部表面齊平並在n型區50N中之第二導電材料108的底部表面之下方。
如第21A及21B圖所例示,可在第一導電材料102及抗反應層104的頂部表面上沉積第二導電材料108。第二導電材料108可覆蓋抗反應層104。隨後,可在第二導電材料108之上選擇性地沉積導電覆蓋件材料。由於抗反應層104是由介電材料所形成,所以抗反應層104可能阻礙導電覆蓋件材料的選擇性沉積。在抗反應層104之上形成第二導電材料108有助於導電覆蓋件材料的後續沉積,將導電覆蓋件材料使用於減少閘極電阻,同時提供提升閾 值電壓的抗反應層104。此舉可改善元件性能。
在一些實施例中,在形成第二導電材料108之前,可在n型區50N中之抗反應層104、第一導電材料102、及閘極介電層100之上及在p型區50P中之閘極介電層100之上沉積黏膠層(並未另外例示),以改善第二導電材料108及下層的結構間之黏附性。黏膠層可進一步防止第二導電材料108及下層的結構間之擴散。黏膠層可包含任何可接受的材料以促進黏附並防止擴散。舉例而言,黏膠層可由金屬或金屬氮化物,諸如氮化鈦、鋁化鈦、氮化鋁鈦、摻雜矽的氮化鈦、氮化鉭、或類似者所形成,可藉由ALD、CVD、PVD、或類似者所沉積。
在第22A至22E圖中,回蝕第一間隔件81、第二間隔件83、閘極介電層100、及第二導電材料108以形成第三凹陷110。第22A、22B、及22E圖例示根據各種實施例之n型區50N,而第22C及22D圖例示p型區50P。可使用諸如各向同性蝕刻製程(例如,濕式蝕刻製程),各向異性蝕刻製程(例如,乾式蝕刻製程)、或類似者之合適的蝕刻製程,蝕刻第一間隔件81、第二間隔件83、閘極介電層100、及第二導電材料108。在一些實施例中,可藉由多個選擇性蝕刻製程,蝕刻第一間隔件81、第二間隔件83、閘極介電層100、及第二導電材料108,以便控制第一間隔件81、第二間隔件83、閘極介電層100、及第二導電材料108各者的高度。在第22A至22E圖所例示之實施例中,n型區50N中之第二導電材料108的頂部 表面可與p型區50P中之第二導電材料108的頂部表面齊平。在p型區50P中之第二導電材料108的高度可等於n型區50N中之第一導電材料102、抗反應層104、及第二導電材料108的結合高度。
如第22A至22D圖所例示,可蝕刻第一間隔件81、第二間隔件83、閘極介電層100、及第二導電材料108,使得第一間隔件81及第二間隔件83的頂部表面彼此齊平,並被設置在閘極介電層100及第二導電材料108的彼此齊平之頂部表面之上方。在第22B圖所例示之截面視圖中,第二導電材料108可為T形狀。如第22E圖所例示,可蝕刻第一間隔件81、第二間隔件83、閘極介電層100、及第二導電材料108使得第一間隔件81、第二間隔件83、及閘極介電層100的頂部表面彼此齊平並被設置在第二導電材料108的頂部表面之上方。可在第二導電材料108及/或閘極介電層100的頂部表面之上方,設置自約0奈米至約10奈米範圍高度H1之第一間隔件81、第二間隔件83、及/或閘極介電層100的頂部表面。可將高度H1使用於控制隨後所形成的導電覆蓋件材料的厚度,此厚度可用於減少閘極電阻並改善元件性能。
在第23A至23H圖中,在第二導電材料108之上之第三凹陷110中形成導電覆蓋件材料112。第23A、23B、及23E至23H圖例示根據各種實施例之n型區50N,而第23C及23D圖例示p型區50P。可藉由選擇性沉積製程形成導電覆蓋件材料112。舉例而言,可使用諸如 ALD、或類似者之製程在第二導電材料108上選擇性地沉積導電覆蓋件材料112。在一些實施例中,第二導電材料108亦可在閘極介電層100的頂部表面之上延伸。在一些實施例中,導電覆蓋件材料112可包括導電材料,諸如鎢(W)、鈷(Co)、釕(Ru)、或類似物。
如第23A及23B圖所例示,可在第二導電材料108之上沉積導電覆蓋件材料112,且第二導電材料108將導電覆蓋件材料112與抗反應層104分離。由於抗反應層104是由介電材料所形成,所以抗反應層104可能阻礙導電覆蓋件材料112的選擇性沉積。這樣,在抗反應層104之上沉積第二導電材料108以覆蓋抗反應層104。此舉有助於導電覆蓋件材料112的沉積,這減少由沉積導電覆蓋件材料112所致使之元件缺陷並減少成本。
在其中導電覆蓋件材料112包括鎢之實施例中,可使用氯化鎢(WCl5)為前驅物、氫氣(H2)為還原氣體、及氬氣(Ar)為裝載氣體,在自約300℃至約500℃之溫度範圍,自約10托至約50托之製程壓力範圍處沉積導電覆蓋件材料112。可在自約100℃至約150℃之溫度範圍供應氯化鎢前驅物。可將導電覆蓋件材料112至沉積至自約2奈米約5奈米範圍之厚度T1。在一些實施例中,導電覆蓋件材料112可進一步包括具有自約0.5%至約5%原子濃度範圍之氯。在n型區50N及閘極介電層100中之閘極介電層100、第一導電材料102、抗反應層104、第二導電材料108、及導電覆蓋件材料112、及在p型區50P 中之第二導電材料108、及導電覆蓋件材料112可統稱作「閘極結構」。可將在n型區50N中之第一導電材料102、抗反應層104、第二導電材料108、導電覆蓋件材料112及第二導電材料108、及在p型區50P中之導電覆蓋件材料112統稱作「閘極電極」。包含具有所規定厚度之導電覆蓋件材料112可減少閘極結構的電阻,這改善元件性能。
如第23A至23D圖所例示,導電覆蓋件材料112可沿著閘極介電層100及第二導電材料108的頂部表面在第二間隔件83的相對側表面間延伸。n型區50N及p型區50P中之導電覆蓋件材料的頂部表面可彼此齊平,並可與第一間隔件81及第二間隔件83的頂部表面齊平。在第23E圖所例示之實施例中,閘極介電層100的頂部表面與第二間隔件83及第一間隔件81及齊平並在第二導電材料108的頂部表面之上方。導電覆蓋件材料112在閘極介電層100的相對側表面間沿著第二導電材料108的頂部表面延伸。在第23F圖所例示之實施例中,第二導電材料108及閘極介電層100的頂部表面與第二間隔件83及第一間隔件81的頂部表面齊平。導電覆蓋件材料112可沿著第二導電材料108及閘極介電層100的頂部表面延伸,且第二間隔件83及第一間隔件81的頂部表面可不具有導電覆蓋件材料112。在一些實施例中,導電覆蓋件材料112亦可沿著第二間隔件83及第一間隔件81的頂部表面在CESL94的相對側表面間延伸。
在第23G圖中所例示之實施例中,省略抗反應層104。在第一導電材料102其中為足夠的厚度的實施例中,可省略抗反應層104,第一導電材料102是由具有相對低氧化電位之材料所形成,或其他未具有抗反應層104的閾值電壓為足夠地大。第23H圖例示第20C及20D圖的實施例,其中抗反應層104及第一導電材料102為在第二間隔件83的相對側表面間延伸之直線。如第23H圖中所例示,第一導電材料102、抗反應層104、及第二導電材料108可具有彼此相等之寬度。在第23G及23H圖的實施例中,導電覆蓋件材料112可沿著閘極介電層100及第二導電材料108的頂部表面在第二間隔件83的相對側面間延伸。
在第24A及24B圖中,在保護層97、第一間隔件81、第二間隔件83、CESL94、及填充第三凹陷110的導電覆蓋件材料112之上沉積第二層間介電質(interlayer dielectric;ILD)114。第24A及24B圖例示n型區50N;然而,亦可在p型區50P之上形成第二ILD114。在一些實施例中,第二ILD114係藉由FCVD所形成之可流動膜。在一些實施例中,由諸如PSG、BSG、BPSG、USG、或類似者之介電材料,形成第二ILD114,且可藉由任何合適的方法,諸如CVD、PECVD、或類似方法,沉積第二ILD114。在沉積第二ILD114之後,平坦化第二ILD114並去除保護層97。可藉由諸如CMP之製程平坦化第二ILD114。可去除被設置在第一 ILD96及CESL94上方之第二ILD114的部分,且在平坦化之後,第一ILD96及CESL94的頂部表面可與第二ILD114的頂部表面齊平。平坦化製程可進一步去除保護層97。
在第25A及25B圖中,蝕刻第二ILD114、第一ILD96、及CESL94以形成第四凹陷116,而暴露磊晶源極/汲極區92及/或導電覆蓋件材料112的表面。第25A及25B圖例示n型區50N;然而,亦可在p型區50P中形成第四凹陷116。可使用各向異性蝕刻製程,諸如RIE、NBE、或類似製程,藉由蝕刻製程,形成第四凹陷116。在一些實施例中,可使用第一蝕刻製程將第四凹陷116蝕刻通過第二ILD114及第一ILD96,接著可使用第二蝕刻製程將第四凹陷116蝕刻通過CESL94。可在第一ILD96、CESL94、及第二ILD114之上形成並圖案化遮罩,諸如光抗蝕劑,以遮蔽第一ILD96、CESL94、及第二ILD114的部分免受第一蝕刻製程及第二蝕刻製程的影響。在一些實施例中,蝕刻製程可過度蝕刻,且因而,第四凹陷116延伸至磊晶源極/汲極區92及/或導電覆蓋件材料112中,且第四凹陷116的底部可與磊晶源極/汲極區92及/或導電覆蓋件材料112(例如,在相同的水平處,或與基材50具有相同的距離)齊平,或比磊晶源極/汲極區及/或導電覆蓋件材料更低(例如,更靠近基材50)。儘管第25B圖例示第四凹陷116在相同橫截面中暴露磊晶源極/汲極區92及閘極結構,在一些實施例中,可將磊晶源 極/汲極區92及閘極結構暴露在不同橫截面中,從而減少隨後所形成的觸點短路的風險。在形成第四凹陷116之後,在磊晶源極/汲極區92之上形成矽化物區118。在一些實施例中,藉由首先沉積能與下層磊晶源極/汲極區92(例如,矽、矽鍺、鍺、或類似者)之半導體材料反應之金屬(並未另外例示)形成矽化物區118,以在磊晶源極/汲極區92的暴露部分之上形成矽化物或鍺化物區,諸如鎳、鈷、鈦、鉭、鉑、鎢、其他貴金屬、其他耐熔金屬、稀土金屬、或其合金,接著,進行熱退火製程以形成矽化物區118。接著,例如,藉由蝕刻製程去除沉積金屬的未反應部分。儘管將矽化物區118稱作矽化物區,矽化物區118亦可為鍺化物區或矽鍺化物區(例如,包括矽化物及鍺化物之區)。在實施例中,矽化物區118包括TiSi,且具有自約2奈米至約10奈米範圍之厚度。
在第26A及26B圖中,在第四凹陷116中形成源極/汲極觸點120及閘極觸點122。第26A及26B圖例示n型區50N;然而,亦可在p型區50P中形成源極/汲極觸點120及閘極觸點122。源極/汲極觸點120及閘極觸點122可各自包括一層或更多層,諸如阻擋層、擴散層、及填充材料。舉例而言,在一些實施例中,每個源極/汲極觸點120及閘極觸點122包含阻擋層及在阻擋層之上之導電材料。將源極/汲極觸點120及閘極觸點122各電性地耦合至下層的導電特徵(例如,導電覆蓋件材料112及/或矽化物區118)。將閘極觸點122電性地耦合至閘極 結構的導電覆蓋件材料112,且將源極/汲極觸點120電性地耦合至磊晶源極/汲極區92之上之矽化物區118。阻擋層可包含鈦、氮化鈦、鉭、氮化鉭、或類似者。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或類似者。可進行平坦化製程,諸如CMP以從CESL94、第一ILD96、及第二ILD114的表面去除多餘的材料,使得源極/汲極觸點120及閘極觸點122的頂部表面與CESL94、第一ILD 96、及第二ILD114的頂部表面齊平。
實施例可實現優點。舉例而言,在第一導電材料102之上可包含抗反應層104,以防止第一導電材料102的氧化並提升包含抗反應層104的元件的閾值電壓。接著第二導電材料108可覆蓋於抗反應層104的表面,而提供在其上可選擇性地沉積導電覆蓋件材料112之材料。接著可使用導電覆蓋件材料112以減少閘極電阻增加的閾值電壓及減少的閘極電阻可改善包含相同抗反應層104及/或導電覆蓋件材料112之半導體元件的性能。
根據本揭露的一些實施例,半導體元件包含在半導體基材之上之閘極結構,閘極結構包含高k值介電層;在高k值介電層上之n型功函數層;在n型功函數層上之抗反應層,抗反應層包含介電材料;在抗反應層之上之p型功函數層,p型功函數層覆蓋抗反應層的頂部表面;及在p型功函數層之上之導電覆蓋件層。在實施例中,p型功函數層的截面視圖為T形狀。在實施例中,抗反應層包含矽。在實施例中,導電覆蓋件層包含鎢。在實施例中,高k值 介電層的頂部表面與p型功函數層的頂部表面齊平。在實施例中,半導體元件進一步包含與閘極結構毗鄰之閘極間隔件,導電覆蓋件層在閘極間隔件的相對側表面間延伸,且閘極間隔件頂部表面與導電覆蓋件層的頂部表面齊平。在實施例中,半導體元件進一步包含與閘極結構毗鄰之閘極間隔件,其中p型功函數層的頂部表面與高k值介電層的頂部表面及閘極間隔件的頂部表面齊平。
根據本揭露的另一些實施例,半導體元件包含在n型區的第一通道區;在p型區中之第二通道區;在第一通道區之上之第一閘極堆疊,第一閘極堆疊在第一通道區之上包含第一閘極介電層;在第一閘極介電層之上並與之接觸之n型金屬層,此n型金屬層包含鋁;在n型金屬層之上之介電層;在n型金屬層及介電層之上之第一p型金屬層;在第一p型金屬層之上之第一金屬覆蓋件層;在第二通道區之上之第二閘極堆疊,第二閘極堆疊在第二通道區之上包含第二閘極介電層;在第二閘極介電層之上並與第二閘極介電層接觸之第二p型金屬層;在第二p型金屬層之上之第二金屬覆蓋件層。在實施例中,n型金屬層、介電層、及第一p型金屬層的結合高度等於第二p型金屬層的高度。在實施例中,介電層及第一p型金屬層與第一閘極介電層接觸。在實施例中,介電層包含矽。在實施例中,第一金屬覆蓋件層及第二金屬覆蓋件層包含氯。在實施例中,第一p型金屬層的頂部表面與第二p型金屬層的頂部表面齊平,且其中第二p型金屬層的底部表面在第一p型 金屬層的底部表面之下方。在實施例中,半導體元件進一步包含沿著第一閘極堆疊的側壁延伸之第一閘極間隔件;及沿著第二閘極堆疊的側壁延伸之第二閘極間隔件,其中第二閘極間隔件的頂部表面與第二金屬覆蓋件層的頂部表面、第一閘極間隔件的頂部表面、及第一金屬覆蓋件層的頂部表面齊平。
根據本揭露的另一些實施例,一種半導體元件的形成方法包含在半導體基材之上形成閘極堆疊,形成此閘極堆疊包含在半導體基材之上沉積n型功函數層;在n型功函數層之上沉積介電層;在介電層之上方形成第一遮罩層;回蝕n型功函數層及介電層;在n型功函數層及介電層之上沉積p型功函數層;及在p型功函數層之上選擇性地沉積金屬覆蓋件層。在實施例中,藉由使用氯化鎢作為前驅物之原子層沉積,沉積金屬覆蓋件層。在實施例中,使用第一遮罩層作為遮罩回蝕刻n型功函數層及介電層,且在沉積p型功函數層之前去除第一遮罩層。在實施例中,此方法進一步包含回蝕此介電層以暴露n型功函數層,其中將p型功函數層沉積為與n型功函數層及介電層接觸。在實施例中,此方法進一步包含形成毗鄰犧牲閘極堆疊之閘極間隔件層;去除犧牲閘極堆疊以形成第一開口,其中在第一開口中形成閘極堆疊;平坦化閘極間隔件及p型功函數層;及在將閘極間隔件及p型功函數層平坦化之後,回蝕p型功函數層。在實施例中,此方法進一步包含回蝕閘極間隔件,其中在閘極間隔件的相對側表面間沉積金屬覆 蓋件層。
上述概述數種實施例的特徵,以便熟習此項技藝者可更瞭解本揭露內容的態樣。熟習此項技藝者應當理解,熟習此項技藝者可輕易地使用本揭露內容作為設計或修改其他製程及結構之基礎,以實現本文中所介紹之實施例的相同目的及/或達成相同優點。熟習此項技藝者亦應當認知,此均等構造不脫離本揭露內容的精神及範圍,且在不脫離本揭露內容之精神及範圍之情況下,熟習此項技藝者可在本文中進行各種改變、替換、及變更。
50:基材
50N:n型區
54A,54B,54C:第二奈米結構
81:第一間隔件
83:第二間隔件
90:第一內部間隔件
92:磊晶源極/汲極區
94:CESL
96:第一ILD
100:閘極介電層
102:第一導電材料
104:抗反應層
108:第二導電材料
112:導電覆蓋件材料
114:第二ILD
118:矽化物區
120:源極/汲極觸點
122:閘極觸點

Claims (10)

  1. 一種半導體元件,包括:一半導體基材之上之一閘極結構,該閘極結構包括:一高k值介電層;在該高k值介電層之上之一n型功函數層;在該n型功函數層之上之一抗反應層,該抗反應層為包括矽的一介電材料;在該抗反應層之上之一p型功函數層,該p型功函數層覆蓋該抗反應層的頂部表面;及在該p型功函數層之上之一導電覆蓋件層。
  2. 如請求項1所述之半導體元件,其中該p型功函數層的一橫截面視圖為T形狀。
  3. 如請求項1所述之半導體元件,進一步包括與該閘極結構毗鄰之複數個閘極間隔件,其中該導電覆蓋件層在該些閘極間隔件的相對側表面間延伸,且其中該些閘極間隔件頂部表面與該導電覆蓋件層的頂部表面齊平。
  4. 如請求項1所述之半導體元件,進一步包括與該閘極結構毗鄰之複數個閘極間隔件,其中該p型功函數層的頂部表面與該高k值介電層的頂部表面及該些閘極間隔件的頂部表面齊平。
  5. 一種半導體元件,包括:一n型區中之一第一通道區;一p型區中之一第二通道區;在該第一通道區之上之一第一閘極堆疊層,該第一閘極堆疊層包括:在該第一通道區之上之一第一閘極介電層;在該第一閘極介電層之上並與該第一閘極介電層接觸之一n型金屬層,該n型金屬層包括鋁;在該n型金屬層之上之一介電層;在該n型金屬層及該介電層之上之一第一p型金屬層;及在該第一p型金屬層之上之一第一金屬覆蓋件層;及在該第二通道區之上之一第二閘極堆疊,該第二閘極堆疊包括:在該第二通道區之上之一第二閘極介電層;在該第二閘極介電層之上並與該第二閘極介電層接觸之一第二p型金屬層;及在該第二p型金屬層之上之一第二金屬覆蓋件層。
  6. 如請求項5所述之半導體元件,其中該n型金屬層、該介電層、及該第一p型金屬層的一結合高度等於該第二p型金屬層的一高度。
  7. 如請求項5所述之半導體元件,其中該介電 層及該第一p型金屬層與該第一閘極介電層接觸。
  8. 如請求項5所述之半導體元件,其中該第一金屬覆蓋件層及該第二金屬覆蓋件層包括氯。
  9. 如請求項5所述之半導體元件,其中該第一p型金屬層的頂部表面與該第二p型金屬層的頂部表面齊平,且其中該第二p型金屬層的底部表面在該第一p型金屬層的底部表面之下方。
  10. 一種半導體元件的形成方法,包括以下步驟:在一半導體基材之上形成一閘極堆疊,其中形成該閘極堆疊之步驟包括以下步驟:在該半導體基材之上沉積一n型功函數層;在該n型功函數層之上沉積一介電層;在該介電層之上方形成一第一遮罩層;回蝕該n型功函數層及該介電層;在該n型功函數層及該介電層之上沉積一p型功函數層;及在該p型功函數層之上選擇性地沉積一金屬覆蓋件層。
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