TWI762533B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TWI762533B
TWI762533B TW106142841A TW106142841A TWI762533B TW I762533 B TWI762533 B TW I762533B TW 106142841 A TW106142841 A TW 106142841A TW 106142841 A TW106142841 A TW 106142841A TW I762533 B TWI762533 B TW I762533B
Authority
TW
Taiwan
Prior art keywords
electrode
semiconductor device
load
ball portion
manufacturing
Prior art date
Application number
TW106142841A
Other languages
English (en)
Other versions
TW201836106A (zh
Inventor
松原優子
Original Assignee
日商瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW201836106A publication Critical patent/TW201836106A/zh
Application granted granted Critical
Publication of TWI762533B publication Critical patent/TWI762533B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78343Means for applying energy, e.g. heating means by means of pressure by ultrasonic vibrations
    • H01L2224/78353Ultrasonic horns
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83193Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8501Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85012Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8503Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85203Thermocompression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • H01L2224/85206Direction of oscillation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

[課題] 提高半導體裝置的可靠性。 [解決手段] 一實施型態之半導體裝置的製造方法,包含以下步驟:一邊將接觸於半導體晶片的第1電極上的第1接線的球部以負載M3進行推壓,一邊在上述球部上施加超音波的活性化步驟ST5。並且,此半導體裝置之製造方法尚包含以下步驟:在上述第1步驟之後,一邊將上述球部以較負載M3大的負載M4進行推壓,一邊在上述球部上施加上述超音波來將上述球部與上述第1電極相接合的主接合步驟ST 6。

Description

半導體裝置之製造方法
本發明係關於半導體裝置的製造技術,例如關於能有效地應用在包含在半導體晶片的電極接線墊上連接金屬接線的步驟之半導體裝置的製造方法的技術。
在日本特開平2-297949號公報(專利文獻1)中,記載了在半導體晶片的電極接線墊上連接金屬接線的步驟中,在接合工具上施加負載以及超音波的打線接合方法。
另外,在日本特開平7-58142號公報(專利文獻2)中,記載著在進行熱壓接合方式的打線接合時,施加超音波震動的打線接合裝置。 [先行技術文獻] [專利文獻]
[專利文獻1]日本特開平2-297949號公報 [專利文獻2]日本特開平7-58142號公報
[發明所欲解決之問題]
用來將半導體裝置的外部端子與半導體晶片的電極接線墊進行電性連接的方法中,包含在電極接線墊上以接線來連接的方法。用來連接電極接線墊跟接線的方法,包含在接線的前端上形成球部後,將球部壓接於電極接線墊上的球形接合方式。以球形接合方式來連接接線與電極接線墊時,會在半導體晶片的構成元件中,位於電極接線墊四周的元件上施加應力。因此,要減少對電極接線墊本身以及在電極接線墊四周的元件的損害,從提高可靠性的觀點來看,將球部進行壓接時,需要能夠減少施加在電極接線墊上的應力的技術。
至於其他的問題以及新的特徴,應該能夠從本詳細說明書的描述以及附圖中來了解。 [解決問題之方式]
一實施型態之半導體裝置的製造方法包含以下步驟:第1步驟,一邊將與半導體晶片的第1電極相接觸之第1接線的球部以第1負載進行推壓,一邊在上述球部上施加超音波。此半導體裝置之製造方法尚包含以下步驟:在上述第1步驟之後,一邊以較上述第1負載大的第2負載推壓上述球部,一邊在上述球部上施加上述超音波來將上述球部與上述第1電極加以接合的步驟。 [發明之效果]
依據上述一實施型態可以提高半導體裝置的可靠性。
(本專利申請之記載方式,基本的用詞跟用法的說明) 在本專利申請中,實施型態的記載會視需要將其分成多個段落以便說明,但是除非有特別標示並非如此情況以外,這些說明並非是相互獨立的,不管其記載順序為何,在單一例子的各個部分中,一部分可以是其他部分的詳細,或者是一部分或者全部的變化例子等。原則上省略對相同部分的重複說明。而且,實施型態中的各個構成要素並非都是必須的,除非有特別說明並非如此情況,或者在理論上會被限定在該數目的情況,以及在說明中明顯並非如此情況。
同樣地在實施型態等的記載中,關於材料,組成等,當說明「由A來構成X」等時,除非有特別說明並非如此情況以及在說明中很明顯並非如此情況以外,並不排除包含A以外的要素的情況。舉例來說,當在說明成分時,指的是「包含以A為主要成分的X」的意思。比如說,當說明「矽構件」等時,並不僅限定在單純的矽上,當然也包含矽鍺合金以及其他以矽為主要成分的多元合金,以及包含其他添加物等構件。此外,當在說明鍍金,銅層,鍍鎳等時,除非有特別說明並非如此情況以外,指的並不僅是純粹的物質,也包含各種以金,銅,鎳等為主要成分的構件。
此外,當說到特定的數值與數量時,除非有特別說明並非如此情況以外,或者在理論上會被限定在該數目的情況以及在說明的脈絡中明顯並非此種情況以外,也可以是超過該特定數値的數値,或者是小於該特定的數値。
此外,在實施型態的各個圖中,同一個或者是相同的部分會以同一個或類似的記號或參考號碼來標示,原則上不會重複地說明。
在附圖中,有時為了避免過於複雜或者很明顯並非空白時,即使是剖面有時也會省略影線等。與此相關連的是,當在說明中是很明顯的情況時,即使在平面上是封閉的孔,有時也會省略掉其背景的輪廓線。即使並非是剖面,有時為了清楚地說明並非是空隙,或者為了清楚地說明區域的邊界,有時會加上影線或點圖。
<半導體裝置> 首先,以圖1~圖4來說明本實施型態的半導體裝置PKG1的構成概要。圖1是本實施型態的半導體裝置的俯視圖。圖2是沿著圖1的A-A線的剖面圖。圖3是以圖1中所顯示的密封體被透視後的狀態來說明半導體裝置的内部構造之透視平面圖。
以下的實施型態中所說明的技術,可以廣泛地應用於在半導體晶片表面上露出的電極接線墊上連接金屬接線的半導體裝置。在本實施型態中,以接線來連接半導體晶片的電極接線墊的半導體裝置的一個例子,是以導線架型的半導體裝置為例子來說明。在導線架型的半導體裝置的情況,搭載在導線架的晶粒墊上的半導體晶片是與配置在晶粒墊周圍的複數導線分別透過接線來進行電性連接。
如圖1~圖3中所顯示,半導體裝置PKG1包含:半導體晶片CP(參考圖2,圖3);複數導線(端子,外部端子)LD,即配置在半導體晶片CP周圍的外部端子;及複數接線BW(參考圖2,圖3),即將半導體晶片CP與複數導線LD進行電性連接的導電性構件。半導體晶片CP及複數接線BW是被密封在密封體(樹脂體)MR中。 複數導線LD各自的內部導線部ILD(參考圖2,圖3)是被密封在密封體MR中,複數導線LD各自的外部導線部OLD則是露在密封體MR外面。
如圖1中所示,半導體裝置PKG1中的密封體MR的俯視形狀是成四角形。密封體MR包含:頂面MRt;底面(背面,被安裝面)MRb(參考圖2),位於頂面MRt的相反側;及複數(圖1中有四個)側面MRs,位於頂面MRt與底面MRb之間。
密封體MR俯視時包含:沿著X方向的邊(主邊)S1;沿著與X方向交叉(直角)的Y方向上延伸的邊(主邊)S2;與邊S1相對的邊(主邊)S3;及與邊S2相對的邊(主邊)S4。密封體MR所包含的4個側面MRs沿著密封體MR的各個邊來配置。
在半導體裝置PKG1上,沿著俯視形狀為四角形的密封體MR的四個邊(主邊) S1,S2,S3,以及S4,分別配置有複數導線LD。複數導線LD是由金屬所構成,在本實施型態中是以例如銅(Cu)為主要成分的金屬構件。如本實施型態,沿著密封體MR的四個邊來分別配置複數導線LD的半導體封裝被稱為QFP(Quad Flat Pa ckage)。在此省略圖示,在密封體MR所有的四個邊中,沿著相對著的兩個邊來排列複數導線LD,而在其他的兩個邊上沒有排列導線LD的半導體封裝被稱為S OP(Small Outline Package)。本實施型態是以應用在QFP的半導體裝置PKG1上的實施態様來做說明,但是也可以應用在其變化例之SOP的半導體裝置上。
如圖2所示,複數導線LD的外部導線部OLD,在密封體MR的側面MRs上,朝向密封體MR的外側伸出。在QFP與SOP的情況,外部導線部OLD是從密封體MR的側面MRs來伸出,朝向安裝面形成彎曲的形狀。在此省略圖示,半導體裝置PKG1的一變化例,也有複數導線LD是分別從密封體MR的底面MRb露出的半導體封裝。導線LD從密封體MR的底面MRb露出的半導體封裝包含QFN(Quad Fl at Non-leaded package)與SON(Small Outline Non-leaded package)等。
在複數導線LD的外部導線部OLD的露出面上,例如以銅為主要成分的基材的表面上,形成有金屬膜(外部電鍍膜)MC。金屬膜MC是由例如焊接材等,比基材的銅對焊接材具有較好的潤濕性的金屬材料所構成,是覆蓋在基材即銅構件的表面上的金屬膜。藉著在半導體裝置PKG1的外部端子之導線LD的外部導線O LD上形成金屬膜MC,可以較容易將半導體裝置PKG1安裝在圖中未標示的安裝基板上。詳細來說,將外部導線部OLD與安裝基板的端子(省略圖示)分別連接時, 外部導線部OLD是透過焊接材等具導電性的連接材來與端子連接。此時,當外部導線部OLD被金屬膜MC所覆蓋時,可以改善與上述焊接材的潤濕性。藉此,因為複數導線LD與焊接材的接合面積會增加,可以提高複數導線LD與安裝基板端的端子的接合強度。
在圖2所示的例子的說明中,在導線LD的外部導線部OLD的露出面上,作為焊接膜的金屬膜MC是以電鍍法來形成。金屬膜MC有許多種變化例。例如,金屬膜MC也可以是以鎳(Ni)為主要成分之金屬膜跟以鈀(Pd)為主要成分的金屬膜的積層膜。或者,例如也可以在以鈀為主要成分之金屬膜的表面上進一步疊上以金(Au)為主要成分之金屬膜。當金屬膜MC是以焊接材以外的材料構成時,也可以將其覆蓋在複數導線LD的內部導線部ILD以及外部導線部OLD的表面來形成金屬膜MC。
如圖2及圖3中所示,在密封體MR的内部密封有半導體晶片CP。如圖3所示,半導體晶片CP俯視時是成四角形,其包含:表面(頂面,主面)CPt;跟表面CPt相對的背面CPb(參考圖2);及側面CPs,在半導體晶片CP的厚度方向的剖面圖上, 位於表面CPt與背面CPb之間。在半導體晶片CP的表面CPt上,沿著構成表面CPt的外縁的4個邊分別配置有複數接線墊(接合接線墊)PD。此外,半導體晶片CP(詳細來說,半導體基板)是由例如矽(Si)所構成。在此省略圖示,在半導體晶片CP的主面(詳細來說,在半導體晶片CP的半導體基板的頂面的半導體元件形成區域)上,形成有複數半導體元件(回路元件)。複數接線墊PD是透過半導體晶片CP的内部(詳細來說,在表面CPt與圖中未標示的半導體元件形成區域之間)的配線層中所形成的導線(省略圖示)來跟此半導體元件進行電性連接。也就是說,複數接線墊PD是與半導體晶片CP上所形成的電路進行電性連接。
半導體晶片CP的表面CPt上形成有絕緣膜,其覆蓋著半導體晶片CP基板以及導線。複數接線墊PD的表面分別是在絕緣膜上形成的開口部,從絕緣膜中露出來。此接線墊PD是由金屬所構成,例如在本實施型態中是以鋁(Al)來構成。
半導體晶片CP是被安置在搭載晶片的晶粒墊DP上。如圖3所示地,半導體裝置PKG1從俯視圖來看,在密封體MR的四個邊S1,S2,S3,及S4之間配置有搭載半導體晶片CP的晶片搭載部之晶粒墊(晶片搭載部)DP,半導體晶片CP是被搭載在晶粒墊DP的頂面(表面,主面,晶片搭載面)DPt上。晶粒墊DP的頂面DPt,是由面積較半導體晶片CP的表面積更大的四角形所形成。但是,晶粒墊DP作為支持半導體晶片CP的材料,其形狀以及大小,除了圖3所示的例子以外,也可以有各種變化例。例如,晶粒墊DP的俯視形狀也可以是圓形。或者,例如晶粒墊DP的平面面積也可以比半導體晶片CP的表面CPt小。在半導體裝置PKG1中,晶粒墊DP是被密封在密封體MR中。在此省略圖示,半導體裝置PKG1的一變化例是,晶粒墊DP的底面也可以在密封體MR的底面MRb,從密封體MR露出來。
如圖2所示,半導體晶片CP的背面CPb是與晶粒墊DP的頂面DPt成相對的狀態,透過晶粒接合材DB被搭載在晶粒墊DP上。也就是說,將形成有複數接線墊PD的表面(主面)CPt的相反面(背面CPb)與晶片搭載面(頂面DPt)相對,以所謂面向上的安裝方式來搭載。晶粒接合材DB是對半導體晶片CP進行晶粒接合時的黏接材,例如在環氧樹脂類的熱硬化性樹脂中包含複數導電性粒子(例如銀粒子)之具導電性的樹脂接合材或焊接材。
在半導體晶片CP的周圍(也就是晶粒墊DP的周圍)配置有複數導線LD。在半導體晶片CP的表面CPt上露出的複數接線墊(電極,電極接線墊)PD,分別與位於密封體MR的内部之複數導線LD的內部導線部ILD,透過複數接線(導電性構件) BW來進行電性連接。接線BW的一端部(後面所述圖14中所示的球部BWb)是與接線墊PD相連接,另一端部則是與內部導線部ILD的一部分(打線接合區域)相連接。
本實施型態的接線BW是由例如銅(Cu)所構成。一般來說,與半導體晶片的電極接線墊相連接的接線多是以金來構成,有時為了降低材料的成本,或者是為了降低接線所形成的傳輸路徑上的阻抗成分,會用金以外的材料來構成。例如,在本實施型態中,以銅來構成接線BW可以降低材料成本。
使用比金具有更高導電率的銅來構成接線BW可以降低接線BW所形成的傳輸路徑上的阻抗成分。相對於本實施型態的一變化例,可以在銅所構成的基板的表面上覆蓋以鈀(Pd)所構成的金屬膜。這可以進一步加強接線BW與接線墊PD的接合強度。
如圖3中所示,在晶粒墊DP的周圍上配置有複數懸吊導線HL。懸吊導線HL在半導體裝置PKG1的製造步驟中,是用來將晶粒墊DP支持於導線架的支持部(框部)上的材料。
在本實施型態中,晶粒墊DP的頂面DPt是與導線LD的內部導線部ILD的頂面配置在不同的高度。在圖2所示的例子中,晶粒墊DP的頂面DPt被配置在較內部導線部ILD的頂面LDt的位置低的位置上。因此,在圖3所示的複數懸吊導線HL上,為了使晶粒墊DP的頂面DPt的高度與導線LD的內部導線部ILD的頂面LDt(參考圖2)的高度不同,分別設置有彎曲的偏移部(在本實施型態的例子中是朝下偏移部)OSP。
<半導體晶片> 接著說明圖2及圖3中所示的半導體晶片。圖4是圖3中所示的半導體晶片的俯視圖。圖5是沿著圖4的A-A線的放大剖面圖。圖6是將圖5的A部進一步放大後的放大剖面圖。
圖4~圖6是說明在圖3所示的接線墊PD上連接上接線BW前的狀態。圖6是說明配線部SDL的例子,在形成接線墊PD的層與半導體基板SS之間,有著7層配線層DL的例子。但是,配線層的積層數並不僅限定在7層,也可以是例如6層以下,或者8層以上等各種變化例。在圖6所示的例子中,在半導體基板SS的頂面SSt所形成的複數半導體元件Q1的例子中,記載了MOSFET(Metal Oxide Semiconductor Field Effect Transistor)的構造。但是,半導體元件Q1的構造除了MOSFET以外也有各種的變化例。
圖4及圖6中所示的半導體晶片CP的表面(頂面,主面)CPt上,形成有:絕緣膜(保護膜,保護絕緣膜)PV;及接線墊PD,在絕緣膜PV上形成的開口部PVk從絕緣膜PV露出來。在絕緣膜PV上形成有多數的開口部PVk,在多數的開口部PVk分別露出接線墊PD。換言之,在半導體晶片CP的表面CPt上有著從絕緣膜PV露出的複數接線墊PD。
半導體晶片CP的表面CPt俯視時是成四角形,包含:沿X方向延伸的邊CPs1; 沿著與X方向成交叉(垂直交叉)的Y方向來延伸的邊CPs2;與邊CPs1相對的邊CP s3;及與邊CPs2相對的邊CPs4。如圖3所示地,在本實施型態中,半導體晶片CP的邊CPs1是沿著密封體MR的邊S1來配置,半導體晶片CP的邊CPs2是沿著密封體MR的邊S2來配置。半導體晶片CP的邊CPs3是沿著密封體MR的邊S3來配置,半導體晶片CP的邊CPs4是沿著密封體MR的邊S4來配置。
在絕緣膜PV上所形成的複數開口部PVk也分別具有多數邊。在圖4的例子中,開口部PVk的開口形狀包含:沿X方向延伸的邊Pks1;沿著與X方向交叉(垂直交叉)的Y方向延伸的邊Pks2;與邊Pks1相對的邊Pks3;及與邊Pks2相對的邊Pks 4。在本實施型態中,開口部PVk的邊Pks1是沿著半導體晶片CP的邊CPs1來配置, 開口部PVk的邊Pks2是沿著半導體晶片CP的邊CPs2來配置。開口部PVk的邊Pks3是沿著半導體晶片CP的邊CPs3來配置,開口部PVk的邊Pks4是沿著半導體晶片CP的邊CPs4來配置。
半導體晶片CP中具備有半導體基板SS,該半導體基板SS包含:形成有複數半導體元件Q1(參考圖6)的頂面(半導體元件形成面)SSt;及頂面SSt的相反面的底面(背面)SSb(參考圖5)。半導體基板SS是半導體晶片CP的基材,例如是以矽(Silic on;Si)為主要成分所構成。半導體晶片CP包含了在半導體基板SS的頂面SSt上所形成配線部SDL(參考圖5,圖6)。
在圖5所示的例子中,半導體晶片CP的背面(底面)CPb與半導體基板SS的底面SSb為相同的面。換言之,在圖5所示的例子中,半導體基板SS的底面SSb便是半導體晶片CP的背面CPb。半導體晶片CP的表面(主面,頂面)CPt是由:覆蓋著配線部SDL的最頂層之絕緣膜PV(參考圖4及圖6)的頂面PVt;及從絕緣膜PV露出的多數的接線墊PD(參考圖4及圖6)的露出面所構成。
在圖6中放大來說明,配線部SDL具有積層的複數配線層DL。藉由配線部SD L,複數半導體元件Q1與複數接線墊PD透過積層的複數配線層DL來進行電性連接。複數接線墊PD是在覆蓋著配線部SDL的最頂層的絕緣層IML1上形成。進一步地說,此接線墊PD是透過在絕緣層IML1上的開口部内的通孔配線(構成接線墊PD的導線的一部分)來跟最頂層的配線層DL進行電性連接。
複數配線層DL分別具有複數導體圖案(導線)CBP,以及將複數導體圖案CBP予以電性絕緣的絕緣層IML。導體圖案CBP被埋在絕緣層IML上所形成的開口部内。各個配線層DL的導體圖案CBP與形成該導體圖案CBP的配線層DL相隣接的配線層DL的導體圖案CBP電性連接。例如,從半導體基板SS的頂面SSt算起來,在第3層的配線層DL上所形成的導體圖案CBP,與在第2層的配線層DL上所形成的導體圖案CBP,及在第4層的配線層DL所形成的導體圖案CBP分別電性連接。在第1層的配線層DL上所形成的導體圖案CBP,與半導體元件Q1的閘極,源極區域,以及汲極區域電性連接。在最頂層(圖6中的第7層)的配線層DL上所形成的導體圖案CBP與接線墊PD電性連接。經由配線部SDL來將複數配線層DL上所形成的導體圖案CBP互相電性連接,藉此來構成將半導體元件Q1與接線墊PD進行電性連接的導通路徑。
構成配線部SDL的材料雖不僅限定在以下的情況,但可用以下的例子來說明。絕緣層IML是以例如氧化矽(SiO2 )為主要成分來構成。在最頂層以外的配線層DL上所形成的複數導體圖案CBP是以例如銅(Cu)為主要成分來構成。最頂層的配線層DL與接線墊PD為相同的金屬材料,例如以鋁為主要成分的金屬材料來構成。接線墊PD隔著絕緣層IML1在最頂層的導體圖案CBP上來形成。換言之,在最頂層的配線層DL與接線墊PD之間,隔著絕緣層IML1。絕緣層IML1是覆蓋著最頂層的配線層DL的層。如圖6所示,絕緣層IML1介於接線墊PD與導體圖案CBP之間,在其一部分上形成開口部。接線墊PD與導體圖案CBP在此一開口部上密接在一起。在此一情況下,接線墊PD與導體圖案CBP之間流的電流,會經由接線墊PD與導體圖案CBP密接在一起的部分而流動。
複數接線墊PD及最頂層的配線層DL是被具有半導體晶片CP的表面CPt之絕緣膜PV所覆蓋。使用絕緣膜PV來覆蓋配線部SDL可以保護配線部SDL。絕緣膜P V是覆蓋著配線部SDL的膜,其具有:跟半導體基板SS的頂面SSt相對的底面(面)P Vb;及跟底面PVb相對的頂面(面)PVt。
如圖6中所示,由於絕緣膜PV是覆蓋著配線部SDL的膜,在絕緣膜PV的底面PVb與半導體基板SS的頂面SSt之間,隔著包含複數配線層DL的配線部SDL。
絕緣膜PV是由例如氧化矽(SiO2 ),氮化矽(SiN),氮氧化矽(SiON)或著是這些層的積層膜所構成。有時會在氧化矽,氮化矽,或氮氧化矽的膜上進一步覆蓋上聚醯亞胺(Polyimide)等樹脂膜。以圖4來說明最簡單的例子,是以單層的絕緣膜來構成絕緣膜PV,但是它的變化例是使用積層膜來構成絕緣膜PV。當使用積層膜來構成絕緣膜PV時,最底層(最接近配線層DL的層)的絕緣膜的底面相當於絕緣膜PV的底面PVb。當使用積層膜來構成絕緣膜PV時,最頂層(離配線層DL最遠的層)的絕緣膜的頂面相當於絕緣膜PV的頂面PVt。
半導體晶片CP的複數接線墊PD如圖6所示,是在絕緣膜PV與半導體基板SS之間形成,在半導體晶片CP的表面CPt上,從絕緣膜PV露出來。詳細地說,如圖6所示,在絕緣膜PV上,與接線墊PD在厚度方向(圖6的Z方向)相重疊的位置上, 形成有開口部PVk。開口部PVk是把絕緣膜PV的頂面PVt以及底面PVb,從一邊貫通到另一邊來形成。因此,複數接線墊PD在與絕緣膜PV上形成的複數開口部PVk重疊的位置上,從絕緣膜PV被露出來。圖6所示的例子中,接線墊PD中的一部分從絕緣膜PV露出。複數接線墊PD可以分別與圖2及圖3中所示的接線BW之類的導電性構件連接。換言之,可以將複數接線墊PD作為半導體晶片CP的外部端子來使用。接線墊PD在開口部PVk處從絕緣膜PV露出的面便是與接線BW相連接的接合面PDt。
但是,圖6所示的半導體晶片CP在半導體裝置PKG1(參考圖2)的製造步驟中, 或者在半導體裝置PKG1完成後,會被施加温度循環負載等各種熱應力。這時候, 金屬材料所構成的接線墊PD的線膨脹係數會大於覆蓋接線墊PD的一部分(周邊處)的絕緣膜PV,以及將接線BW(參考圖2)與接線墊PD一起密封的密封體MR(參考圖2)的線膨脹係數。因此,在接線墊PD的周圍,會因為線性膨脹係數的不同,會沿著接線墊PD的接合面PDt的延伸方向產生剪應力(與物體内部的某一個面成平行的方向上,滑動般地作用的應力)。上述的剪應力因為是沿著與接線墊PD的表面PDt成水平的方向來作用,應力大時有可能會成為半導體晶片CP的結構故障的原因。例如,上述剪應力過大可能會造成絕緣膜PV的一部分產生龜裂。
當沿著接線墊PD底層配置之最頂層的導體圖案CBP的延伸方向上發生上述剪應力時,有時會發生導體圖案CBP的位置因為應力而移動(滑動)的現象。
上述剪應力的大小除了金屬材料的線膨脹係數値以外,也會與金屬構件的體積成比例地變大。因此,減少接線墊PD的厚度(從接合面PDt到另一面的背面PDb的長度)可以降低上述剪應力的値。在本實施型態中,接線墊PD的厚度THpd小於接線墊PD上的絕緣膜PV的厚度THpv。例如,圖6中所示的絕緣膜PV的厚度THpv是1μm左右。另一方面,接線墊PD的厚度THpd是450nm~1μm左右。圖6所示的例子中,接線墊PD的厚度THpd比絕緣層IML1的厚度TH1小。絕緣層IML1的厚度TH1可以有各種的變化例,例如可以與接線墊PD的厚度THpd相同,也可以比厚度THpd來得薄。因此,藉著減少接線墊PD的厚度THpd可以降低在接線墊PD的延伸方向上所產生的上述剪應力的値。圖6中所示的接線墊PD的厚度TH pd便是後面所述的打線接合步驟中,與接線BW(參考圖2)連接前的接線墊PD的厚度。
在複數配線層DL上形成的導體圖案CBP之中,在最頂層形成的導體圖案CBP,比其他配線層DL上形成的導體圖案CBP更厚。因此,為了降低在最頂層的導體圖案CBP的延伸方向所產生的剪應力的値,最好能夠減少最頂層的導體圖案CBP的厚度(從頂面CBt及底面CBb的一面到另一面的長度)。例如圖6中所示的最頂層的導體圖案CBP的厚度THcb大約是450nm~1μm。藉由減少最頂層的導體圖案CBP的厚度THcb,可以減少在最頂層的導體圖案CBP的延伸方向上所產生的上述剪應力的値。
<半導體裝置之製造方法> 接著說明圖1中所示的半導體裝置PKG1的製造方法。本實施型態的半導體裝置PKG1是依據圖7中所示的組裝流程來製造。圖7是說明本實施型態的半導體裝置的組裝流程的說明圖。
<基材準備步驟> 在圖7所示的基材準備步驟中,準備圖8中所示的導線架(基板)LF。圖8是圖7所示的基材準備步驟中所準備的導線架的一部分之放大平面圖。
本步驟所準備的導線架LF,在框部LFb的内側具有複數元件形成部LFa。導線架LF是由金屬所構成,在本實施型態中是以例如銅(Cu)為主要成分的金屬所構成。
如圖7所示,本實施型態是在密封步驟之後進行電鍍的步驟,以在外部導線部OLD上形成圖2所示的金屬膜MC為例來加以說明。但是,其變化例是可以在基材準備步驟時,預先在以銅為主要成分的基材的表面上覆蓋上金屬膜MC。此時,導線架LF的露出面全部都會被金屬膜MC所覆蓋。
如圖8所示,在各個元件形成部LFa的中央部形成有作為晶片搭載部之晶粒墊DP。複數懸吊導線HL分別與晶粒墊DP相連接,並朝向元件形成部LFa的四角延伸來配置。晶粒墊DP藉由懸吊導線HL被導線架LF的框部LFb所支持。
在晶粒墊DP的周圍,複數懸吊導線HL之間分別形成有複數導線LD。複數導線LD分別與框部LFb相連接。在本實施型態的例子中,複數導線LD是被設置在晶粒墊DP的周圍,朝向四個方向來延伸。
此外,複數導線LD是透過聯結桿TB相互連接。聯結桿TB除了作為連接複數導線LD之連結構件的功能以外,在圖7中所示的密封步驟中,也具有抑制樹脂漏出的屏障構件的功能。
<半導體晶片準備步驟> 圖7所示的半導體晶片準備步驟是準備圖4~圖6中說明的半導體晶片CP。在本步驟中,例如在矽所構成的半導體晶圓(省略圖示)的主面側(圖6中所示的半導體基板SS的頂面SSt側)上,準備由複數半導體元件Q1(參考圖6)及將其作電性連接的配線層DL(參考圖6)所構成的半導體晶圓。在配線層DL的最頂層形成有複數接線墊PD(參考圖4)。
接著形成絕緣膜PV(參考圖6)來覆蓋形成有複數接線墊PD的最頂層的配線層DL。然後在絕緣膜PV上形成複數開口部PVk(參考圖4)來使得複數接線墊PD的至少一部分被露出來。形成上述半導體晶圓之後,沿著半導體晶圓的切割線將半導體晶圓切斷來得到複數個圖4中所示的半導體晶片CP。
本實施型態中是先說明了基材準備步驟之後才說明半導體晶片準備步驟,但是基材準備步驟與半導體晶片準備步驟,不管是哪個步驟先進行皆可,也可以同時來進行。晶粒接合步驟則是在基材準備步驟以及半導體晶片準備步驟的兩者都完成之後來實施。
<晶粒接合步驟> 如圖9所示地,圖7中所示的晶粒接合步驟(半導體晶片搭載步驟)是將半導體晶片CP搭載在晶粒墊DP上。圖9是沿著圖8的A-A線的剖面上,將半導體晶片搭載在導線架的晶粒墊後的放大剖面圖。
如圖9所示,半導體晶片CP包含:表面CPt,形成有複數接線墊PD;及背面CPb,位於表面CPt的相反面。在本步驟中,透過晶粒接合材DB來將半導體晶片CP與晶粒墊DP加以黏接固定。俯視時,圖9所示的例子是使晶粒墊DP的頂面DPt的一部分被半導體晶片CP覆蓋來搭載半導體晶片CP。晶粒接合材DB是將半導體晶片CP與晶粒墊DP加以黏接固定的黏接材,例如具有著硬化前為糊狀的性質。使用糊狀的黏接材來搭載半導體晶片CP時,是在搭載半導體晶片CP之前,在晶粒墊DP的晶片搭載面之頂面DPt上預先配置糊狀的黏接材。然後將半導體晶片CP壓在晶粒墊DP上,將糊狀的黏接材壓開。然後,例如將其加熱來使黏接材硬化以固定半導體晶片CP。但是,晶粒接合材DB並不僅限定在以上所述者,也可以使用例如被稱為DAF(Die Attach Film)之樹脂膜。這時,例如將兩面都具有黏接層的膠帶(膜狀材)之晶粒接合材DB預先黏在半導體晶片CP的背面CPb上,藉由膠帶來黏接半導體晶片CP。然後,例如將晶粒接合材DB中含有的熱硬化性樹脂成分進行熱硬化處理來固定半導體晶片CP。
在本實施型態的例子中,是將半導體晶片CP的背面CPb與晶粒墊DP的晶片搭載面的頂面DPt相對,以所謂的面向上封裝方式來搭載在晶粒墊DP上。
<打線接合步驟> 接著,在圖7中所示的打線接合步驟中,如圖10中所示,是將半導體晶片CP的表面CPt上形成的複數接線墊PD與配置在半導體晶片CP周圍的複數導線LD,分別藉由複數接線(導電性構件)BW來作電性連接。圖10是將圖9中所示的半導體晶片與複數導線以接線來進行電性連接後的狀態之放大剖面圖。
本步驟的詳細會在後面加以說明,在本步驟中是將例如以銅(Cu)等金屬材料所構成的接線BW的一端部(球部)與半導體晶片CP的接線墊PD相連接,將另一端部(固定部)與導線LD的內部導線部ILD相連接。藉此,半導體晶片CP的接線墊PD與導線LD將透過接線BW在電性上被連接。本實施型態中,是以半導體晶片CP的接線墊PD為第1接合端,以導線架LF的導線LD的頂面LDt為第2接合端,用所謂的正接合方式來連接接線BW。打線接合步驟會在後面詳細地說明。
<密封步驟> 接著,在圖7所示的密封步驟中,將圖10所示的半導體晶片CP,複數接線BW, 及複數導線LD的各個內部導線部ILD以樹脂來進行密封後形成圖11所示的密封體MR。圖11是將圖10中所示的半導體晶片經樹脂密封後的狀態的放大剖面圖。
在本步驟中,如圖11所示,在具有空洞MDc的成形模具MD内搭載導線架LF後的狀態,在空洞MDc形成的空間内加入樹脂後,將上述樹脂硬化後形成密封體(樹脂物體)MR。此種密封體MR的形成方法被稱為轉注成形方式。
俯視時,成形模具MD的空洞MDc是分別被配置在複數元件形成部LFa(圖8參考)中以聯結桿TB(參考圖8)所圍著的區域中。因此,密封體MR的主體部分會分別在各個元件形成部LFa的聯結桿TB所圍著的區域中被形成。從空洞MDc漏出來的樹脂的一部分會被聯結桿TB所阻擋。因此在複數導線LD中,位於聯結桿TB外側的外部導線部OLD並不會被樹脂所密封,而會從密封體MR露出來。在本步驟中,半導體晶片CP的全部,晶粒墊DP的全部,複數接線BW的全部,以及各個複數導線LD的一部分(內部導線部ILD)會被密封。
<電鍍步驟> 接著,在圖7所示的電鍍步驟中,將圖11中從密封體MR露出的複數導線LD的一部分(外部導線部OLD,露出面)以電鍍法來形成金屬膜MC(參考圖2)。在本步驟中,在導線LD的露出面上形成以例如焊材所構成的金屬膜MC。金屬膜MC可以使用電鍍法,將電解後的金屬離子在導線LD的露出面上析出。電鍍法的好處是能夠藉由控制形成金屬膜MC時的電流可以很容易地來控制金屬膜MC的膜質。電鍍法也具有能縮短形成金屬膜MC的時間的好處。
<導線切斷步驟> 接著,在圖7所示的導線切斷步驟中,如圖12所示地是將複數導線LD上的外部導線部OLD分別加以切斷,使得複數導線LD分別從導線架LF切開。在本實施型態中,將導線LD切斷之後形成複數導線LD,然後進行圖2中的彎曲加工。圖12是在圖11中所示的複數導線的露出面上形成金屬膜,將其分別切斷及成形後的狀態之放大平面圖。
在本步驟中,將連接複數導線LD的聯結桿TB加以切斷。並將複數導線LD分別從框部LFb切斷。這時,複數導線LD便成為互相分離的獨立材料。當複數導線LD被切離後,密封體MR以及複數導線LD便成為經由懸吊導線HL被框部LF b支持著的狀態。
本實施型態中的說明是在上述電鍍步驟之後將聯結桿TB切斷,但也可以先切斷聯結桿TB然後進行電鍍步驟,再將複數導線LD分別從框部LFb加以切離的順序。藉此可以在聯結桿TB的切斷面上形成金屬膜MC,來抑制聯結桿TB的切斷面因為氧化而變色。在導線LD從框部LFb切離之前進行電鍍步驟,可以抑制因為電鍍液而造成導線LD的變形。
複數導線LD及聯結桿TB是使用圖中未標示的切斷用的模具,以沖壓加工來加以切斷。切斷後的複數導線LD例如可以用圖中未標示之成形用的模具來進行沖壓加工來將複數導線LD的外部導線部OLD進行彎曲加工,以形成圖2中所示的形狀。
<切割步驟> 接著,在圖7所示的切割步驟中,將圖12中的複數懸吊導線HL分別加以切斷, 將複數元件形成部LFa分別加以分離成半導體封裝。在本步驟中將複數懸吊導線HL,以及殘留在密封體MR的角部的樹脂加以切斷,來得到圖1所示的半導體裝置PKG1(詳細來說,是檢查步驟前的檢查物)之半導體封裝。此切斷方法,例如可以跟上述導線成形步驟相同地,使用圖中未標示的切斷模具以沖壓加工來加以切斷。
在本步驟之後是進行外觀檢查,電性測試等必要的檢查與測試,合格後便成為圖1~圖3中所示的完成品半導體裝置PKG1。然後,半導體裝置PKG1可以被出貨,或著安裝在圖中未標示的安裝基板上。
<打線接合步驟的詳細> 接著詳細說明圖7所示的打線接合步驟。圖13是說明圖4的B部,在接線墊上打上接線後的狀態之放大平面圖。圖14則是沿著圖13的A-A線之放大剖面圖。
如圖10中所示,在本實施型態的打線接合步驟中,接線BW的一邊的端部與半導體晶片CP的接線墊PD相連接,接線BW的另一邊的端部則是與導線LD的內部導線部ILD相接合。將接線BW與接線墊PD連接的步驟中,將接線BW上所形成的球部推壓接合在接線墊PD上,也就是用所謂的球形接合方式來將接線BW與接線墊PD相連接。
後面會詳細來說明,如圖13及圖14中的例子所示,以球形接合方式來將接線BW的球部BWb與接線墊PD接合時,在球部BWb上施加超音波震動之類的高頻震動可以提高接合強度。「超音波」及「超音波震動」是指比人類的聽覺區域更高頻率的彈性波。在本專利申請中,將20kHz以上的高頻稱之為「超音波」或者「超音波震動」。另一方面,「震動」則是包含了超音波以外,波長不到20kHz的彈性波。當施加超音波震動時,例如圖14中所示地,在球部BWb與接線墊PD的接合面上會形成由構成接線BW的金屬與構成接線墊PD的金屬的合金層PDa(參考圖14)。若是在接合面PDt與球部BWb之間,存在著接線墊PD的氧化膜則會造成接合強度降低,或者成為電性降低的原因,所以最好能夠去除在接合面PDt的露出面上所形成的氧化膜(後面所述的磨砂動作)。
但是,依據本專利申請的發明人的研究,若是一邊進行磨砂動作一邊在球部BWb上施加超音波之類的高頻震動時,在接合面PDt與球部BWb的界面的一部分會形成合金層,其他部分則會被除去前的氧化膜所阻礙而不會形成合金層的狀態。當接合界面成為不平均的狀態時,已知應力會容易集中在特定的地方。尤其是如本實施型態一般地,當接線墊PD的厚度THpd(圖6參考)較薄時,已知上述的應力有可能會造成接線墊PD本身的損傷。
造成接線墊PD本身的損傷,或者接線墊PD的底層材料損傷的原因之一,是打線接合步驟時在接線墊PD上加了大的負載。但是依據本申請發明人的研究,接線墊PD本身的損傷,或者接線墊PD的底層材料損傷的主要原因,是因為上述接合面成為不平均狀態時所產生的應力。換言之,如果可以讓接線墊PD的接合面PDt與球部BWb的接觸面能夠在平均地活性化後的狀態下開始接合,便可以在接觸界面上形成良好的合金層PDa(參考圖14),並減少對接線墊PD本身或者接線墊PD的底層材料的損傷。
特別是如圖6所示地當接線墊PD的厚度THpd較薄時,由於上述的應力會使得接線墊PD容易發生例如龜裂等的損傷。即使是接線墊PD沒有發生損傷,有時在與接線墊PD的背面PDb相接的絕緣層IML1會發生龜裂等的損傷。當接線墊PD發生龜裂時,此龜裂有時會沿半導體基板SS的頂面SSt來延伸。
例如,當接線墊PD本身或者接線墊PD與導體圖案CBP之間的絕緣層IML1發生龜裂,且此一龜裂延伸到與其他的信號導線等相接時,因為此龜裂會成為漏電路徑的原因,有可能會成為半導體晶片CP的電性降低的原因。在與接線墊PD重疊的位置上,形成有跟接線墊PD連接到不同電極的導線時,當接線墊PD等發生損傷時便容易發生漏電流。
特別是像本實施型態,將銅(Cu)所構成的接線BW的球部BWb與鋁(Al)所構成的接線墊PD相接合時,接線BW的硬度比接線墊PD的硬度高。例如,以維克氏硬度來比較時,銅的硬度是46Hv,而鋁的硬度是25Hv。因此,當把較硬的材料接合到相對上柔軟的材料上時,如果柔軟的材料的被接合部的厚度薄時,在被接合部的周邊容易發生損傷。
另一方面,若是為了防止被接合部周邊的損傷,例如沒有進行上述磨砂動作時,會因為沒有完全去除接合界面上的氧化膜,而造成接合強度降低,或者電性降低的原因。或者例如為了防止被接合部周邊的損傷,在施加超音波震動時僅施加低的負載,會因為負載不足而成為接合強度降低的原因。特別是像本實施型態中,將銅(Cu)所構成的接線BW的球部BWb接合到以鋁(Al)所構成的接線墊PD上時,使得接合面PDt與球部BWb的界面全部成為均勻的狀態(適合形成合金層的活性化狀態)之後,一邊施加足夠大的負載(例如,0.15N(牛頓)左右)一邊施加超音波,較容易得到良好的接合狀態。後面會詳細來說明,在本實施型態中,在使得接合面PDt與球部BWb的界面全部成為均勻狀態的步驟中,包含進行磨砂動作的步驟(後面說明的圖17中所示的磨砂步驟ST4),以及在施加不會形成合金層的負載的狀態下來施加超音波的步驟(圖17中所示的活性化步驟ST5)。
如同本實施型態,當接線墊PD的厚度THpd(圖6參考)較薄時,特別是在進行球形接合時,需要能夠降低施加在被接合部的負載(應力),同時能提高接合強度的技術。以下使用圖面來依序來說明本實施型態的打線接合步驟。
圖15是說明圖7的打線接合步驟中使用的打線接合裝置與導線架間的位置關係之俯視圖。圖16是以模型來說明沿著圖15的A-A線的剖面之剖面圖。圖17是說明圖7的打線接合步驟之中,連接接線的球部與接線墊的步驟時,接合工具的高度,施加在球部上的負載,有無磨砂動作,及有無超音波震動的關係之時序圖。在圖17中,進行後面所述的磨砂動作的時間,及施加超音波的時間分別標示有斜影線。圖18~圖25分別是說明圖17的時序圖中在各個時間所實施的各個步驟的動作之放大平面圖或放大剖面圖。在上述圖14跟圖25中,雖然在球部BWb與接線墊PD之間標示有合金層PDa,該合金層PDa的厚度跟形狀可以有許多種變化例。
在本實施型態的打線接合步驟中,以圖15所示為例,在固定有導線架LF的底座STG的旁邊,配置有打線接合裝置WBD。導線架LF與打線接合裝置WBD是以圖15中所示的位置關係為例來配置。也就是說,打線接合裝置俯視時是使突出物USH沿著X方向延伸地來配置,導線架LF是與振盪器USG相對地配置在突出物USH的另一邊。藉此可以在接線BW的球部BWb(圖16參考)上施加沿著X方向震動的超音波US1。
打線接合裝置WBD包含圖16中所示的鋼嘴CAP,突出物USH,及用來支持包含振盪器USG的接合頭部的支持部SUP。支持部SUP可以沿著圖15所示的X-Y平面自由地移動,藉著移動支持部SUP與接合頭的位置,可以在導線架LF的複數接線墊PD上分別連接上接線BW。
在球形接合步驟中,施加在接線BW的球部BWb上的負載,是藉著將固定鋼嘴CAP的突出物USH的前端部分往下壓,透過鋼嘴CAP來傳達到球部BWb上。
如圖16所示地,本實施型態的打線接合步驟中包含在鋼嘴CAP的底端側突出來的接線BW的端部上形成球部BWb的步驟(圖17中所示的球部形成步驟ST 1)。球部BWb是藉由圖中未標示的電火炬放電而在接線BW的前端形成。球部形成步驟ST1是在圖17中的時間(時序)T0 時實施。
如圖18及圖19所示,打線接合步驟中包含將接線BW的球部BWb接觸在接線墊PD的接合面PDt上的步驟(圖17所示的球部接觸步驟ST2)。球部接觸步驟ST2是在圖17所示的時間(時序)T1 時實施。在此步驟是將保持在接合工具即鋼嘴CAP的前端之球部BWb的前端部分與接合面PDt接觸。
如圖20及圖21所示地,打線接合步驟包含在球部接觸步驟ST2之後,將接線BW的球部BWb朝向接合面PDt以負載M1(參考圖17)進行推壓,以及使球部BWb變形的步驟(圖17中所示的球部變形步驟ST3)。球部變形步驟ST3是在圖17中所示的時間T1 與時間(時序)T2 之間來實施。在球部變形步驟ST3中,藉由鋼嘴CAP在球部BWb上施加負載來將球部BWb朝向接線墊PD的厚度方向推壓。此時所加的負載M1,在圖17所示的時間T1 與時間(時序)T7 之間最大,例如大約0.8N(牛頓)。 此時,球部BWb及接線墊PD會被加熱。球部BWb被接線墊PD與鋼嘴CAP夾著,會隨著鋼嘴CAP的形狀來變形。如圖21所示地,球部BWb的一部分被壓在接線墊PD上,使得接線墊PD的一部分變形。此時,因為球部BWb的一部分被埋在接線墊PD中,使得在埋入的區域上構成接線墊PD的金屬材料的一部分會被排出到球部BWb的周圍。因此,如圖21所示的接線墊PD的接合面PDt,在與球部BWb密接區域的周圍的高度會成為比跟球部BWb接合的區域來的隆起的狀態。
在本實施型態中,施加高負載來進行球部變形步驟ST3的時間比圖17中所示的磨砂步驟ST4及施加超音波的時間短。進行球部變形步驟ST3的時間的長度(時間T2 -時間T1 )約為1msec(毫秒)左右。如此地,藉著在短時間內施加高負載,可以改善圖21中所示的球部BWb與接合面PDt接合的面的平坦性。
如圖17所示地,時間T1 與時間T2 之間,也就是在球部變形步驟ST3時,不會施加超音波,也不會實施後面所述的磨砂動作。因此,在球部變形步驟ST3時,即使施加比較大的負載也不容易在接線墊PD本身或者絕緣層IML1上發生損傷。
如圖22及圖23所示地,打線接合步驟包含在球部變形步驟ST3(參考圖17)之後,一邊以較負載M1(參考圖17)小的負載M2(參考圖17)來將接線BW的球部BWb推壓在接線墊PD上,一邊俯視時將球部BWb朝向包含X方向與Y方向的複數方向來移動的步驟(圖17中所示的磨砂步驟ST4)。
圖15及圖16所示的打線接合裝置WBD的支持部SUP,可以在圖15中所示的X-Y平面上自由地移動。藉著調整支持部SUP的移動量,可以一邊推壓圖25中所示的球部BWb,一邊做移動球部BWb與接線墊PD在平面上的相對位置關係的動作(在此稱之為磨砂動作)。以此磨砂動作在球部BWb上施加震動時,可以使用比較低的頻率(例如1Hz左右)來機械性地震動球部BWb。
如此地一邊推壓球部BWb一邊以低頻率來震動球部BWb,可以去除球部BW b與接線墊PD的接合面PDt間的界面上的金屬氧化膜。為了在球部BWb與接線墊PD間的接合面上安定地形成合金層PDa(參考圖14),最好除去上述的金屬氧化膜。因此,在磨砂步驟ST4中,最好能夠去除包含球部BWb與接線墊PD接觸部分的周邊區域的金屬氧化膜。
如以上所述,在本實施型態的情況,圖15及圖16中所示的打線接合裝置WBD的支持部SUP可以在圖15所示的X-Y平面上自由地移動。因此,磨砂步驟ST4(參考圖17)可以去除包含球部BWb與接線墊PD接觸部分(接觸界面)的周邊區域的金屬氧化膜。詳細來說,在圖15所示的X-Y平面上,打線接合裝置WBD的支持部SUP,當在X方向及Y方向上同時震動時,藉著調整X方向震動的周期跟振幅以及Y方向震動的周期跟振幅,可以使球部BWb在X-Y平面上的任意的方向上動作。例如以模型來說明圖22中的方向DR1,可以讓球部BWb以接線墊PD的中央為中心來進行畫圓的動作。換言之,藉著使支持部SUP俯視時朝向複數方向來同時地動作,可以讓球部BWb進行圓運動(或者螺旋運動)。例如圖22中的方向DR2所示,可以在X-Y平面上,朝彼此交叉的任意的方向(例如X方向與Y方向)來震動。 如此地,在沿著接線墊PD的接合面PDt的平面上,藉著在複數方向上移動球部BWb,可以確實地去除球部BWb與接線墊PD相接觸的部分以及其周邊區域上的金屬氧化膜。其結果是在後面所述的主接合步驟ST6中,當在形成接線BW的金屬(例如銅)與接線墊PD的金屬(例如鋁)的合金層PDa(圖14參考)時,不容易混入金屬氧化物的成分。
在圖22中的方向DR2是以兩端都有箭頭的複數雙箭頭來標示。「使球部BWb震動」指的是,沿著雙箭頭所示的直線,朝互相相反的方向來使球部BWb進行往復運動(在同一條線上來回)。此一往復運動可以將特定頻率的超音波施加在球部來產生。後面所述的圖24與圖25中也是標示著雙箭頭的方向DR3,這也是指將球部BWb沿著方向DR3所示的直線來進行往復運動。
在磨砂步驟ST4(參考圖17)中,施加在球部BWb上的負載M2(參考圖17)的値可以有各種變化例子,在本實施型態中是以較後面所述的主接合步驟ST6(參考圖17)中所施加的負載M4(參考圖17)小,例如0.1N(牛頓)左右。當在磨砂步驟ST4中所加的負載M2的値小時,可以降低在磨砂步驟ST4時施加在接線墊PD的周邊上的應力。另一方面,從容易除去金屬氧化膜的觀點來看,負載M2的値是越大越好。依據本專利申請的發明人的研究結果,當負載M2與圖17中所示的負載M4相同(例如,0.15N(牛頓)左右)時,在磨砂步驟ST4時並不會造成接線墊PD(參考圖23)與絕緣層IML1(參考圖23)的損傷。當圖17中所示的負載M2跟後面所述的活性化步驟ST5時所加的負載M3相同(例如0.05N(牛頓)左右)時,則確認可以去除金屬氧化膜。
如圖23所示,在磨砂步驟ST4(參考圖17)時,構成接線墊PD的金屬材料的一部分會被排出到與球部BWb接合的區域的周圍。因此,接線墊PD的接合面PDt的狀態是,與球部BWb接合的區域的周圍的高度會比球部BWb接合的區域來得隆起。與球部BWb接合的區域的周圍的高度的隆起的程度會比上述球部變形步驟ST3(參考圖17)時來得更高。
打線接合步驟中包含了在磨砂步驟ST4之後,以較負載M2(參考圖17)更小的負載M3(參考圖17)來一邊將接線BW的球部BWb壓在接線墊PD上,一邊經由鋼嘴CAP在球部BWb上施加超音波的步驟(圖17中所示的活性化步驟ST5)。打線接合步驟中包含了在活性化步驟ST5之後,以較負載M3大,但是較負載M1(參考圖17)小的負載M4(參考圖17),一邊將接線BW的球部BWb壓在接線墊PD上,一邊施加超音波來接合球部BWb與接線墊PD的步驟(圖17中所示的主接合步驟ST6)。
換言之,本實施型態的打線接合步驟是先在低負載(負載M3)的狀態上施加超音波之後,提高到較高的負載M4的狀態,然後繼續施加超音波來將球部BWb與接線墊PD相接合。活性化步驟ST5是在圖17中所示的時間T5 與時間(時序)T6 之間來實施。主接合步驟ST6是在圖17中所示的時間T6 與時間(時序)T7 之間來實施。
在本實施型態中,在活性化步驟ST5與主接合步驟ST6中所加的超音波的頻率,是例如120kHz(千赫)左右。進行活性化步驟ST5及主接合步驟ST6的時間的長度(時間T7 -時間T5 )大約在10msec(毫秒)左右。
依據本專利申請的發明人的研究,接線BW與接線墊PD可以在施加一定程度的高負載的狀態下,施加超音波震動等高頻震動來加以接合。特別是銅所構成的接線BW與鋁所構成的接線墊PD不容易接合,在上述球部接觸步驟ST2,球部變形步驟ST3,以及磨砂步驟ST4的各個步驟中,在球部BWb與接線墊PD相接合的界面上,幾乎不會形成合金層PDa(參考圖14)。從接合強度或者電性的觀點來看,若是要形成良好狀態的合金層PDa,如本實施型態一般地,一開始先以低負載的狀態來施加超音波,然後再以高負載的狀態來施加超音波的方法會特別地有效。
在本實施型態的活性化步驟ST5(參考圖17)中所加的負載M3(參考圖17)是大約在例如0.05N(牛頓)左右。當加超音波時的負載如此低時,即使是施加超音波球部BWb與接線墊PD也不會開始接合,但是球部BWb與接線墊PD的接合界面會因摩擦被活性化。因為活性化步驟ST5時的負載M3的値較低,在此段階中球部BWb與接線墊PD並不會開始接合。換言之,依據本實施型態,可以防止球部BWb與接線墊PD的接合面的一部分開始進行局部的接合(形成合金層PDa(參考圖2 5))。而是當接合面全部在活性狀態時施加負載M4(參考圖17)及超音波時,在接合面上全面地來形成合金層PDa。因此,即使負載M4的値不是非常大也可以得到良好的合金層PDa。負載M4的値是例如0.15N(牛頓)左右。
也就是說,依據本實施型態,在施加比負載M4低的負載M3的狀態下來施加超音波的活性化步驟ST5之後,提高施加在球部BWb上的負載來施加負載M4及超音波,使得接合面PDt與球部BWb的接觸界面都是在活性化的狀態下來開始接合。結果是可以抑制在主接合步驟ST6時,因為施加在接線墊PD上的應力的影響而造成接線墊PD與絕緣層IML1的損傷。藉著在主接合步驟ST6之前進行活性化步驟ST5,在圖25所示的球部BWb與接線墊PD之間所形成的合金層PDa的膜質較好。因此,即使在主接合步驟ST6中的負載M4低時也可以確保足夠的接合強度。依據本實施型態,因為合金層PDa的密度與組成不容易變得不均勻,可以使得接線BW跟接線墊PD間的接合界面上的電性較安定。
在本實施型態的情況,圖17中所示的磨砂步驟ST4及活性化步驟ST5時所加的負載M2,M3比負載M4小。因此可以減少在進行球形接合的時間(圖17中所示的時間T7 -時間T1 )時所加的負載對接線墊PD(圖25參考)所加的力積。
若是要在活性化步驟ST5使得接線墊PD的接合面PDt活性化之後,馬上開始主接合步驟ST6的觀點來看,如圖17所示地,最好是持續地施加活性化步驟ST5時的超音波的狀態之下來進行主接合步驟ST6。但是,當切換超音波的開關很容易時,也可以在從活性化步驟ST5移到主接合步驟ST6之前,暫時停止施加超音波。
活性化步驟ST5及主接合步驟ST6中所施加的超音波,是以圖15及圖16中所示的打線接合裝置WBD的振盪器USG來產生。詳細來說,振盪器USG所產生的超音波US1在突出物USH被放大,經由鋼嘴CAP傳到接線BW上。在本實施型態的情況,在活性化步驟ST5及主接合步驟ST6時,如以上所述是施加例如120kHz (千赫)左右頻率的超音波。如以上所述,從減少接合界面在不均勻的狀態時所產生的應力的觀點來看,在磨砂步驟ST4時最好不要開始接合。因此,在活性化步驟ST5及主接合步驟ST6以外的各個步驟中最好是能夠關掉振盪器USG,不要施加超音波。但如果是對球部BWb與接線墊PD的接合不會產生影響的震動則是施加也沒有關係。例如,在磨砂步驟ST4中,可以在球部BWb上施加1Hz(赫)左右的頻率的震動。例如只要是不會使球部BWb與接合面PDt間開始接合的超音波,也可以在例如圖17中所示的磨砂步驟ST4中施加超音波。當在磨砂步驟ST4中施加超音波時,其頻率最好是後面所述的活性化步驟ST5及主接合步驟ST6時所施加的超音波頻率的一半以下(最好是在1/4以下)。
施加在球部BWb上的超音波的震動方向,基於以下的理由被限定在一個方向。因為超音波US1是疏密波(縱波),會沿著突出物USH的延伸方向(圖15及圖16所示的例子中的X方向)來震動。如圖16中所示,因為鋼嘴CAP是被固定在突出物USH上,經由鋼嘴CAP被傳到球部BWb上的超音波US1在平面上的震動方向會與突出物USH的延伸方向相同。
在圖24及圖25所示的例子中,超音波的震動方向(沿著直線反覆運動的方向) DR3是與X方向相。但以上所述超音波的震動方向會被限制在圖15中所示的突出物USH的延伸方向。因此本實施型態的一個變化例中,超音波的震動方向DR3也可以是跟X方向及Y方向不同的方向(與X方向及Y方向成交叉的方向)。
當在球部BWb上施加超音波時,隨著超音波的震動,構成接線墊PD的金屬材料的一部分會被排出到周圍,形成激起部SPP。激起部SPP是沿超音波的震動方向DR3來延伸。因此,圖24所示的例子中激起部SPP在X方向會比Y方向長。激起部SPP是隨著所加的高頻震動來成長。因此,雖然在上述球部變形步驟ST3 (參考圖17)與磨砂步驟ST4(參考圖17)時在球部BWb的周圍也會形成隆起的部分,激起部SPP跟這些隆起的部分相比,會延伸的更薄與更長。
將活性化步驟ST5(參考圖17)與主接合步驟ST6(參考圖17)相比時,當施加超音波時在球部BWb上所加的負載越小,激起部SPP越容易成長。因此,在本實施型態的情況,在活性化步驟ST5時較容易成長激起部SPP。但是從以下的觀點來看,最好是能夠抑制激起部SPP的成長。亦即,當激起部SPP的成長,造成鄰接的接線墊PD上分別形成的激起部SPP互相接觸時會成為短路的原因。當激起部S PP的面積變大時,會變得容易斷裂,當接線墊PD與激起部SPP因斷裂而分離時,會成為具導電性的異物。因此,從改善半導體裝置的可靠性的觀點來看,即使會產生激起部SPP,也最好能夠縮小它的面積。
減少作為激起部來源的接線墊PD的體積可以有効地抑制激起部SPP的成長。在本實施型態的情況,如以上所述接線墊PD的厚度THpd(參考圖6)較薄,例如是在覆蓋接線墊PD的絕緣膜PV的厚度THpv(圖6參考)以下。依據本實施型態, 因為接線墊PD的厚度THpd較薄,在活性化步驟ST5時,即使是在施加低負載的負載M3(參考圖17)的狀態下來施加超音波,也可以抑制激起部SPP的成長。
在本實施型態的情況,圖14中所示的合金層PDa的大部分是在圖17的主接合步驟ST6時被形成。換言之,在主接合步驟ST6開始前,球部BWb與接線墊PD間幾乎不會被接合。因此,從提高接合強度的觀點來看,進行形成合金層PDa的主接合步驟ST6的時間,最好是有一定的長度。在本實施型態的情況,如圖17所示地,主接合步驟ST6的時間長度(時間T6 -時間T5 ),較活性化步驟ST5的時間長度(時間T5 -時間T4 )來得長。換言之,在主接合步驟ST6施加超音波的時間比在活性化步驟ST5施加超音波的時間長。主接合步驟ST6的時間長度(時間T6 -時間T5 )較球部變形步驟ST3的時間長度(時間T4 -時間T3 )長。如此地,藉著加長主接合步驟ST6的時間長度,可以提高球部BWb跟接線墊PD的接合強度。
藉由以上的各個步驟,接線BW的球部BWb會與接線墊PD相接合。在打線接合步驟中,在球部BWb與接線墊PD相接合之後,亦即在主接合步驟ST6之後,形成圖10所示的接線圈。接線圈一邊將接線BW從鋼嘴CAP(參考圖25)伸出來,一邊將鋼嘴CAP朝著導線LD的打線接合區域移動。然後,藉著將接線BW的另一端部接合在導線LD的頂面LDt上來形成圖10中所示的接線BW。
<變化例> 以上,將本專利申請的發明人所完成的發明依據實施型態來具體地作了說明,但是本發明並不僅限定在上述的實施型態,只要不脫離其要點的範圍當然也可以有各種的變化。
(變化例1) 在上述實施型態中,在球形接合步驟中的接合工具的高度,施加在球部上的負載,是否有磨砂動作,及是否有超音波震動的關係是以圖17中所示的時序圖來作說明,但也可以在圖17中應用各種的變化例。圖26~圖28分別是相對於圖17的變化例之時序圖。
首先,在圖17中說明了在磨砂步驟ST4時施加在球部BWb上的負載M2的値較負載M3大,但是較負載M4小的實施態様。但是負載M2的値可以有各種的變化例。
例如圖26所示的變化例中,在磨砂步驟ST4時施加在球部BWb(參考圖23)上的負載M2的値,也可以跟主接合步驟ST6時施加在球部BWb(參考圖25)上的負載M4的値相同。在圖26所示的變化例的情況,在磨砂動作結束的時間T4 之後,跟施加超音波的時間T5 之前,減小施加在球部BWb上的負載而成為負載M3。然後, 在施加超音波的時間T5 之後,增大施加在球部BWb上的負載,使其成為與負載M2相同的負載M4。這時,在磨砂步驟ST4中,因為使用比圖17所示的例子中更大的負載來去除金屬氧化膜,可以有效率地去除金屬氧化膜。在圖17及圖26所示的例子中,進行磨砂動作的時間長度(時間T4 -時間T3 )大約在5msec(毫秒)左右, 但有時候也可以根據金屬氧化膜的除去効率來縮短此時間的長度。
但是,當負載M2的値變大時,對球形接合步驟整體來說,施加在接線墊PD上的負載的力積會變大,可能成為接線墊PD(參考圖25)或者絕緣層IML1(參考圖25)損傷的原因。因此負載M2最好是在負載M4以下。
例如在圖27所示的變化例中,在磨砂步驟ST4時施加在球部BWb(參考圖23)上的負載M2的値,也可以跟活性化步驟ST5時施加在球部BWb上的負載M3的値相同。圖27所示的變化例的情況,在球部變形步驟ST3結束的時間T2 時,將傳達到球部BWb上的負載的値降低到負載M2,直到主接合步驟ST6開始的時間T6 之前,持續地施加一定的負載。這時,跟圖17所示的例子相比,在磨砂步驟ST4時可以進一步減少傳達到接線墊PD上的應力。因此,即使圖6所示的接線墊PD的厚度THpd是在特別薄的情況(例如600nm以下),也可以減少圖23中所示的接線墊PD跟絕緣層IML1的損傷。
圖17,圖26,及圖27中所分別記載的時間T2 ~時間T3 間的時間,及時間T4 ~時間T5 間的時間,是在一個步驟結束之後,直到下個步驟開始前的轉換時間,這些時間也可以很短。在此省略圖示,例如時間T2 跟時間T3 也可以是同一時間。
圖17所示的例子是在時間T5 ~時間T7 的時間內施加超音波,在其他的時間則沒有施加超音波。圖17的一變化例則是在時間T5 ~時間T7 的時間以外也可以施加超音波。
例如圖28所示的變化例中,與圖17所示的實施型態不同的是除了時間T5 ~時間T7 的時間以外,在時間T0 ~時間T1 的時間內也有施加超音波。時間T0 ~時間T1 的時間是上述打線接合步驟中,從球部形成步驟ST1到球部接觸步驟ST2之間的時間。如此地在從球部形成步驟ST1到球部接觸步驟ST2之間施加超音波,可以提高在圖19中所示的俯視圖中,球部BWb與接線墊PD的位置對準的精度。
在此省略圖示,圖17的另一變化例是在時間T5 ~時間T7 以外的時間,可以使用不會讓接線BW跟接線墊PD開始接合的頻率來施加超音波。
(變化例2) 在上述實施型態中說明了圖3中所示的複數接線BW分別是由銅所構成,接線墊PD是由鋁所構成的實施型態。但是如同上述實施型態中所說明的,當構成接線BW的金屬材料比構成接線墊PD的金屬材料硬,在進行球形接合時接線墊PD容易發生變形的情況時,也可以應用在其他金屬材料的情況。但是,當接線BW是由金所構成,接線墊PD是由鋁所構成的情況,跟接線BW是銅的情況相比較,接線BW跟接線墊PD較容易接合。因此,在上述實施型態的說明中,直在主接合步驟ST6為止,接線BW跟接線墊PD幾乎都不會開始接合這點上,應用在接線BW是銅所構成的情況會特別的有効。
(變化例3) 在上述實施型態中,如同使用圖6所作的說明,是針對接線墊PD的厚度THpd較薄(例如1μm以下)的情況來做說明。但即使例如接線墊PD的厚度THpd是比覆蓋接線墊PD的絕緣膜PV的厚度THpv厚的情況,也是可以應用上述實施型態中所說明的打線接合步驟。但是跟上述實施型態所說明的實施態様相比較,因為激起部SPP(圖25參考)較容易成長,需要能夠縮短活性化步驟ST5的時間等抑制激起部SPP成長的對策。
(變化例4) 例如,在上述實施型態中將半導體晶片CP的接線墊PD與接線BW的球部BW b相接合的半導體裝置的例子,是以導線架型的半導體裝置來做了說明,但是半導體裝置的實施態様有各種的變化例。例如也可以應用在像圖29中所示的半導體裝置PKG2,半導體晶片CP是被搭載在配線基板(基材)WS上的面矩陣式的半導體裝置。圖29是圖2的變化例子的半導體裝置的剖面圖。面矩陣式的半導體裝置指的是配置在安裝面上的外部端子是排列成矩陣狀的半導體裝置。面矩陣式半導體裝置包含例如圖29中所示的半導體裝置PKG2,在配線基板WS的安裝面之底面WSb上,形成有作為外部端子的焊接球SB的BGA(Ball Grid Array)等。
半導體裝置PKG2的情況,是將接線BW的一端部即球部BWb與半導體晶片CP的接線墊PD接在一起,另一端部是與露在配線基板WS的頂面WSt那一側的接合導線(端子)BL接在一起。接合導線BL是經由配線基板WS上所具有的導線WS w來與外部端子之焊接球SB相連接。
半導體裝置PKG2的製造方法的情況,是在圖7所示的基材準備步驟中,準備配線基板WS來代替上述實施型態中所說明的導線架LF(參考圖8)。圖7中所示的晶粒接合步驟中,半導體晶片CP是透過晶粒接合材DB來搭載在配線基板WS的晶片搭載面之頂面(主面)WSt上。在圖7所示的打線接合步驟中,接線BW的一端部之球部BWb是與半導體晶片CP的接線墊PD相連接,另一端部是與露在配線基板WS的頂面WSt那一側的接合導線BL相連接。在圖7所示的密封步驟中,搭載在配線基板WS的頂面WSt的半導體晶片CP,複數接線BW,及複數接合導線BL分別都被密封在密封體MR中。另一方面,在配線基板WS的底面WSb那一側則不會被密封,而是從密封體MR露出來。圖7所示的電鍍步驟及導線切斷步驟可以被省略,而是使用將複數焊接球SB搭載在配線基板WS的底面WSb側之球安裝步驟來代替。
(變化例5) 只要不脫離上述實施型態所說明的技術思想的重點的範圍,也可以將變化例將以組合來使用。
只要不脫離上述實施型態所說明的技術思想的重點的範圍,也可以將以上所述的各個實施型態之間,或者將各個實施型態中所說明的各種變化例之間加以組合來應用。
BL‧‧‧接合導線(端子)BW‧‧‧接線(導電性構件)BWb‧‧‧球部CAP‧‧‧鋼嘴CBb‧‧‧底面CBP‧‧‧導體圖案(導線)CBt‧‧‧頂面CP‧‧‧半導體晶片CPb‧‧‧背面(底面)CPs‧‧‧側面CPs1~CPs4、Pks1~Pks4、S1~S4‧‧‧邊(主邊)CPt‧‧‧表面(主面、頂面)DB‧‧‧晶粒接合材(接合材)DL‧‧‧配線層DP‧‧‧晶粒墊(晶片搭載部)DPt‧‧‧頂面(表面、主面、晶片搭載面)DR1~DR3‧‧‧方向HL‧‧‧懸吊導線ILD‧‧‧內部導線部IML、IML1‧‧‧絕緣層LD‧‧‧導線(端子、外部端子)LDt‧‧‧頂面LF‧‧‧導線架(基板)LFa‧‧‧元件形成部LFb‧‧‧框部M1~M4‧‧‧負載MC‧‧‧金屬膜(外表電鍍膜)MD‧‧‧成形模具MDc‧‧‧空洞MR‧‧‧密封體(樹脂體、密封部)MRb‧‧‧底面(背面、被安裝面)MRs‧‧‧側面MRt‧‧‧頂面OLD‧‧‧外部導線部OSP‧‧‧偏移部PD‧‧‧接線墊(電極、電極接線墊、接合接線墊)PDa‧‧‧合金層PDb‧‧‧背面PDt‧‧‧接合面PKG1、PKG2‧‧‧半導體裝置PV‧‧‧保護膜(Passivation膜、絕緣膜)PVb‧‧‧底面(面)PVk‧‧‧開口部PVt‧‧‧頂面(面)Q1‧‧‧半導體元件SB‧‧‧焊接球SDL‧‧‧配線部SPP‧‧‧激起部SS‧‧‧半導體基板SSb‧‧‧底面(背面)SSt‧‧‧頂面(半導體元件形成面)ST1‧‧‧球部形成步驟ST2‧‧‧球部接觸步驟ST3‧‧‧球部變形步驟ST4‧‧‧磨砂步驟ST5‧‧‧活性化步驟ST6‧‧‧主接合步驟STG‧‧‧基座SUP‧‧‧支持部TB‧‧‧聯結桿TH1、THcb、THpd、THpv‧‧‧厚度US1‧‧‧超音波USG‧‧‧振盪器USH‧‧‧突出物WBD‧‧‧打線接合裝置WS‧‧‧配線基板(基材)WSb‧‧‧底面WSt‧‧‧頂面(主面)WSw‧‧‧配線
【圖1】一實施型態的半導體裝置的俯視圖。 【圖2】沿著圖1的A-A線的剖面圖。 【圖3】透視圖1中的密封體來顯示半導體裝置的内部構造之透視平面圖。 【圖4】圖3中的半導體晶片的俯視圖。 【圖5】沿著圖4的A-A線的放大剖面圖。 【圖6】將圖5的A部進一步放大後放大剖面圖。 【圖7】說明一實施型態的半導體裝置的組裝流程的說明圖。 【圖8】圖7中說明的基材準備步驟中所準備的導線架的一部分的放大平面圖。 【圖9】沿著圖8的A-A線的剖面,來說明在導線架的晶粒墊上搭載半導體晶片後之狀態的放大剖面圖。 【圖10】說明將圖9中所示的半導體晶片與複數導線,透過接線來進行電性連接後的狀態的放大剖面圖。 【圖11】說明將圖10中所示的半導體晶片以樹脂來密封後的狀態之放大剖面圖。 【圖12】說明在圖11中所示的複數導線的露出面上形成金屬膜,將其分別切斷並成形後的狀態之放大平面圖。 【圖13】說明在圖4的B部,在接線墊上連接接線後的狀態之放大平面圖。 【圖14】沿著圖13的A-A線上的放大剖面圖。 【圖15】用來說明圖7中所示的打線接合步驟中所使用的打線接合裝置與導線架的位置關係的俯視圖。 【圖16】用來說明沿著圖15的A-A線的剖面的剖面圖。 【圖17】圖7所示的打線接合步驟中,說明連接接線的球部與接線墊的步驟中,接合工具的高度,施加在球部上的負載,有無施加磨砂動作,以及有無超音波震動的關係的時序圖。 【圖18】說明在圖13所對應的接線墊上,球部接觸於接線墊後的狀態之放大平面圖。 【圖19】沿著圖18的A-A線的放大剖面圖。 【圖20】用來說明將圖18所示的球部推壓使其變形後的狀態的放大平面圖。 【圖21】沿著圖20的A-A線的放大剖面圖。 【圖22】用來說明對圖20所示的球部進行磨砂動作的方向的放大平面圖。 【圖23】沿著圖22的A-A線之放大剖面圖。 【圖24】說明在圖22所示的球上施加超音波使其與接線墊接合後的狀態之放大平面圖。 【圖25】沿著圖24的A-A線之放大剖面圖。 【圖26】圖17的一變化例子之時序圖。 【圖27】圖17的其他變化例子之時序圖。 【圖28】圖17之其他變化例子之時序圖。 【圖29】圖2的變化例之半導體裝置的剖面圖。
M1~M4‧‧‧負載
ST1‧‧‧球部形成步驟
ST2‧‧‧球部接觸步驟
ST3‧‧‧球部變形步驟
ST4‧‧‧磨砂步驟
ST5‧‧‧活性化步驟
ST6‧‧‧主接合步驟

Claims (27)

  1. 一種半導體裝置之製造方法,包含以下步驟:(a)準備具有第1主面之半導體晶片的步驟,該第1主面上形成有絕緣膜及從該絕緣膜上所形成的複數開口部分別露出的複數電極;(b)準備具有搭載上述半導體晶片的第2主面及多數端子的基材的步驟;(c)在該(a)步驟及該(b)步驟之後,將該半導體晶片搭載在該基材的該第2主面上的步驟;(d)在該(c)步驟之後,將該複數電極與該複數端子透過複數接線分別電性連接的步驟;及(e)在該(d)步驟之後,將該半導體晶片與該複數接線進行樹脂密封的步驟;在該(a)步驟中,該複數電極包含第1電極,該第1電極具有從該複數開口部中的第1開口部露出的第1接合面,俯視時,該複數開口部分別包含沿第1方向延伸的第1邊及沿與該第1方向交叉的第2方向延伸的第2邊之複數邊,該(d)步驟包含以下步驟:(d1)將該複數接線所包含的第1接線的球部接觸在該第1電極的該第1接合面的步驟;(d2)在該(d1)步驟之後,將該第1接線的該球部朝向該第1接合面以第1負載進行推壓的步驟;(d3)在該(d2)步驟之後,以較該第1負載小的第2負載,一邊使該第1接線的該球部推壓於該第1電極上,並且俯視時使該球部在包含彼此交叉的2個方向的複數方向移動的步驟; (d4)在該(d3)步驟之後,一邊使用與該第2負載相同,或者比該第2負載小的第3負載來使該第1接線的該球部推壓於該第1電極上,一邊將具有第1頻率的第1超音波施加在該球部上,使該球部在俯視時沿著第3方向進行往復運動的步驟;及(d5)在該(d4)步驟之後,一邊使用較該第3負載大,但比該第1負載小的第4負載來使該第1接線的該球部推壓於該第1電極上,一邊施加具有該第1頻率的該第1超音波,使該球部在俯視時沿著該第3方向進行往復運動,藉此將該球部與該第1電極接合的步驟;在該(d3)步驟中不施加超音波。
  2. 如申請專利範圍第1項的半導體裝置之製造方法,其中,該第3方向與該第1方向及該第2方向不同。
  3. 如申請專利範圍第2項的半導體裝置之製造方法,其中,該(d4)步驟及該(d5)步驟分別都一邊僅沿著該第3方向來進行往復運動,一邊將該第1超音波施加在該球部上。
  4. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d3)步驟中,俯視時,沿著該2個方向分別進行往復運動。
  5. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d4)步驟到該(d5)步驟之間,持續地施加具有該第1頻率的該第1超音波。
  6. 如申請專利範圍第1項的半導體裝置之製造方法,其中, 在該(d5)步驟中,施加該第1超音波的時間比在該(d4)步驟中施加該第1超音波的時間長。
  7. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d3)步驟中施加的該第2負載與在該(d5)步驟中施加的該第4負載係相同。
  8. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d3)步驟中施加的該第2負載與在該(d4)步驟中施加的該第3負載係相同。
  9. 如申請專利範圍第1項的半導體裝置之製造方法,其中,該第1電極具有位於該第1接合面之相反側的第1背面,接合該球部之前的該第1電極的厚度,較該絕緣膜中覆蓋該第1電極的一部分之部分的厚度薄。
  10. 如申請專利範圍第1項的半導體裝置之製造方法,其中,該第1電極是以鋁為主要成分的金屬材料所構成,該第1接線是以銅為主要成分的金屬材料所構成。
  11. 如申請專利範圍第1項的半導體裝置之製造方法,其中,該第1電極具有位於該第1接合面之相反側的第1背面,在該第1電極的該第1背面側,形成有較該第1電極的厚度厚的第1絕緣層。
  12. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d3)步驟中,在該第1電極的該第1接合面上所形成的金屬氧化膜被去除。
  13. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d5)步驟中,在該球部與該第1電極的接合界面上形成合金層。
  14. 如申請專利範圍第1項的半導體裝置之製造方法,其中,在該(d2)步驟中,該球部會變形。
  15. 一種半導體裝置之製造方法,包含以下步驟:(a)準備具有第1主面之半導體晶片的步驟,該第1主面上形成有絕緣膜及從該絕緣膜上所形成的複數開口部分別露出的複數電極;(b)準備具有搭載上述半導體晶片的第2主面及多數端子的基材的步驟;(c)在該(a)步驟及該(b)步驟之後,將該半導體晶片搭載在該基材的該第2主面上的步驟;(d)在該(c)步驟之後,將該複數電極與該複數端子透過複數接線分別電性連接的步驟;及(e)在該(d)步驟之後,將該半導體晶片與該複數接線進行樹脂密封的步驟;在該(a)步驟中,該複數電極包含第1電極,該第1電極具有從該複數開口部中的第1開口部露出的第1接合面,俯視時,該複數開口部分別包含沿第1方向延伸的第1邊及沿與該第1方向交叉的第2方向延伸的第2邊之複數邊,該(d)步驟包含以下步驟:(d1)將該複數接線所包含的第1接線的球部接觸在該第1電極的該第1接合面的步驟; (d2)在該(d1)步驟之後,將該第1接線的該球部朝向該第1接合面以第1負載進行推壓的步驟;(d3)在該(d2)步驟之後,以較該第1負載小的第2負載,一邊使該第1接線的該球部推壓於該第1電極上,並且俯視時使該球部在包含彼此交叉的2個方向的複數方向移動的步驟;(d4)在該(d3)步驟之後,一邊使用與該第2負載相同,或者比該第2負載小的第3負載來使該第1接線的該球部推壓於該第1電極上,一邊將具有第1頻率的第1超音波施加在該球部上,使該球部在俯視時沿著第3方向進行往復運動的步驟;及(d5)在該(d4)步驟之後,一邊使用較該第3負載大,但比該第1負載小的第4負載來使該第1接線的該球部推壓於該第1電極上,一邊施加具有該第1頻率的該第1超音波,使該球部在俯視時沿著該第3方向進行往復運動,藉此將該球部與該第1電極接合的步驟;在該(d5)步驟中,施加該第1超音波的時間比在該(d4)步驟中施加該第1超音波的時間長。
  16. 如申請專利範圍第15項的半導體裝置之製造方法,其中,該第3方向與該第1方向及該第2方向不同。
  17. 如申請專利範圍第16項的半導體裝置之製造方法,其中,該(d4)步驟及該(d5)步驟分別都一邊僅沿著該第3方向來進行往復運動,一邊將該第1超音波施加在該球部上。
  18. 如申請專利範圍第15項的半導體裝置之製造方法,其中,在該(d3)步驟中,俯視時,沿著該2個方向分別進行往復運動。
  19. 如申請專利範圍第15項的半導體裝置之製造方法,其中,在該(d4)步驟到該(d5)步驟之間,持續地施加具有該第1頻率的該第1超音波。
  20. 如申請專利範圍第15項的半導體裝置之製造方法,其中,在該(d3)步驟中施加的該第2負載與在該(d5)步驟中施加的該第4負載係相同。
  21. 如申請專利範圍第15項的半導體裝置之製造方法,其中,在該(d3)步驟中施加的該第2負載與在該(d4)步驟中施加的該第3負載係相同。
  22. 如申請專利範圍第15項的半導體裝置之製造方法,其中,該第1電極具有位於該第1接合面之相反側的第1背面,接合該球部之前的該第1電極的厚度,較該絕緣膜中覆蓋該第1電極的一部分之部分的厚度薄。
  23. 如申請專利範圍第15項的半導體裝置之製造方法,其中,該第1電極是以鋁為主要成分的金屬材料所構成,該第1接線是以銅為主要成分的金屬材料所構成。
  24. 如申請專利範圍第15項的半導體裝置之製造方法,其中,該第1電極具有位於該第1接合面之相反側的第1背面,在該第1電極的該第1背面側,形成有較該第1電極的厚度厚的第1絕緣層。
  25. 如申請專利範圍第15項的半導體裝置之製造方法,其中, 在該(d3)步驟中,在該第1電極的該第1接合面上所形成的金屬氧化膜被去除。
  26. 如申請專利範圍第15項的半導體裝置之製造方法,其中,在該(d5)步驟中,在該球部與該第1電極的接合界面上形成合金層。
  27. 如申請專利範圍第15項的半導體裝置之製造方法,其中,在該(d2)步驟中,該球部會變形。
TW106142841A 2016-12-26 2017-12-07 半導體裝置之製造方法 TWI762533B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-251734 2016-12-26
JP2016251734A JP6688725B2 (ja) 2016-12-26 2016-12-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201836106A TW201836106A (zh) 2018-10-01
TWI762533B true TWI762533B (zh) 2022-05-01

Family

ID=60452456

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106142841A TWI762533B (zh) 2016-12-26 2017-12-07 半導體裝置之製造方法

Country Status (6)

Country Link
US (1) US10134705B2 (zh)
EP (1) EP3340286B1 (zh)
JP (1) JP6688725B2 (zh)
KR (1) KR102457570B1 (zh)
CN (1) CN108242435B (zh)
TW (1) TWI762533B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3603826B1 (en) * 2018-07-31 2023-05-10 Infineon Technologies AG Method for calibrating an ultrasonic bonding machine
US11545418B2 (en) * 2018-10-24 2023-01-03 Texas Instruments Incorporated Thermal capacity control for relative temperature-based thermal shutdown
JP7368055B2 (ja) * 2019-06-21 2023-10-24 ローム株式会社 半導体装置、および、半導体装置の実装構造
JP2022082887A (ja) 2020-11-24 2022-06-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN116529876A (zh) * 2020-11-27 2023-08-01 罗姆股份有限公司 半导体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884835A (en) * 1995-07-26 1999-03-23 Hitachi, Ltd. Ultrasonic bonding method and ultrasonic bonding apparatus
US6112969A (en) * 1996-10-17 2000-09-05 Mitsubishi Denki Kabushiki Kaisha Wire bonding apparatus
US20120164795A1 (en) * 2010-12-27 2012-06-28 Renesas Electronics Corporation Ultrasonic Wire Bonding Method for a Semiconductor Device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960006710B1 (ko) 1987-02-25 1996-05-22 가부시기가이샤 히다찌세이사꾸쇼 면실장형 반도체집적회로장치 및 그 제조방법과 그 실장방법
JPH01215033A (ja) * 1988-02-24 1989-08-29 Fuji Electric Co Ltd 半導体チップ用ボンディングパッド
JP2761922B2 (ja) 1989-05-11 1998-06-04 株式会社日立製作所 ワイヤボンディング方法および装置
JP2530224B2 (ja) * 1989-05-15 1996-09-04 株式会社新川 ワイヤボンデイング方法
US7198969B1 (en) * 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
JPH0574874A (ja) * 1991-09-11 1993-03-26 Hitachi Ltd 金属細線の超音波接合方法および装置
JP2527531B2 (ja) 1994-04-22 1996-08-28 株式会社日立製作所 ワイヤボンディング装置
JPH08316264A (ja) * 1996-04-05 1996-11-29 Hitachi Ltd 半導体装置及びその形成方法
JP2001308145A (ja) * 2000-04-25 2001-11-02 Fujitsu Ltd 半導体チップの実装方法
JP4595018B2 (ja) * 2009-02-23 2010-12-08 株式会社新川 半導体装置の製造方法およびボンディング装置
JP5893266B2 (ja) * 2011-05-13 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6279339B2 (ja) * 2014-02-07 2018-02-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2016028417A (ja) * 2014-07-11 2016-02-25 ローム株式会社 電子装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5884835A (en) * 1995-07-26 1999-03-23 Hitachi, Ltd. Ultrasonic bonding method and ultrasonic bonding apparatus
US6112969A (en) * 1996-10-17 2000-09-05 Mitsubishi Denki Kabushiki Kaisha Wire bonding apparatus
US20120164795A1 (en) * 2010-12-27 2012-06-28 Renesas Electronics Corporation Ultrasonic Wire Bonding Method for a Semiconductor Device

Also Published As

Publication number Publication date
EP3340286A1 (en) 2018-06-27
CN108242435A (zh) 2018-07-03
JP6688725B2 (ja) 2020-04-28
TW201836106A (zh) 2018-10-01
US20180182731A1 (en) 2018-06-28
EP3340286B1 (en) 2022-02-23
KR20180075408A (ko) 2018-07-04
KR102457570B1 (ko) 2022-10-24
JP2018107269A (ja) 2018-07-05
US10134705B2 (en) 2018-11-20
CN108242435B (zh) 2022-11-04

Similar Documents

Publication Publication Date Title
TWI762533B (zh) 半導體裝置之製造方法
JP5041654B2 (ja) リボンボンディング
US7400002B2 (en) MOSFET package
US7863107B2 (en) Semiconductor device and manufacturing method of the same
JP6279339B2 (ja) 半導体装置の製造方法
JP5553766B2 (ja) 半導体装置とその製造方法
JPWO2011039795A1 (ja) 半導体装置とその製造方法
JP5566296B2 (ja) 半導体装置の製造方法
US20160197030A1 (en) Integrated circuit (ic) package with thick die pad, and associated methods
JP6653235B2 (ja) 半導体装置の製造方法および半導体装置
JP2005050948A (ja) リードフレーム及びそれを用いた樹脂封止型半導体装置及びその製造方法
JP2015037151A (ja) 半導体装置
US11018078B2 (en) Method of producing electronic components, corresponding electronic component
JP2018190859A (ja) 半導体装置およびその製造方法
JP2006140329A (ja) 半導体装置の製造方法