TWI759290B - 異向性導電連接結構體 - Google Patents

異向性導電連接結構體 Download PDF

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TWI759290B
TWI759290B TW106110549A TW106110549A TWI759290B TW I759290 B TWI759290 B TW I759290B TW 106110549 A TW106110549 A TW 106110549A TW 106110549 A TW106110549 A TW 106110549A TW I759290 B TWI759290 B TW I759290B
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Taiwan
Prior art keywords
electrode terminal
anisotropic conductive
connection structure
conductive connection
conductive particles
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TW106110549A
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English (en)
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TW201804583A (zh
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佐藤大祐
樋口明史
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日商迪睿合股份有限公司
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Abstract

提供一種新穎且經改良之異向性導電連接結構體,該異向性導電連接結構體可減少電極端子彼此之異向性導電連接部分的連接電阻,提高可靠性,且能夠提高連接強度。
為了解決上述課題,若根據本發明之某觀點,則提供一種異向性導電連接結構體,該異向性導電連接結構體具備表面形成有突出部之第1電極端子、第2電極端子及含有將第1電極端子與第2電極端子導通之導電性粒子的異向性導電接著劑層,突出部之高度相對於導電性粒子之壓縮前粒徑的比未達60%,第1電極端子之開口面積率為55%以上,第2電極端子之高度為6μm以上。

Description

異向性導電連接結構體
本發明係關於一種異向性導電連接結構體。
作為將具有電極端子之複數個電子零件(例如,IC晶片、剛性基板(rigid substrate)、撓性基板等)彼此連接的方法,已知有倒裝晶片黏接法。倒裝晶片黏接法係在使複數個電子零件之電極端子彼此對向的狀態下,將電極端子彼此連接。
作為此種倒裝晶片黏接法之例,已知有超音波連接法。此方法係使複數個電子零件之電極端子彼此接觸。接著,藉由超音波使電極端子之接觸部分振動。藉此,將電極端子彼此連接。於此方法中,以金構成兩邊電子零件之電極端子。接著,將填充劑(所謂之底膠(underfill))填充於連接部分之周邊空間,使之硬化。
又,作為倒裝晶片黏接法之其他例,已知有共晶法。此方法係使複數個電子零件之電極端子彼此接觸。接著,將電極端子之接觸部分加熱。藉此,使電極端子彼此共晶而連接。於此方法中,例如以金構成其中一邊之電子零件的電極端子,而以錫構成另一邊之電子零件的電極端子。接著,將填充劑(所謂之底膠)填充於連接部分之周邊空間,使之硬化。
然而,超音波連接法由於超音波會使電極端子劇烈振動,因此,可能會發生連接不良或短路等。又,可應用超音波連接法之電極端子由於必須以金等昂貴材料構成,因此會使得成本增加。又,由於必須進行填充劑之填充、硬化,因此,成本在此方面上亦會增加。又,工作量亦會增加。
另一方面,於共晶法,會對電極端子之連接部分進行加熱,此時之加熱溫度會非常高。例如,加熱溫度會到達400℃左右。因此,當電子零件為撓性基板之情形時,於加熱時撓性基板可能會變形。若撓性基板變形,則有時撓性基板上之電極端子的位置等會偏移。因此,可能會發生連接不良、短路等。並且,與超音波連接法同樣地亦會有填充劑之相關問題。
因此,近年來,例如如專利文獻1、2揭示般,倒裝晶片黏接法亦即使用異向性導電膜將電極端子彼此異向性導電連接之方法受到矚目。此方法由於不需要超音波,因此不會發生超音波之相關問題。又,雖然即使是使用異向性導電膜之連接方法,也需要加熱之製程,但加熱溫度較共晶法低。並且,由於構成異向性導電膜之硬化性樹脂作為填充劑用,因此不需要另外填充填充劑並使之硬化的製程。
專利文獻1:日本特開平11-31698號公報
專利文獻2:日本特開2005-93978號公報
然而,當電子零件為IC晶片之情形時,在IC晶片會形成凸 塊作為電極端子。於此凸塊表面(亦即,與其他電子零件之電極端子對向之面)之周邊部分,大多會形成突出部。並且,突出部大多會形成於凸塊表面之整個外緣。以往,此種突出部由於被認為會是連接不良之原因,因此認為較佳盡可能地小。具體而言,當在由突出部形成之凹部(所謂之小凹坑)內埋藏有導電性粒子的情形時,導電性粒子可能會未被充分地壓縮。因此,可能會發生連接不良。因此,專利文獻1、2揭示之技術,要使突出部盡可能地小。
然而,專利文獻1、2揭示之技術,為了縮小突出部而花費了非常大的工夫。具體而言,專利文獻1揭示之技術為了縮小突出部,而使形成於絕緣層之開口部分的開口面積非常地小。此處,絕緣層為覆蓋IC晶片之功能面之層,開口部分形成於IC晶片之電極墊(electrode pad)上。又,凸塊透過絕緣層之開口部分與電極墊連接。於專利文獻1揭示之技術中,藉由縮小此種開口部分之開口面積,來縮小突出部。然而,使開口面積縮小之步驟非常花費工夫。另一方面,於專利文獻2揭示之技術,為了縮小突出部,而另外需要對突出部照射超音波之步驟。
並且,本發明人經對縮小突出部之技術進行研究後,結果明白了若僅使突出部縮小,則反而會發生連接電阻增大或可靠性降低。並且近年來,強烈要求進一步提升異向性導電連接部分之連接強度。
因此,本發明係有鑑於上述問題而完成者,本發明之目的在於提供一種新穎且經改良之異向性導電連接結構體,該異向性導電連接結構體可減少電極端子彼此之異向性導電連接部分的連接電阻,提高可靠性,且能夠提高連接強度。
為了解決上述課題,若根據本發明之某觀點,則提供一種異向性導電連接結構體,該異向性導電連接結構體具備表面形成有突出部之第1電極端子、第2電極端子及含有將第1電極端子與第2電極端子導通之導電性粒子的異向性導電接著劑層,突出部之高度相對於導電性粒子之壓縮前粒徑的比未達60%,第1電極端子之開口面積率為55%以上,第2電極端子之高度為6μm以上。
若根據本觀點,則突出部可將更多之導電性粒子捕捉於突出部內之凹部。並且,凹部內之導電性粒子會被充分壓縮。因此,連接電阻會降低,可靠性會提升。並且,由於足量的接著劑會流入第2電極端子之間,因此,第1電極端子與第2電極端子會被牢固地接著。
此處,第1電極端子之硬度相對於第2電極端子之硬度的比可大於10%。
又,於第1電極端子之表面,形成有被突出部圍繞之凹部,導電性粒子之壓縮前粒徑相對於第1電極端子之凹部短邊長度的比可未達10%。
又,於第1電極端子之表面,形成有被突出部圍繞之凹部,存在於第1電極端子之凹部的導電性粒子之平均佔有面積率可未達20%。
又,突出部可形成於第1電極端子表面之整個外緣。
又,第1電極端子可為形成於第1電子零件之凸塊。
如以上說明,若根據本發明,則可減少電極端子彼此之異向性導電連接部分的連接電阻,提高可靠性,且能夠提高連接強度。
10‧‧‧異向性導電連接結構體
20‧‧‧第1電子零件
21‧‧‧第1電極端子
22‧‧‧突出部
23‧‧‧凹部
30‧‧‧第2電子零件
31‧‧‧第2電極端子
40‧‧‧接著劑層
41‧‧‧硬化樹脂層
42‧‧‧導電性粒子
圖1為表示本實施形態之異向性導電連接結構體10之概略構成的側剖面圖。
圖2為表示該實施形態之第1電極端子其表面構造的俯視圖。
以下,一邊參照附圖,一邊詳細說明本發明之較佳實施形態。另,於本說明書及圖式中,對實質上具有相同功能構成之構成要素,因賦予相同之符號,而省略重複說明。
<1.異向性導電連接結構體之構成>
首先,依照圖1及圖2,說明本實施形態之異向性導電連接結構體10的構成。
異向性導電連接結構體10具備第1電子零件20、形成於第1電子零件20上之第1電極端子21、第2電子零件30、形成於第2電子零件30上之第2電極端子32、及接著劑層40。
第1電子零件20例如為電子電路基板。電子電路基板之種類沒有特別限制,可為IC晶片、各種剛性基板(例如,玻璃環氧基板等)、撓性基板等。第1電子零件20例如為IC晶片。當第1電子零件20為IC晶片之情形時,第1電極端子21為凸塊。於凸塊易形成突出部22。
第1電極端子21形成於第1電子零件20上。又,第1電極端子21與構成第1電子零件20之電子電路導通。於第1電極端子21之表面(亦即,與第2電子零件30對向之面),形成有突出部22。當第1電子零件20為IC晶片之情形時,第1電極端子21為凸塊。惟,第1電極端子 21只要為形成有突出部22者即可。因此,第1電極端子21並未限定於凸塊。
構成第1電極端子21之材料,只要具有導電性者,則無特別限制。作為構成第1電極端子21之材料,例如較佳由鋁、銀、鎳、銅及金等金屬構成。
突出部22形成於第1電極端子21之表面。如圖2所示,突出部22形成於第1電極端子21表面之整個外緣。另,當第1電極端子21為凸塊之情形時,突出部22大多形成於第1電極端子21表面之整個外緣。當然,突出部22之形狀沒有限定於圖1所示者,但較佳為圖2之形狀。於此情形時,突出部22可更確實地捕捉導電性粒子42。
又,於第1電極端子21之表面,形成有被突出部22圍繞之凹部23(所謂之小凹坑)。以往此種突出部22及凹部23由於被認為會是連接不良之原因,因此,認為較佳盡可能地小。然而,於本實施形態,積極地充分利用突出部22。具體而言,藉由利用突出部22捕捉導電性粒子42,而可將導電性粒子42保持在第1電極端子21及第2電極端子32之間。此處,導電性粒子42為被包含在接著劑層40者。藉此,於本實施形態,可減低連接電阻,且提高可靠性。具體而言,可降低初期電阻,且可減低冷熱循環測試後之不良率。
第2電子零件30例如為電子電路基板。電子電路基板之種類沒有特別限制,可為IC晶片、各種剛性基板(例如,玻璃環氧基板等)、撓性基板等。第2電子零件30例如為撓性基板。當第2電子零件30為撓性基板之情形時,第2電極端子32之高度H2容易滿足後述之要件。撓性基 板之種類亦無特別限制,例如亦可為聚醯亞胺基板。
第2電極端子31形成於第2電子零件30上。又,第2電極端子31與構成第2電子零件30之電子電路導通。構成第2電極端子31之材料,只要為具有導電性者,則無特別限制。作為構成第2電極端子31之材料,例如可列舉:鋁、銀、鎳、銅及金等金屬。構成第2電極端子31之金屬,亦可經各種金屬鍍覆。
接著劑層40係異向性導電接著劑硬化者,具備有硬化樹脂層41與導電性粒子42。亦即,接著劑層40係將第1電極端子21與第2電極端子31異向性導電連接。
異向性導電接著劑具備有硬化性樹脂與導電性粒子42。硬化性樹脂含有聚合性化合物及硬化起始劑。聚合性化合物係藉由硬化起始劑硬化之樹脂。經硬化之聚合性化合物亦即硬化樹脂層41於接著劑層40內將第1電極端子21與第2電極端子31接著,且將導電性粒子42保持在接著劑層40內。作為聚合性化合物,例如可列舉:環氧聚合性化合物及丙烯酸聚合性化合物等。環氧聚合性化合物為於分子內具有1個或2個以上之環氧基的單體、寡聚物或預聚合物。作為環氧聚合性化合物,可列舉:各種雙酚型環氧樹脂(雙酚A型、F型等)、酚醛型環氧樹脂、橡膠及胺酯(urethane)等各種改質環氧樹脂;萘型環氧樹脂、聯苯型環氧樹脂、苯酚酚醛(phenol novolak)型環氧樹脂、茋型環氧樹脂、三酚甲烷(triphenolmethane)型環氧樹脂、二環戊二烯型環氧樹脂、三苯甲烷型環氧樹脂,及此等預聚合物等。
丙烯酸聚合性化合物為於分子內具有1個或2個以上之丙烯 酸基的單體、寡聚物或預聚合物。作為丙烯酸聚合性化合物,例如可列舉:丙烯酸甲酯、丙烯酸乙酯、丙烯酸異丙酯、丙烯酸異丁酯、環氧丙烯酸酯、乙二醇二丙烯酸酯、二乙二醇二丙烯酸酯、三羥甲基丙烷三丙烯酸酯、二羥甲基三環癸烷二丙烯酸酯、四亞甲二醇四丙烯酸酯、2-羥基-1,3-二丙烯醯氧基丙烷、2,2-雙[4-(丙烯醯氧基甲氧基)苯基]丙烷、2,2-雙[4-(丙烯醯氧基乙氧基)苯基]丙烷、丙烯酸二環戊烯酯、丙烯酸三環癸酯、參(丙烯醯氧乙基)異氰酸酯及胺酯丙烯酸酯(urethane acrylate)等。於本實施形態,可使用上述列舉之聚合性化合物中的任1種,或亦可任意地組合2種以上使用。
硬化起始劑例如為熱硬化起始劑。熱硬化起始劑係會因熱而與上述聚合性化合物同時硬化之材料。熱硬化起始劑之種類亦無特別限制。作為熱硬化起始劑,例如可列舉:使環氧聚合性化合物硬化之熱陰離子或熱陽離子硬化起始劑、使丙烯酸聚合性化合物硬化之熱自由基聚合型硬化劑等。於本實施形態,根據聚合性化合物選擇適當之熱硬化起始劑即可。另,作為硬化起始劑之其他例,可舉光硬化起始劑。作為光硬化起始劑,例如可列舉:使環氧聚合性化合物硬化之光陰離子或光陽離子硬化起始劑、使丙烯酸聚合性化合物硬化之光自由基聚合型硬化劑等。於本實施形態,根據聚合性化合物選擇適當之光硬化起始劑即可。
又,異向性導電接著劑除了上述成分以外,亦可含有膜形成樹脂、各種添加劑等。當為了使異向性導電接著劑容易處理製作成膜狀之情形時,而可於異向性導電接著劑添加膜形成樹脂。作為膜形成樹脂,例如可使用環氧樹脂、苯氧基樹脂(phenoxy resin)、聚酯氨酯(polyesterurethane) 樹脂、聚酯樹脂、聚氨酯樹脂(polyurethane resin)、丙烯酸樹脂、聚醯亞胺樹脂、丁醛樹脂等各種樹脂。又,於本實施形態,可僅使用此等膜形成樹脂中的任1種,或亦可任意地組合2種以上使用。另,膜形成樹脂從使膜形成性及接著可靠性良好之觀點而言,較佳為苯氧基樹脂。另,當將異向性導電接著劑製成膜狀之情形時,膜(亦即,異向性導電膜)之厚度並無特別限制。惟,膜若過厚,則不需要之樹脂的量會過多,流動性會發生問題。因此,較佳為100μm以下,更佳為40μm以下。若過薄,則由於會難以處理,因此,較佳為5μm以上,更佳為12μm以上。
作為可添加於異向性導電接著劑之添加劑,可列舉:矽烷偶合劑、無機填料、著色劑、抗氧化劑及防鏽劑等。矽烷偶合劑之種類並無特別限制。作為矽烷偶合劑,例如可列舉:環氧系、胺基系、氫硫基-硫醚系、脲基系之矽烷偶合劑等。當於異向性導電接著劑添加有此等矽烷偶合劑之情形時,視基材之材質,可提升接著性。
又,無機填料係用以調整異向性導電接著劑之流動性及膜強度尤其是後述之最低熔融粘度的添加劑。無機填料之種類亦無特別限制。作為無機填料,例如可列舉:二氧化矽、滑石、氧化鈦,碳酸鈣、氧化鎂等。
導電性粒子42係於接著劑層40內將第1電極端子21與第2電極端子31異向性導電連接之材料。具體而言,於接著劑層40內被第1電極端子21與第2電極端子31夾持之導電性粒子42,使第1電極端子21與第2電極端子31導通。另一方面,其他之導電性粒子42(例如進入第1電極端子21彼此之間隙的導電性粒子42、進入第2電極端子31彼此之間 隙的導電性粒子42等),則不會使任何端子間導通(亦即,不會產生於第1電極端子21間導電性粒子42連接之形態的短路、於第2電極端子31間導電性粒子42連接之形態的短路等)。
因此,導電性粒子42可於接著劑層40內維持第1電極端子21彼此及第2電極端子31彼此之絕緣性,且同時使第1電極端子21與第2電極端子31導通。亦即,導電性粒子42因在接著劑層40內被第1電極端子21與第2電極端子31夾持而將此等導通,進行異向性導電連接。導電性粒子42以不短路之程度分散於異向性導電劑,或亦可配置成各個獨立。此配置可根據各電極端子之尺寸或電極端子之排列方向的距離等作適當設定,但亦可為規則的。又,導電性粒子42滿足後述之要件。另,導電性粒子42之壓縮前粒徑若滿足後述之要件則無特別限制,作為一例,例如為1~10μm。此處,如前述,異向性導電連接前之異向性導電接著劑亦可為預先被形成膜體者。
<2.異向性導電連接結構體應滿足之要件>
接著,說明異向性導電連接結構體10應滿足之要件。當異向性導電連接結構體10滿足以下之要件的情形時,突出部22可捕捉到導電性粒子42。結果可降低連接電阻,提升可靠性。並且,接著劑層40可將第1電極端子21與第2電極端子31牢固地接著。另,異向性導電連接結構體10必須至少滿足要件1~3。異向性導電連接結構體10進一步較佳滿足要件4以後。另,當評價是否滿足以下之要件時,各電極之構造等可藉由SEM(掃瞄型電子顯微鏡)等加以觀察。例如,突出部22之高度H1可藉由使用SEM觀察第1電極端子21來測量。又,以下之參數可為測量複數個異向性導電連 接結構體10得到之測量值的算術平均值,或亦可將任一值作為代表值來使用。
(2-1.要件1)
突出部22之高度H1相對於導電性粒子42之壓縮前粒徑的比(以下,亦稱為「突出部高度/粒徑比」」未達60%。此處,壓縮前粒徑為將導電性粒子42壓縮前的粒徑。當突出部高度/粒徑比在60%以上之情形時,突出部22會妨礙導電性粒子42之壓縮。亦即,於凹部23內所捕捉之導電性粒子42會未被充分壓縮。結果,使得連接電阻增加,可靠性惡化。當突出部高度/粒徑比未達60%之情形時,突出部22可將導電性粒子42捕捉在凹部23內。並且,導電性粒子42被充分地壓縮。突出部高度/粒徑比較佳未達50%。
另,突出部高度/粒徑比之下限值並無特別限制,但若太過小,則可能突出部22會無法充分地捕捉到導電性粒子42。因此,突出部高度/粒徑比較佳在30%以上,更佳在40%以上,再更佳在42%以上。
(2-2.要件2)
第1電極端子21之開口面積率為55%以上。此處,開口面積率係凹部23之開口面相對於第1電極端子21表面之總面積的面積比。當開口面積率未達55%之情形時,於凹部23內會無法捕捉到足夠數量之導電性粒子42。開口面積率較佳在70%以上。開口面積率之上限值並無特別限制,但開口面積率若過大,則可能突出部22之剛性會變低。因此,開口面積率較佳在90%以下。
(2-3.要件3)
第2電極端子31之高度H2為6μm以上。藉此,由於足量的接著劑亦會流入第2電極端子31間,因此,第1電極端子21與第2電極端子31會被牢固地接著。並且,即使第1電極端子21之突出部22暫時接觸第2電極端子31,於第1電極端子21之下方亦會存在足量之硬化樹脂層41。因此,突出部22甚至第1電極端子21會充分受到硬化樹脂層41的保護。結果,使得連接電阻降低,可靠性提升。高度H2之上限值並無特別限制,但較佳在35μm以下。
(2-5.要件4)
第1電極端子21之硬度相對於第2電極端子31之硬度的比(以下,亦稱為「電極端子之硬度比」)較佳大於10%。其原因在於:當第1電極端子21較第2電極端子31過軟之情形時,於壓縮時(亦即,異向性導電連接時),第1電極端子21會大幅變形。因此,當變形量大之情形時,第1電極端子21彼此接觸,可能會短路。另,各電極端子之硬度,例如為維氏硬度。電極端子之硬度比,更佳大於15%,再更佳大於30%。電極端子之硬度比的上限值並無特別限制,但亦可為1左右(亦即,兩者之硬度大致一致)。
(2-6.要件5)
導電性粒子42之壓縮前粒徑相對於凹部23之短邊長度的比(以下,亦稱為「粒徑/開口短邊長度比」)較佳未達10%。此處,凹部23之短邊長度為凹部23之俯視形狀(例如圖2所示之形狀)的短邊長度。當粒徑/開口短邊長度比未達10%之情形時,可於凹部23內捕捉到更多的導電性粒子42。粒徑/開口短邊長度比,更佳未達9%,再更佳未達8.5%。另,粒徑/開口短邊長度比之下限值係根據要件1來決定。亦即,粒徑/開口短邊 長度比若過小,則導電性粒子42之粒徑會過小,而不滿足要件1。
(2-7.要件6)
又,存在於凹部23內之導電性粒子42的平均佔有面積率較佳未達20%。平均佔有面積率之下限,較佳為被壓縮之導電性粒子1個分量以上的佔有面積率,更佳為被壓縮之導電性粒子2個分量以上的佔有面積率,再更佳為被壓縮之導電性粒子3個分量以上的佔有面積率。此處,各導電性粒子42之佔有面積係於將被壓縮之導電性粒子42投影在水平面時所得到的面積。又,平均佔有面積率可用以下之步驟測量。亦即,自異向性導電連接結構體10剝除第1電極端子21,或研磨異向性導電連接結構體10至連接部分,藉此使第1電極端子21與第2電極端子31之連接部分露出。接著,選擇50個露出之連接部分。接著,於面視域對各連接部分進行觀察,測量各連接部分中之導電性粒子42的佔有面積。另,觀察可用SEM(掃瞄型電子顯微鏡)等來進行。然後,測量存在於各連接部分之凹部23內全部的導電性粒子42之佔有面積,將此等之總面積除以凹部23之開口面的面積。藉此,測量各連接部分之佔有面積率。然後,對此等之佔有面積率進行算術平均,藉此測量平均佔有面積率。當平均佔有面積率為上述範圍內之情形時,足量的導電性粒子42會被捕捉於凹部23內。
當導電性粒子42排斥過大之情形時,會有對可靠性等造成影響之虞。因此,異向性導電連接結構體除了上述之要件外,較佳進一步滿足以下之要件。亦即,導電性粒子42之30%變形時的壓縮硬度(K值)較佳未達6000N/mm2,更佳為5500N/mm2以下。此處,30%變形時之壓縮硬度(K值)為導電性粒子42壓縮強度指標之參數的一種。30%變形時 之壓縮硬度(K值)可用下述之步驟算出。亦即,將導電性粒子42於單方向壓縮至導電性粒子42之粒徑(直徑)比原粒徑短30%。然後,基於此時之荷重、位移量及壓縮前之導電性粒子42的半徑與以下之算式(1),算出30%變形時之壓縮硬度(K值)。若根據算式(1),則K值越小,導電性粒子42越會成為柔軟之粒子。
K=(3/√2)F‧S-8/2‧R-1/2 (1)
算式(1)中,F為導電性粒子42之30%壓縮變形時的荷重,S為因壓縮造成之導電性粒子42的位移量(mm),R為導電性粒子42之壓縮前的半徑(mm)。
綜上所述,若根據本實施形態,則由於突出部22之高度H1等滿足規定之要件,因此,可有效利用突出部22而提高異向性導電連接結構體10之品質。具體而言,突出部22可將更多導電性粒子42捕捉於突出部22內之凹部23。並且,凹部23內之導電性粒子會被充分地壓縮。因此,使得連接電阻降低,可靠性提升。並且,第2電極端子31之高度H2由於會成為規定範圍內之值,因此,足量之接著劑會流入第2電極端子31之間。因此,第1電極端子與第2電極端子會被牢固地接著。並且,本實施形態只要有ACF之壓接線就可適用。因此,可輕易地將本實施形態導入。
[實施例]
<1.實施例1>
(1-1.準備第1電子零件)
準備IC晶片作為第1電子零件20。於此IC晶片形成有複數個凸塊作為第1電極端子21。於第1電極端子21形成有高度H1=1.5μm之突出部 22。又,凸塊尺寸(亦即,第1電極端子21之平面形狀)為50μm×50μm之正方形。又,開口面積率為73.96%。因此,滿足要件2。又,第1電極端子21之維氏硬度為50Hv。
(1-2.準備第2電子零件)
準備撓性基板作為第2電子零件30。具體而言,對厚度25μm之聚醯亞胺基板(新日鐵化學公司製造CS12-25-00CE)進行Cu蝕刻後,實施Ni/Au鍍覆,藉此形成第2電極端子31。藉由以上之步驟,製作撓性基板。Ni/Au鍍覆係藉由電鍍法來進行。第2電極端子31之高度H1為12μm。因此,滿足要件3。又,第2電極端子31之寬度為50μm。因此,第1電極端子21與第2電極端子31之有效連接面積為1849μm2。此處,有效連接面積意指第2電極端子31相對於第1電極端子21之開口面積所佔的面積。
又,第2電極端子31之維氏硬度為150Hv。因此,電極端子之硬度比為33.3%。因此,滿足要件4。
(1-3.準備異向性導電膜(ACF))
將苯氧基樹脂(品名:YP50,新日鐵化學公司製造)36質量份、環氧硬化劑(品名:HP3941HP,旭化成化學公司製造)36質量份、環氧單體(品名:HP4032D,DIC公司製造)5質量份、橡膠改質環氧樹脂(品名:XER-91,JSR公司製造)15質量份、橡膠成分(品名:SG80H,長瀨化成公司製造)7質量份、偶合劑(品名:A-187,邁圖高新材料日本合同公司)、導電性粒子42(日本化學股份有限公司製)混合,藉此製作接著劑組成物。此處,導電性粒子42以個數密度成為3,500,000個/mm3之方式摻合於接著劑組成物。然後,藉由棒塗布將接著劑組成物塗布於另外準備之厚度38μ m的剝離處理PET膜,進行乾燥,藉此得到厚度40μm之異向性導電膜。
導電性粒子42之壓縮前粒徑為3.5μm,實施過Ni/Au鍍覆。因此,突出部高度/粒徑比為42.85%。因此,滿足要件1。又,粒徑/開口短邊長度比為8.14%。因此,滿足要件5。根據上述,可確認實施例1有滿足要件1~5。又,導電性粒子42之30%變形時的壓縮硬度為5500N/mm2。30%變形時之壓縮硬度係藉由島津製作所製微小壓縮測試機測得。另,於以下之各實施例、比較例使用之導電性粒子42之30%變形時的壓縮硬度皆為5500N/mm2
(1-4.製作異向性導電連接結構體)
依序積層第1電子零件20、異向性導電膜及第2電子零件30。此處,進行第1電子零件20及第2電子零件30之對位,以使第1電極端子21與第2電極端子31之位置一致。接著,透過緩衝材料等將加熱工具壓接於第2電子零件30上。接著,使用加熱工具將第1電極端子21與第2電極端子31熱壓接。藉由以上之步驟,製作異向性導電連接結構體10。此處,使熱壓接之條件為200℃-10sec-100MPa。亦即,以加熱工具之溫度自開始壓接於10秒鐘內成為200℃之方式將加熱工具升溫,且同時以100MPa之壓力將第1電極端子21與第2電極端子31熱壓接10秒鐘。異向性導電連接結構體10為了後述之評價而製作了複數個。將異向性導電連接結構體10之構成彙整表示於表1。
(1-5.初期電阻)
使用數位萬用電表(商品名:digital multimeter7561,横河電機公司製造)測量1-4.製作之異向性導電連接結構體10的連接電阻。將結果彙整表示於 表1。另,測量於複數個連接部分的初期電阻。將測量值之範圍示於表1。
(1-6.可靠性評價)
進行1-4.所製作之異向性導電連接結構體10的冷熱循環測試,藉此評價可靠性。冷熱循環測試係將異向性導電連接結構體10暴露於-40℃及100℃之環境各30分鐘,將以此為1循環之冷熱循環進行500循環。接著,將異向性導電連接結構體10之連接部分取出400個部位,計算此等中有不良(顯示出100mΩ以上之電阻的通道)之部位的數量。將結果彙整表示於表1。
(1-7.測量佔有面積率等)
自異向性導電連接結構體10剝除第1電極端子21,藉此使連接部分露出。接著,以SEM觀察連接部分,測量存在於凹部23內之導電性粒子42的數量(亦即,捕捉粒子數)及導電性粒子42之平均佔有面積率。平均佔有面積率之測量係藉由上述方法進行。亦即,於面視域觀察成為測量對象之50個連接部分,測量粒子佔有之面積亦即佔有面積。然後,基於此佔有面積,算出佔有面積率。又,導電性粒子42之捕捉粒子數係對50個連接部分測得之粒子數的算術平均值。將結果彙整表示於表1。
<2.實施例2>
於實施例2,除了使第1電極端子21之維氏硬度為90Hv外,其餘皆進行與實施例1同樣之處理。於實施例2,電極端子之硬度比為60%。因此,實施例2亦滿足要件4。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<3.實施例3>
於實施例3,除了使第1電極端子21之維氏硬度為20Hv外,其餘皆進行與實施例1同樣之處理。於實施例3,電極端子之硬度比為13.3%。因此,實施例3亦滿足要件4。惟,硬度比在30%以下,因此,確認到第1電極端子21之些微變形。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<4.實施例4>
於實施例4,除了使第2電極端子31之維氏硬度為500Hv外,其餘皆進行與實施例1同樣之處理。具體而言,以無電電鍍進行第2電極端子31之鍍覆,藉此得到上述維氏硬度。於實施例4,電極端子之硬度比為10%。因此,實施例4未滿足要件4。因此,於壓接後第1電極端子21大幅變形。然而,由於擴大了第1電極端子21之間距,故沒有發生短路。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<5.實施例5>
於實施例5,除了使第2電極端子31之寬度為40μm外,其餘皆進行與實施例1同樣之處理。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<6.實施例6>
於實施例6,除了使導電性粒子42之粒徑為3.0μm外,其餘皆進行與實施例1同樣之處理。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<7.實施例7>
除了使第2電極端子31之寬度為30μm外,其餘皆進行與實施例1同 樣之處理。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<8.實施例8>
除了使第2電極端子31之寬度為20μm外,其餘皆進行與實施例1同樣之處理。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<9.實施例9>
除了使第2電極端子31之高度H2為6μm外,其餘皆進行與實施例1同樣之處理。將異向性導電連接結構體10之構成及評價結果彙整表示於表1。
<10.比較例1>
除了使導電性粒子42之壓縮前粒徑為2.5μm外,其餘皆進行與實施例1同樣之處理。因此,突出部高度/粒徑比為60%,故要件1未被滿足。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
<11.比較例2>
除了使第1電極端子21之開口面積率為51.84%外,其餘皆進行與實施例1同樣之處理。因此,於比較例2,要件2未被滿足。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
<12.比較例3>
除了使突出部22之高度H1為3.0μm外,其餘皆進行與實施例1同樣之處理。因此,於比較例3,由於突出部高度/粒徑比為85.71%,故要件1未被滿足。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
<13.比較例4>
除了藉由研磨自第1電極端子21去除突出部22,使第2電極端子31 之寬度為20μm外,其餘皆進行與實施例1同樣之處理。因此,於比較例4,至少沒有滿足要件1。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
<14.比較例5>
除了使第2電子零件30為玻璃基板外,其餘皆進行與實施例1同樣之處理。於此玻璃基板上,形成有由ITO構成之第2電極端子31,第2電極端子31之高度H2為1μm以下。因此,於比較例5,要件3未被滿足。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
<15.參考例1>
除了藉由研磨自第1電極端子21去除突出部22,使第2電極端子31之寬度為40μm外,其餘皆進行與實施例1同樣之處理。因此,於參考例1,至少沒有滿足要件1。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
<16.參考例2>
除了藉由研磨自第1電極端子21去除突出部22,使第2電極端子31之寬度為30μm外,其餘皆進行與實施例1同樣之處理。因此,於參考例2,至少沒有滿足要件1。將異向性導電連接結構體10之構成及評價結果彙整表示於表2。
Figure 106110549-A0202-12-0021-2
Figure 106110549-A0202-12-0022-3
實施例1~3、5~9由於滿足所有要件1~6,因此,關於初期電阻、不良率及剝離強度皆得到良好之結果。於此等實施例,可藉由突出部22將足夠數量之導電性粒子42捕捉於凹部23內。並且,可充分壓縮此等導電性粒子42。因此,推斷為得到良好之結果。
惟,於實施例3中,在第1電極端子21觀察到些微變形。於實施例3,電極端子之硬度比在30%以下。亦即,於實施例3,雖然滿足要件4,但為30%以下之值。又,於實施例4,雖然亦可得到良好之結果,但第1電極端子21之變形進一步增加。於實施例4,電極端子之硬度比在10%以下。因此,要件4未被滿足。因此,從抑制電極端子變形之觀點而言,可知較佳為要件4有被滿足。
另一方面,於比較例1~5,特別是可靠性之評價差。推斷為比較例1~5由於要件1~3的某一者未被滿足,因此得到此種結果。於參考例1、2,沒有形成突出部22。因此,捕捉粒子數相對於實施例少。然而,得到與實施例幾乎不遜色之評價結果。另一方面,同樣地沒有形成突出部22之比較例4,評價結果差。其理由可舉參考例1、2之有效連接面積大。然而,於參考例1、2,由於另外需要將突出部22去除之作業,故會花費工夫於異向性導電連接。因此,可說較佳為實施例1~9。
以上,一邊參照附圖,一邊詳細說明有關本發明之較佳實施形態,但本發明並非限於該例。很明顯地若為本發明所屬之技術領域中具有通常知識者,便可在申請專利範圍記載之技術思想範疇內想到各種變更例或修正例,此等亦當然屬於本發明之技術範圍。
10‧‧‧異向性導電連接結構體
20‧‧‧第1電子零件
21‧‧‧第1電極端子
22‧‧‧突出部
23‧‧‧凹部
30‧‧‧第2電子零件
31‧‧‧第2電極端子
40‧‧‧接著劑層
41‧‧‧硬化樹脂層
42‧‧‧導電性粒子
H1‧‧‧突出部之高度
H2‧‧‧第2電極端子之高度

Claims (6)

  1. 一種異向性導電連接結構體,具備有表面形成有突出部之第1電極端子,第2電極端子,及含有將該第1電極端子與該第2電極端子導通之導電性粒子的異向性導電接著劑層;該突出部之高度相對於該導電性粒子之壓縮前粒徑的比未達60%,該第1電極端子之開口面積率為55%以上,該第2電極端子之高度為6μm以上,於該第1電極端子之表面,形成有被該突出部圍繞之凹部。
  2. 如申請專利範圍第1項之異向性導電連接結構體,其中,該第1電極端子之硬度相對於該第2電極端子之硬度的比大於10%。
  3. 如申請專利範圍第1項之異向性導電連接結構體,其中,該導電性粒子之壓縮前粒徑相對於該第1電極端子之凹部短邊長度的比未達10%。
  4. 如申請專利範圍第1項之異向性導電連接結構體,其中,存在於該第1電極端子之凹部的該導電性粒子之平均佔有面積率未達20%。
  5. 如申請專利範圍第1至4項中任一項之異向性導電連接結構體,其中,該突出部形成於該第1電極端子表面之整個外緣。
  6. 如申請專利範圍第1至4項中任一項之異向性導電連接結構體,其中,該第1電極端子為形成於第1電子零件之凸塊。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6945276B2 (ja) * 2016-03-31 2021-10-06 デクセリアルズ株式会社 異方性導電接続構造体
CN108987439A (zh) * 2018-06-21 2018-12-11 武汉华星光电半导体显示技术有限公司 显示面板和显示装置
TWI671921B (zh) * 2018-09-14 2019-09-11 頎邦科技股份有限公司 晶片封裝構造及其晶片
CN111179750A (zh) * 2019-12-12 2020-05-19 武汉华星光电技术有限公司 显示面板的结构和其制作方法
JP7334198B2 (ja) 2021-02-01 2023-08-28 プライムプラネットエナジー&ソリューションズ株式会社 電極端子および該電極端子を備えた二次電池

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004186411A (ja) * 2002-12-03 2004-07-02 Renesas Technology Corp 半導体装置およびその製造方法
JP2015028920A (ja) * 2013-06-26 2015-02-12 積水化学工業株式会社 接続構造体
JP2015146379A (ja) * 2014-02-03 2015-08-13 デクセリアルズ株式会社 接続体
TW201545988A (zh) * 2014-06-02 2015-12-16 Fujifilm Corp 氧化物粒子及其製造方法、氧化物粒子分散液、氧化物粒子薄膜的形成方法、薄膜電晶體以及電子元件
JP2016029698A (ja) * 2014-07-22 2016-03-03 デクセリアルズ株式会社 接続体、及び接続体の製造方法
TW201611446A (zh) * 2014-03-31 2016-03-16 Dexerials Corp 異向性導電膜及其製造方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2699951B2 (ja) * 1995-09-28 1998-01-19 日本電気株式会社 電子部品の接続構造及び製造方法
JPH1131698A (ja) 1997-07-14 1999-02-02 Texas Instr Japan Ltd 半導体装置、その製造方法及び実装構造
US5965064A (en) * 1997-10-28 1999-10-12 Sony Chemicals Corporation Anisotropically electroconductive adhesive and adhesive film
JP3624729B2 (ja) * 1998-04-06 2005-03-02 セイコーエプソン株式会社 Icチップ、ic構造体、液晶装置及び電子機器
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP2001028280A (ja) * 1999-07-13 2001-01-30 Three Bond Co Ltd 回路接続部材
US6451875B1 (en) * 1999-10-12 2002-09-17 Sony Chemicals Corporation Connecting material for anisotropically electroconductive connection
JP2002151551A (ja) * 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US7154206B2 (en) * 2002-07-31 2006-12-26 Kyocera Corporation Surface acoustic wave device and method for manufacturing same
JP4115832B2 (ja) * 2002-12-27 2008-07-09 東芝松下ディスプレイテクノロジー株式会社 半導体素子及び液晶表示パネル
JP2005093978A (ja) 2003-08-12 2005-04-07 Seiko Instruments Inc 半導体装置の製造方法
US7393771B2 (en) * 2004-06-29 2008-07-01 Hitachi, Ltd. Method for mounting an electronic part on a substrate using a liquid containing metal particles
JP3964911B2 (ja) * 2004-09-03 2007-08-22 松下電器産業株式会社 バンプ付き基板の製造方法
CN100495677C (zh) * 2005-03-29 2009-06-03 松下电器产业株式会社 倒装芯片封装方法及其焊锡点形成方法
KR101410108B1 (ko) * 2007-05-15 2014-06-25 히타치가세이가부시끼가이샤 회로 접속 재료 및 회로 부재의 접속 구조
EP2211596A4 (en) * 2007-10-02 2011-08-10 Hitachi Chemical Co Ltd CIRCUIT CONNECTION MATERIAL AND CIRCUIT TERMINAL CONNECTION STRUCTURE
JP2008047943A (ja) * 2007-11-01 2008-02-28 Renesas Technology Corp 半導体装置
US20090278213A1 (en) * 2008-05-08 2009-11-12 International Business Machines Corporation Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array
US8450753B2 (en) * 2008-09-29 2013-05-28 Sharp Kabushiki Kaisha Board module and method of manufacturing same
JP5533665B2 (ja) * 2008-11-28 2014-06-25 富士通株式会社 電子装置の製造方法、電子部品搭載用基板及びその製造方法
JP5599680B2 (ja) * 2010-08-27 2014-10-01 富士フイルム株式会社 導電接合構造、実装構造体及び導電接合方法
JP6057521B2 (ja) * 2012-03-05 2017-01-11 デクセリアルズ株式会社 異方性導電材料を用いた接続方法及び異方性導電接合体
KR102208591B1 (ko) * 2012-08-24 2021-01-27 데쿠세리아루즈 가부시키가이샤 이방성 도전 필름의 제조 방법 및 이방성 도전 필름
JP6321910B2 (ja) * 2013-03-26 2018-05-09 日東電工株式会社 封止シート、半導体装置の製造方法及び封止シート付き基板
KR101628440B1 (ko) * 2013-10-31 2016-06-08 제일모직주식회사 이방성 도전 필름 및 이를 이용한 반도체 장치
JP6750197B2 (ja) * 2015-07-13 2020-09-02 デクセリアルズ株式会社 異方性導電フィルム及び接続構造体
JP6945276B2 (ja) * 2016-03-31 2021-10-06 デクセリアルズ株式会社 異方性導電接続構造体

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004186411A (ja) * 2002-12-03 2004-07-02 Renesas Technology Corp 半導体装置およびその製造方法
JP2015028920A (ja) * 2013-06-26 2015-02-12 積水化学工業株式会社 接続構造体
JP2015146379A (ja) * 2014-02-03 2015-08-13 デクセリアルズ株式会社 接続体
TW201611446A (zh) * 2014-03-31 2016-03-16 Dexerials Corp 異向性導電膜及其製造方法
TW201545988A (zh) * 2014-06-02 2015-12-16 Fujifilm Corp 氧化物粒子及其製造方法、氧化物粒子分散液、氧化物粒子薄膜的形成方法、薄膜電晶體以及電子元件
JP2016029698A (ja) * 2014-07-22 2016-03-03 デクセリアルズ株式会社 接続体、及び接続体の製造方法

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