US20090278213A1 - Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array - Google Patents
Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array Download PDFInfo
- Publication number
- US20090278213A1 US20090278213A1 US12/117,000 US11700008A US2009278213A1 US 20090278213 A1 US20090278213 A1 US 20090278213A1 US 11700008 A US11700008 A US 11700008A US 2009278213 A1 US2009278213 A1 US 2009278213A1
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- United States
- Prior art keywords
- array
- dielectric layer
- semiconductor device
- electrodes
- conductive
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- G—PHYSICS
- G01—MEASURING; TESTING
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- G01N33/48—Biological material, e.g. blood, urine; Haemocytometers
- G01N33/50—Chemical analysis of biological material, e.g. blood, urine; Testing involving biospecific ligand binding methods; Immunological testing
- G01N33/53—Immunoassay; Biospecific binding assay; Materials therefor
- G01N33/543—Immunoassay; Biospecific binding assay; Materials therefor with an insoluble carrier for immobilising immunochemicals
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- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Definitions
- This invention relates to semiconductor device fabrication, and particularly to electrode arrays and methods of fabricating such arrays using a printing plate to arrange conductive particles in alignment with an array of electrodes.
- Biosensors have been described that include an array of electrode test sites in electrical connection with a plurality of conductive leads.
- the electrode test sites can be formed in a semiconductor wafer using photolithography and etch processing techniques. Further, the test sites can be coupled to associated detection circuitry via transistor switches using row and column addressing techniques employed, for example, in addressing dynamic random access memory (DRAM) or active matrix liquid crystal display (AMLCD) devices.
- DRAM dynamic random access memory
- AMLCD active matrix liquid crystal display
- MEAs microelectrode arrays
- current photolithography and etch techniques can be employed to pattern openings or vias in an insulation layer formed above the electrodes before filling those vias with a conductive material to form contacts to the electrodes.
- the ability of the photolithography and etch techniques to pattern small features is restricted by factors such as the resolution limits of the optical lithography system. It would therefore be desirable to develop a method for producing a large number of electrode arrays of relatively small dimensions at a relatively low cost.
- a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.
- a method of fabricating a semiconductor device comprises: contacting a face of a printing plate with a suspension comprising conductive particles to arrange the particles at predefined positions on the face of the printing plate; and contacting a dielectric layer residing upon an array of electrodes disposed upon a semiconductor substrate with the face of the printing plate to transfer the conductive particles to a position in or on the dielectric layer.
- FIGS. 1-3 illustrate one example of a semiconductor fabrication method in which a printing plate is used to arrange conductive particles in alignment with an array of electrodes formed upon a semiconductor substrate and coated by a dielectric layer;
- FIG. 4 illustrates one example of a semiconductor device comprising conductive particles arranged in alignment with an underlying array of electrodes.
- FIGS. 1-3 illustrate an exemplary embodiment of a method for fabricating an array of electrodes comprising conductive particles printed in alignment with an array of flat electrodes formed above a semiconductor substrate using, for example, a directed assembly method.
- This method can be used to economically form an array of densely packed electrodes across a large area in a relatively short period of time.
- the electrode arrays described herein can be interfaced with biological systems.
- an array of electrodes can be fabricated by obtaining a printing plate 10 that includes an array of recessed features 12 on the face of the printing plate 10 .
- the printing plate 10 can include a molded material that can replicate a three-dimensional relief structure by a molding process. Examples of suitable molded materials include but are not limited to as silicone, elastomers that can replicate a three-dimensional relief structure by a molding process (e.g. fluorinated polyethers), or combinations comprising at least one of the foregoing.
- the recessed features 12 of the printing plate 10 can be pre-selected to correspond with an array of flat electrodes formed upon a semiconductor substrate (discussed later).
- a suspension 14 comprising conductive particles 16 dispersed therein can be placed in contact with the face of the printing plate 10 .
- a particle 16 becomes embedded in each recessed feature 12 of the printing plate 10 , as depicted in FIG. 1 .
- the conductive particles 16 are purposely arranged in the array of recessed features 12 .
- the liquid can be removed to form a dry, filled printing plate 10 that can be stored until it is desirable to transfer the particles 16 to a substrate.
- the particles can be captured in protruding structures on the printing plate such as corners having 90° angles.
- the particles can be captured on binding sites on the printing plate having chemical functionalities that specifically attract and bind the particles. Examples of such chemical functionalities include but are not limited to polyelectrolytes.
- the particle suspension 14 shown in FIG. 1 can be formed by mixing the conductive particles 16 with a liquid.
- suitable liquids include but are not limited to ink, water, aqueous solutions comprising surfactants, alcohols (e.g., methanol, ethanol, propanol, and 2-propanol), and combinations comprising at least one of the foregoing (e.g., a water/alcohol mixture).
- the amount of particles present in the liquid can be about 0.01 to about 40% by weight, specifically about 0.01 to about 20% by weight, more specifically about 0.05 to about 10% by weight, and even more specifically about 0.1 to about 5% by weight.
- the conductive particles 16 include but are not limited to metals (e.g., Cu, Au, Ag, Pt, Ir, W, Ta, Pd, Al, Ni, and Co), conductive oxides such as indium tin oxide (ITO), and combinations comprising at least one of the foregoing metals.
- the particles 16 have a grain size dimension of less than or equal to about 100 micrometers (microns), more specifically less than or equal to about 100 nanometers (particles of this size are referred to as “nanoparticles”), to allow for the formation of densely packed electrode arrays.
- grain size dimension is herein defined as any straight lined segment that passes through the center of the particle and has its end points positioned at the surface of the particle.
- the particles 16 are depicted as being substantially spherical shaped, they can have other geometries such as cube shaped. Particles of such small dimensions can be synthesized by the reduction of the salts of the metals to be formed into particles.
- the particles 16 disposed in the recessed features 12 of the printing plate 10 can be transferred to a semiconductor topography comprising an array of flat electrodes 20 disposed upon a semiconductor substrate 18 and a dielectric layer 22 extending across the electrodes 20 .
- the substrate 18 can comprise, for example, single crystalline silicon.
- the flat electrodes 20 can be formed into an array or matrix upon the substrate 18 by depositing a conductive material, e.g., a transition metal, across the substrate 18 and patterning the conductive material using photolithography followed by an etch technique such as a dry, plasma etch.
- each electrode 20 has lateral dimensions (e.g., the width and the depth) of less than or equal to about 1000 micrometers, more specifically less than or equal to about 100 nanometers, such that a microelectrode array is formed.
- the dielectric layer 22 can be formed through the deposition of a thin dielectric material, e.g., a spin-deposited polymer, followed by the planarization of the surface of the dielectric material using, e.g., chemical mechanical polishing (CMP). The resulting dielectric layer 22 can have a substantially planar surface.
- suitable polymers for use in the dielectric layer 22 include but are not limited to polymethylmethacrylate (PMMA), polystyrene (PS), polyimide, polyurethanes (PU), spin-on glass, and combinations comprising at least one of the foregoing.
- PMMA polymethylmethacrylate
- PS polystyrene
- PU polyurethanes
- spin-on glass and combinations comprising at least one of the foregoing.
- the transfer of the conductive particles 16 can be accomplished by positioning the printing plate 10 upside down on top of the dielectric layer 22 such that the particles 16 are aligned to the underlying electrodes 20 . As a result of this positioning, the particles are “stamped” into the dielectric layer 22 to which they adhere due to their large surface interface. As shown in FIG. 3 , after the removal of the printing plate 10 , the conductive particles 16 remain in or on the dielectric layer 22 in their pre-selected positions, i.e., in alignment with the underlying array of electrodes 20 . In this manner, a conductive particle 16 is positioned above each electrode 20 . In an alternative embodiment, multiple particles could be printed on each electrode 20 . Subsequently, the substrate 18 and the dielectric layer 22 can be heated above the glass transition temperature, T g , of the dielectric material.
- the electrodes 20 can be spaced apart by equivalent distances, thus forming an equidistantly spaced array.
- the particles 16 can protrude into the dielectric layer 22 , and the dielectric layer 22 can be sufficiently thin to allow the particles 16 to be in electrical communication with corresponding ones of the array of flat electrodes 20 .
- a polymeric dielectric layer 22 can have a thickness of about equivalent to or less than the grain size dimension of the printed particles.
- the thickness of the dielectric layer 22 is less than the grain size dimension of the printed particles, specifically less than about 0.75 times the grain size dimension of the printed particles, or more specifically less than half the grain size dimension of the printed particles. Consequently, the protruding parts of the particles 16 can act as electrodes.
- the conductive particles described above can be functionalized with inorganic salts or ions such as calcium, chloride, inorganic phosphorous, potassium, selenium, and sodium; proteins such as poly-L-lysine, laminin, bilirubin, albumin, insuline, hemoglobin, collagen, fibronectin, and fibrinogen; enzymes such as alkaline phosphatase, lactate dehydrogenase, and glutamate oxalacetate transaminase; carbohydrates such as glucose; lipids such as triglycerides nucleic acids, e.g., DNA, RNA, m-RNA, t-RNA, or selected portions thereof; vitamins such as beta-carotene, bioflavonoids, biotin, choline, CoQ-10, essential fatty acids, folic acid, hesperidin, inositol, para-aminobenzoic acid, rutin, vitamin A, vitamin B complex, vitamin B-1 thiamine, vitamin B-2
- chemical functionalization of the particles is achieved by pre-treating the surface of the particles with a solution of a chemical moiety (e.g., proteins such as poly-L-lysine and larninin) in water for a duration of, for example, 2 hours.
- a chemical moiety e.g., proteins such as poly-L-lysine and larninin
- the particles are treated after they have been printed into the dielectric layer 22 .
- the terms “a” and “an” do not denote a limitation of quantity but rather denote the presence of at least one of the referenced items. Moreover, ranges directed to the same component or property are inclusive of the endpoints given for those ranges (e.g., “about 5 wt % to about 20 wt %,” is inclusive of the endpoints and all intermediate values of the range of about 5 wt % to about 20 wt %).
- Reference throughout the specification to “one embodiment”, “another embodiment”, “an embodiment”, and so forth means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the embodiment is included in at least one embodiment described herein, and might or might not be present in other embodiments. In addition, it is to be understood that the described elements may be combined in any suitable manner in the various embodiments. Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of skill in the art to which this invention belongs.
Abstract
Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.
Description
- 1. Field of the Invention
- This invention relates to semiconductor device fabrication, and particularly to electrode arrays and methods of fabricating such arrays using a printing plate to arrange conductive particles in alignment with an array of electrodes.
- 2. Description of Background
- Substantial attention has been directed to the design, implementation, and use of array-based electronic systems for carrying out and/or monitoring biological systems. For example, electronic biosensors of various types have been used to monitor the progress of certain biological systems. Biosensors have been described that include an array of electrode test sites in electrical connection with a plurality of conductive leads. The electrode test sites can be formed in a semiconductor wafer using photolithography and etch processing techniques. Further, the test sites can be coupled to associated detection circuitry via transistor switches using row and column addressing techniques employed, for example, in addressing dynamic random access memory (DRAM) or active matrix liquid crystal display (AMLCD) devices.
- There are ongoing efforts to increase the density of electrode arrays by reducing electrode and overlying lead or contact sizes to nanometer-or micrometer-scale dimensions, thereby producing “microelectrode arrays” (MEAs). However, it has been difficult to produce MEAs with very small dimensions using current top-down semiconductor fabrication methods. For example, current photolithography and etch techniques can be employed to pattern openings or vias in an insulation layer formed above the electrodes before filling those vias with a conductive material to form contacts to the electrodes. However, the ability of the photolithography and etch techniques to pattern small features is restricted by factors such as the resolution limits of the optical lithography system. It would therefore be desirable to develop a method for producing a large number of electrode arrays of relatively small dimensions at a relatively low cost.
- The shortcomings of the prior art are overcome and additional advantages are provided through the provision of electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.
- In another embodiment, a method of fabricating a semiconductor device comprises: contacting a face of a printing plate with a suspension comprising conductive particles to arrange the particles at predefined positions on the face of the printing plate; and contacting a dielectric layer residing upon an array of electrodes disposed upon a semiconductor substrate with the face of the printing plate to transfer the conductive particles to a position in or on the dielectric layer.
- Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
- The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
-
FIGS. 1-3 illustrate one example of a semiconductor fabrication method in which a printing plate is used to arrange conductive particles in alignment with an array of electrodes formed upon a semiconductor substrate and coated by a dielectric layer; and -
FIG. 4 illustrates one example of a semiconductor device comprising conductive particles arranged in alignment with an underlying array of electrodes. - The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
- Turning now to the drawings in greater detail, it will be seen that
FIGS. 1-3 illustrate an exemplary embodiment of a method for fabricating an array of electrodes comprising conductive particles printed in alignment with an array of flat electrodes formed above a semiconductor substrate using, for example, a directed assembly method. This method can be used to economically form an array of densely packed electrodes across a large area in a relatively short period of time. The electrode arrays described herein can be interfaced with biological systems. - As shown in
FIG. 1 , an array of electrodes can be fabricated by obtaining aprinting plate 10 that includes an array ofrecessed features 12 on the face of theprinting plate 10. Theprinting plate 10 can include a molded material that can replicate a three-dimensional relief structure by a molding process. Examples of suitable molded materials include but are not limited to as silicone, elastomers that can replicate a three-dimensional relief structure by a molding process (e.g. fluorinated polyethers), or combinations comprising at least one of the foregoing. Therecessed features 12 of theprinting plate 10 can be pre-selected to correspond with an array of flat electrodes formed upon a semiconductor substrate (discussed later). Asuspension 14 comprisingconductive particles 16 dispersed therein can be placed in contact with the face of theprinting plate 10. As thesuspension 14 is moved over theprinting plate 10, e.g., on a movable stage, aparticle 16 becomes embedded in eachrecessed feature 12 of theprinting plate 10, as depicted inFIG. 1 . In this manner, theconductive particles 16 are purposely arranged in the array ofrecessed features 12. When theparticles 16 have assumed their desired positions, the liquid can be removed to form a dry, filledprinting plate 10 that can be stored until it is desirable to transfer theparticles 16 to a substrate. In another embodiment, the particles can be captured in protruding structures on the printing plate such as corners having 90° angles. In yet another embodiment, the particles can be captured on binding sites on the printing plate having chemical functionalities that specifically attract and bind the particles. Examples of such chemical functionalities include but are not limited to polyelectrolytes. - The
particle suspension 14 shown inFIG. 1 can be formed by mixing theconductive particles 16 with a liquid. Examples of suitable liquids include but are not limited to ink, water, aqueous solutions comprising surfactants, alcohols (e.g., methanol, ethanol, propanol, and 2-propanol), and combinations comprising at least one of the foregoing (e.g., a water/alcohol mixture). The amount of particles present in the liquid can be about 0.01 to about 40% by weight, specifically about 0.01 to about 20% by weight, more specifically about 0.05 to about 10% by weight, and even more specifically about 0.1 to about 5% by weight. Examples of materials that can be present in theconductive particles 16 include but are not limited to metals (e.g., Cu, Au, Ag, Pt, Ir, W, Ta, Pd, Al, Ni, and Co), conductive oxides such as indium tin oxide (ITO), and combinations comprising at least one of the foregoing metals. In one embodiment, theparticles 16 have a grain size dimension of less than or equal to about 100 micrometers (microns), more specifically less than or equal to about 100 nanometers (particles of this size are referred to as “nanoparticles”), to allow for the formation of densely packed electrode arrays. The term “grain size dimension” is herein defined as any straight lined segment that passes through the center of the particle and has its end points positioned at the surface of the particle. Although theparticles 16 are depicted as being substantially spherical shaped, they can have other geometries such as cube shaped. Particles of such small dimensions can be synthesized by the reduction of the salts of the metals to be formed into particles. - Turning to
FIG. 2 , theparticles 16 disposed in therecessed features 12 of theprinting plate 10 can be transferred to a semiconductor topography comprising an array offlat electrodes 20 disposed upon asemiconductor substrate 18 and adielectric layer 22 extending across theelectrodes 20. Thesubstrate 18 can comprise, for example, single crystalline silicon. Theflat electrodes 20 can be formed into an array or matrix upon thesubstrate 18 by depositing a conductive material, e.g., a transition metal, across thesubstrate 18 and patterning the conductive material using photolithography followed by an etch technique such as a dry, plasma etch. In one embodiment, eachelectrode 20 has lateral dimensions (e.g., the width and the depth) of less than or equal to about 1000 micrometers, more specifically less than or equal to about 100 nanometers, such that a microelectrode array is formed. Thedielectric layer 22 can be formed through the deposition of a thin dielectric material, e.g., a spin-deposited polymer, followed by the planarization of the surface of the dielectric material using, e.g., chemical mechanical polishing (CMP). The resultingdielectric layer 22 can have a substantially planar surface. Examples of suitable polymers for use in thedielectric layer 22 include but are not limited to polymethylmethacrylate (PMMA), polystyrene (PS), polyimide, polyurethanes (PU), spin-on glass, and combinations comprising at least one of the foregoing. - The transfer of the
conductive particles 16 can be accomplished by positioning theprinting plate 10 upside down on top of thedielectric layer 22 such that theparticles 16 are aligned to theunderlying electrodes 20. As a result of this positioning, the particles are “stamped” into thedielectric layer 22 to which they adhere due to their large surface interface. As shown inFIG. 3 , after the removal of theprinting plate 10, theconductive particles 16 remain in or on thedielectric layer 22 in their pre-selected positions, i.e., in alignment with the underlying array ofelectrodes 20. In this manner, aconductive particle 16 is positioned above eachelectrode 20. In an alternative embodiment, multiple particles could be printed on eachelectrode 20. Subsequently, thesubstrate 18 and thedielectric layer 22 can be heated above the glass transition temperature, Tg, of the dielectric material. - The resulting alignment of the
conductive particles 16 with the array ofelectrodes 20 is better illustrated inFIG. 4 . In one embodiment, theelectrodes 20 can be spaced apart by equivalent distances, thus forming an equidistantly spaced array. As a result of the printing step, theparticles 16 can protrude into thedielectric layer 22, and thedielectric layer 22 can be sufficiently thin to allow theparticles 16 to be in electrical communication with corresponding ones of the array offlat electrodes 20. For example, apolymeric dielectric layer 22 can have a thickness of about equivalent to or less than the grain size dimension of the printed particles. In preferred embodiments, the thickness of thedielectric layer 22 is less than the grain size dimension of the printed particles, specifically less than about 0.75 times the grain size dimension of the printed particles, or more specifically less than half the grain size dimension of the printed particles. Consequently, the protruding parts of theparticles 16 can act as electrodes. - The conductive particles described above can be functionalized with inorganic salts or ions such as calcium, chloride, inorganic phosphorous, potassium, selenium, and sodium; proteins such as poly-L-lysine, laminin, bilirubin, albumin, insuline, hemoglobin, collagen, fibronectin, and fibrinogen; enzymes such as alkaline phosphatase, lactate dehydrogenase, and glutamate oxalacetate transaminase; carbohydrates such as glucose; lipids such as triglycerides nucleic acids, e.g., DNA, RNA, m-RNA, t-RNA, or selected portions thereof; vitamins such as beta-carotene, bioflavonoids, biotin, choline, CoQ-10, essential fatty acids, folic acid, hesperidin, inositol, para-aminobenzoic acid, rutin, vitamin A, vitamin B complex, vitamin B-1 thiamine, vitamin B-2 riboflavin, vitamin B-3 niacin/niacinamide, vitamin B-5 pantothenic acid, vitamin B-6 pyridoxine, vitamin B-9 folic acid, vitamin B-12 cyanocobalamine, vitamin B-15 dimethylglycine, vitamin B-17 leatrile or amygdalin, vitamin C, vitamin D, vitamin E, vitamin F unsaturated fats, vitamin G, vitamin J, vitamin K, and vitamin P; antibodies such as immunoglobulin A, immunoglobulin D, immunoglobulin E, immunoglobulin G, and immunoglobulin M; steroids and hormones such as cholesterol, cortisol, follicle stimulating hormone, growth hormone, leutinizing hormone, platelet-derived growth factor, fibroblast growth factor, parathyroid hormone, progesterone, prolactin, prostaglandins, testosterone, and thyroid stimulating hormone; aminoacids such as alanine, arginine, asparagine, aspartic acid, cysteine, glutamine, glutamic acid, glycine, histidine, isoleucine, leucine, lysine, methionine, phenylalanine, proline, serine, threonine, tryptophan, and valine; and aminoacid derivatives such as creatine.
- In one embodiment, chemical functionalization of the particles is achieved by pre-treating the surface of the particles with a solution of a chemical moiety (e.g., proteins such as poly-L-lysine and larninin) in water for a duration of, for example, 2 hours. In another embodiment, the particles are treated after they have been printed into the
dielectric layer 22. - As used herein, the terms “a” and “an” do not denote a limitation of quantity but rather denote the presence of at least one of the referenced items. Moreover, ranges directed to the same component or property are inclusive of the endpoints given for those ranges (e.g., “about 5 wt % to about 20 wt %,” is inclusive of the endpoints and all intermediate values of the range of about 5 wt % to about 20 wt %). Reference throughout the specification to “one embodiment”, “another embodiment”, “an embodiment”, and so forth means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the embodiment is included in at least one embodiment described herein, and might or might not be present in other embodiments. In addition, it is to be understood that the described elements may be combined in any suitable manner in the various embodiments. Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of skill in the art to which this invention belongs.
- While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Claims (20)
1. A semiconductor device comprising:
a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate;
a dielectric layer residing upon the semiconductor topography; and
at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.
2. The semiconductor device of claim 1 , wherein the at least one conductive particle has a grain size dimension of less than or equal to about 100 micrometers.
3. The semiconductor device of claim 2 , wherein the at least one conductive particle has a grain size dimension of less than or equal to about 100 nanometers
4. The semiconductor device of claim 1 , wherein the at least one conductive particle is a plurality of conductive particles in alignment with and in electrical communication with the array of electrodes.
5. The semiconductor device of claim 1 , wherein the at least one conductive particle comprises Cu, Au, Ag, Pt, Ir, W, Ta, Pd, Al, Ni, Co, a conductive oxide, or a combination comprising at least one of the foregoing.
6. The semiconductor device of claim 1 , wherein the dielectric layer has a substantially planar surface and comprises a polymer.
7. The semiconductor device of claim 1 , wherein the at least one conductive particle is substantially cube shaped or spherical shaped.
8. The semiconductor device of claim 1 , wherein the at least one conductive particle is functionalized with an inorganic ion, a protein, an enzyme, a nucleic acid, a vitamin, an antibody, a steroid, a hormone, an aminoacid, or a combination comprising at least one of the foregoing.
9. The semiconductor device of claim 1 , wherein each electrode in the array of electrodes has a lateral dimension of less than or equal to about 1000 micrometers.
10. A method of fabricating a semiconductor device, comprising:
contacting a face of a printing plate with a suspension comprising conductive particles to arrange the particles at predefined positions on the face of the printing plate; and
contacting a dielectric layer residing upon an array of electrodes disposed upon a semiconductor substrate with the face of the printing plate to transfer the conductive particles to a position in or on the dielectric layer.
11. The method of claim 10 , wherein the conductive particles have a grain size dimension of less than or equal to about 100 micrometers.
12. The method of claim 10 , wherein the conductive particles have a grain size dimension of less than or equal to about 100 nanometers.
13. The method of claim 10 , wherein the predefined positions on the face of the printing plate comprise recessed features, protruding structures, binding sites, or a combination comprising at least one of the foregoing.
14. The method of claim 10 , wherein the conductive particles are aligned to the array of electrodes during said contacting of the dielectric layer with the face of the printing plate.
15. The method of claim 10 , wherein the conductive particles comprises Cu, Au, Ag, Pt, Ir, W, Ta, Pd, Al, Ni, Co, a conductive oxide, or a combination comprising at least one of the foregoing.
16. The method of claim 10 , wherein the conductive particles are substantially cube shaped or spherical shaped.
17. The method of claim 10 , wherein the dielectric layer comprises a polymer.
18. The method of claim 10 , wherein the dielectric layer is planarized prior to being contacted with the face of the printing plate.
19. The method of claim 10 , wherein the conductive particles are functionalized with an inorganic ion, a protein, an enzyme, a nucleic acid, a vitamin, an antibody, a steroid, a hormone, an aminoacid, or a combination comprising at least one of the foregoing.
20. The method of claim 10 , wherein each electrode in the array of electrodes has a lateral dimension of less than or equal to about 1000 micrometers.
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US8546257B2 (en) | 2008-05-08 | 2013-10-01 | International Business Machines Corporation | Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9756100B2 (en) | 2013-03-15 | 2017-09-05 | Echostar Technologies L.L.C. | Placeshifting of adaptive media streams |
JP2015135878A (en) * | 2014-01-16 | 2015-07-27 | デクセリアルズ株式会社 | Connection body, method for manufacturing connection body, connection method and anisotropic conductive adhesive |
JP6945276B2 (en) * | 2016-03-31 | 2021-10-06 | デクセリアルズ株式会社 | Anisotropic conductive connection structure |
Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5586892A (en) * | 1994-03-10 | 1996-12-24 | Casio Computer Co., Ltd. | Electrically connecting structure |
US5616206A (en) * | 1993-06-15 | 1997-04-01 | Ricoh Company, Ltd. | Method for arranging conductive particles on electrodes of substrate |
US5891366A (en) * | 1994-05-10 | 1999-04-06 | Robert Bosch Gmbh | Anisotropically conducting adhesive, and process for producing an anisotropically conducting adhesive |
US5965064A (en) * | 1997-10-28 | 1999-10-12 | Sony Chemicals Corporation | Anisotropically electroconductive adhesive and adhesive film |
US6555408B1 (en) * | 1999-02-05 | 2003-04-29 | Alien Technology Corporation | Methods for transferring elements from a template to a substrate |
US6623579B1 (en) * | 1999-11-02 | 2003-09-23 | Alien Technology Corporation | Methods and apparatus for fluidic self assembly |
US6683663B1 (en) * | 1999-02-05 | 2004-01-27 | Alien Technology Corporation | Web fabrication of devices |
US20040229032A1 (en) * | 2002-04-25 | 2004-11-18 | Cobbley Chad A. | Electrical interconnect using locally conductive adhesive |
US20050082655A1 (en) * | 2003-10-06 | 2005-04-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20050110406A1 (en) * | 2003-10-24 | 2005-05-26 | Jeong Young-Chul | Interconnector, method for manufacturing a plasma display device using the same, and a plasma display device with the same |
US20050146053A1 (en) * | 2003-12-31 | 2005-07-07 | Lee Kevin J. | Wafer stacking with anisotropic conductive adhesive |
US20050150684A1 (en) * | 2004-01-14 | 2005-07-14 | Nobuaki Hashimoto | Electronic device and method for producing the same |
US20050191448A1 (en) * | 2004-02-26 | 2005-09-01 | Suh Min-Chul | Donor sheet, method of manufacturing the same, method of manufacturing TFT using the donor sheet, and method of manufacturing flat panel display device using the donor sheet |
US20050227475A1 (en) * | 2004-03-18 | 2005-10-13 | Yu-Chih Chen | Method of conductive particles dispersing |
US20060003097A1 (en) * | 2003-08-06 | 2006-01-05 | Andres Ronald P | Fabrication of nanoparticle arrays |
US20070001313A1 (en) * | 2003-02-05 | 2007-01-04 | Kozo Fujimoto | Method of interconnecting terminals and method for mounting semiconductor device |
US20070023908A1 (en) * | 2005-07-27 | 2007-02-01 | Palo Alto Research Center Incorporated | Method of fabricating self-assembled electrical interconnections |
US20070138460A1 (en) * | 2005-12-19 | 2007-06-21 | Samsung Electronics Co., Ltd. | Light emitting device with three-dimensional structure and fabrication method thereof |
US20070155184A1 (en) * | 2005-12-20 | 2007-07-05 | Sungsoo Yi | Method for producing a nanostructure such as a nanoscale cantilever |
US20070187840A1 (en) * | 2005-11-21 | 2007-08-16 | Dell Acqua-Bellavitis Ludovico | Nanoscale probes for electrophysiological applications |
US8028621B2 (en) * | 2008-05-02 | 2011-10-04 | International Business Machines Corporation | Three-dimensional structures and methods of fabricating the same using a printing plate |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6540127B2 (en) * | 2000-06-22 | 2003-04-01 | The Regents Of The University Of California | Electrostatic methods and apparatus for mounting and demounting particles from a surface having an array of tacky and non-tacky areas |
WO2006052104A1 (en) | 2004-11-12 | 2006-05-18 | Seoul National University Industry Foundation | Method for aligning or assembling nano-structure on solid surface |
US7846642B2 (en) | 2007-08-17 | 2010-12-07 | The University Of Massachusetts | Direct incident beam lithography for patterning nanoparticles, and the articles formed thereby |
US20090278213A1 (en) | 2008-05-08 | 2009-11-12 | International Business Machines Corporation | Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array |
-
2008
- 2008-05-08 US US12/117,000 patent/US20090278213A1/en not_active Abandoned
-
2012
- 2012-07-17 US US13/551,159 patent/US8546257B2/en not_active Expired - Fee Related
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5616206A (en) * | 1993-06-15 | 1997-04-01 | Ricoh Company, Ltd. | Method for arranging conductive particles on electrodes of substrate |
US5586892A (en) * | 1994-03-10 | 1996-12-24 | Casio Computer Co., Ltd. | Electrically connecting structure |
US5891366A (en) * | 1994-05-10 | 1999-04-06 | Robert Bosch Gmbh | Anisotropically conducting adhesive, and process for producing an anisotropically conducting adhesive |
US5965064A (en) * | 1997-10-28 | 1999-10-12 | Sony Chemicals Corporation | Anisotropically electroconductive adhesive and adhesive film |
US6555408B1 (en) * | 1999-02-05 | 2003-04-29 | Alien Technology Corporation | Methods for transferring elements from a template to a substrate |
US6683663B1 (en) * | 1999-02-05 | 2004-01-27 | Alien Technology Corporation | Web fabrication of devices |
US6623579B1 (en) * | 1999-11-02 | 2003-09-23 | Alien Technology Corporation | Methods and apparatus for fluidic self assembly |
US20040229032A1 (en) * | 2002-04-25 | 2004-11-18 | Cobbley Chad A. | Electrical interconnect using locally conductive adhesive |
US20070001313A1 (en) * | 2003-02-05 | 2007-01-04 | Kozo Fujimoto | Method of interconnecting terminals and method for mounting semiconductor device |
US20060003097A1 (en) * | 2003-08-06 | 2006-01-05 | Andres Ronald P | Fabrication of nanoparticle arrays |
US20050082655A1 (en) * | 2003-10-06 | 2005-04-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20050110406A1 (en) * | 2003-10-24 | 2005-05-26 | Jeong Young-Chul | Interconnector, method for manufacturing a plasma display device using the same, and a plasma display device with the same |
US20050146053A1 (en) * | 2003-12-31 | 2005-07-07 | Lee Kevin J. | Wafer stacking with anisotropic conductive adhesive |
US20050150684A1 (en) * | 2004-01-14 | 2005-07-14 | Nobuaki Hashimoto | Electronic device and method for producing the same |
US20050191448A1 (en) * | 2004-02-26 | 2005-09-01 | Suh Min-Chul | Donor sheet, method of manufacturing the same, method of manufacturing TFT using the donor sheet, and method of manufacturing flat panel display device using the donor sheet |
US20050227475A1 (en) * | 2004-03-18 | 2005-10-13 | Yu-Chih Chen | Method of conductive particles dispersing |
US20070023908A1 (en) * | 2005-07-27 | 2007-02-01 | Palo Alto Research Center Incorporated | Method of fabricating self-assembled electrical interconnections |
US20070187840A1 (en) * | 2005-11-21 | 2007-08-16 | Dell Acqua-Bellavitis Ludovico | Nanoscale probes for electrophysiological applications |
US20070138460A1 (en) * | 2005-12-19 | 2007-06-21 | Samsung Electronics Co., Ltd. | Light emitting device with three-dimensional structure and fabrication method thereof |
US20070155184A1 (en) * | 2005-12-20 | 2007-07-05 | Sungsoo Yi | Method for producing a nanostructure such as a nanoscale cantilever |
US8028621B2 (en) * | 2008-05-02 | 2011-10-04 | International Business Machines Corporation | Three-dimensional structures and methods of fabricating the same using a printing plate |
US20110244192A1 (en) * | 2008-05-02 | 2011-10-06 | International Business Machines Corporation | Three-dimensional structures and methods of fabricating the same using a printing plate |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090272285A1 (en) * | 2008-05-02 | 2009-11-05 | International Business Machines Corporation | Three-dimensional structures and methods of fabricating the same using a printing plate |
US8028621B2 (en) * | 2008-05-02 | 2011-10-04 | International Business Machines Corporation | Three-dimensional structures and methods of fabricating the same using a printing plate |
US8546257B2 (en) | 2008-05-08 | 2013-10-01 | International Business Machines Corporation | Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array |
US11564002B2 (en) | 2013-03-15 | 2023-01-24 | Sling TV L.L.C. | Automated replacement of video program content |
US11778257B2 (en) | 2013-03-15 | 2023-10-03 | Sling TV L.L.C. | Digital advertisement frequency correction |
US11956499B2 (en) | 2013-03-15 | 2024-04-09 | Sling TV L.L.C. | Automated replacement of stored digital content |
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US20120282771A1 (en) | 2012-11-08 |
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