CN111430513A - Preparation method of nano-column and preparation method of nano-column L ED device - Google Patents

Preparation method of nano-column and preparation method of nano-column L ED device Download PDF

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CN111430513A
CN111430513A CN202010354230.3A CN202010354230A CN111430513A CN 111430513 A CN111430513 A CN 111430513A CN 202010354230 A CN202010354230 A CN 202010354230A CN 111430513 A CN111430513 A CN 111430513A
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film
gan layer
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thin film
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CN111430513B (en
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刘召军
蒋府龙
李四龙
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Southern University of Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00111—Tips, pillars, i.e. raised structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The embodiment of the invention provides a preparation method of a nano-pillar and a preparation method of a nano-pillar L ED device, wherein the preparation method of the nano-pillar comprises the steps of evaporating a first thin film on the upper surface of a L ED wafer, wherein a L ED wafer comprises a P-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, carrying out thermal annealing treatment on the L ED wafer evaporated with the first thin film to enable the first thin film and the P-type GaN layer to form ohmic contact, depositing a second thin film on the upper surface of the first thin film, enabling the lower surface of the second thin film to be in contact with the first thin film, preparing a plurality of auxiliary nano-patterns on the upper surface of the second thin film, etching the second thin film through the auxiliary nano-patterns to form a plurality of masks, etching the first thin film, the P-type GaN layer, the quantum well active layer and the n-type GaN layer through the masks to form a plurality of L ED nano-pillars, and connecting two ends of a L ED nano-pillar with an electrode to achieve the effect of improving P-type ohmic contact performance of nano-L ED.

Description

Preparation method of nano-column and preparation method of nano-column L ED device
Technical Field
The embodiment of the invention relates to the technical field of micro-nano device manufacturing, in particular to a preparation method of a nano column and a preparation method of a nano column L ED device.
Background
The GaN-based nanoscale L ED can be used as a single photon light source in the fields of quantum computing, quantum communication and the like, and is characterized in that the GaN-based nanoscale L ED is taken as an example, the InGaN-based device has unique photoelectric characteristics due to the quantum-like characteristics of the InGaN well layer, which are strongly quantum-limited in the growth direction of the quantum well and in the direction parallel to the quantum well, and the stress on the quantum well is basically released when the size of the device is reduced to the nanoscale, and the quantum-limited Stark effect (QCSE) is eliminated.
Currently, the conventional method for preparing the nanopillar comprises electron beam exposure (EB L) or focused ion beam etching (FIB). taking the electron beam exposure (EB L) as an example, the electron beam exposure is to expose and develop a sample by using the shorter de Broglie wavelength of an electron beam, and further evaporate the electrode metal.
However, although the EB L process has high precision, the thickness of the electrode metal is limited, and thus the conductivity is weakened to some extent, resulting in poor P-type ohmic contact performance of the nano L ED.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a nano-pillar and a preparation method of a nano-pillar L ED device, so as to achieve the effect of improving the P-type ohmic contact performance of nano-L ED.
In a first aspect, an embodiment of the present invention provides a method for preparing a nanorod, including:
evaporating a first thin film on the upper surface of an L ED wafer, wherein the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the p-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate;
performing thermal annealing treatment on the L ED wafer evaporated with the first thin film to enable the first thin film and the p-type GaN layer to form ohmic contact;
depositing a second film on the upper surface of the first film, wherein the lower surface of the second film is in contact with the first film;
preparing a plurality of auxiliary nano patterns on the upper surface of the second film;
etching the second film through the auxiliary nano-patterns to form a plurality of masks;
and etching the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through the mask to form a plurality of L ED nano-pillars, wherein two ends of the L ED nano-pillars are used for being connected with electrodes.
Optionally, the etching the second film through the auxiliary nano-pattern to form a plurality of masks includes:
spraying a first etching gas along a first target direction, wherein the first target direction is a direction vertical to the upper surface of the second film, and the auxiliary nano pattern is used for blocking the first etching gas;
and the second film forms a plurality of masks under the etching of the first etching gas.
Optionally, the first etching gas is CHF3Or O2。
Optionally, the etching the first thin film, the p-type GaN layer, the quantum well active layer, and the n-type GaN layer through the mask to form a plurality of L ED nanorods includes:
injecting a second etching gas along a second target direction, wherein the second target direction is a direction vertical to the upper surface of the first film, and the mask is used for blocking the second etching gas;
the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer form a plurality of middle nano columns under the etching of the second etching gas;
the mask of the intermediate nanopillars is removed to form a plurality L ED nanopillars.
Optionally, the second etching gas is Cl2Or Cl3B。
Optionally, the removing the mask of the middle nanopillar to form a plurality of L ED nanopillars includes:
the mask is removed by hydrofluoric acid to form a plurality of L ED nanopillars.
Optionally, the first film is a silicon oxide film.
Optionally, the second film is an ITO film.
Optionally, the thermal annealing treatment temperature is 650-850 ℃, and the annealing time is 0.5-10 minutes.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a nanopillar L ED device, including:
evaporating a first thin film on the upper surface of an L ED wafer, wherein the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the p-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate;
performing thermal annealing treatment on the L ED wafer evaporated with the first thin film to enable the first thin film and the p-type GaN layer to form ohmic contact;
depositing a second film on the upper surface of the first film, wherein the lower surface of the second film is in contact with the first film;
preparing a plurality of auxiliary nano patterns on the upper surface of the second film;
etching the second film through the auxiliary nano-patterns to form a plurality of masks;
etching the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through the mask to form a plurality of L ED nano-pillars, wherein two ends of the L ED nano-pillars are used for being connected with electrodes;
a first electrode was fabricated at one end of the L ED nanopillar carrying the first thin film, and a second electrode was fabricated at one end of the n-type GaN layer of the L ED nanopillar to form a nanopillar L ED device, wherein the quantum well active layer was not in contact with the first and second electrodes.
The embodiment of the invention solves the problem of poor conductivity of a P-type GaN column electrode, and solves the problem of poor ohmic contact property of a P-type GaN column electrode, and a problem of poor conductivity of a P-type GaN column electrode, wherein a first film is evaporated on the upper surface of a L ED wafer, the L ED wafer comprises a P-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the P-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the P-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, the L ED wafer evaporated with the first film is subjected to thermal annealing treatment so that the first film is in contact with the P-type GaN layer, a second film is deposited on the upper surface of the first film, the lower surface of the second film is in contact with the first film, a plurality of auxiliary nanopattern patterns are formed on the upper surface of the second film, the second film is etched through the auxiliary nanopattern layer to form a plurality of auxiliary nanopattern electrodes, the nanopattern contact layer, the first film, the P-type GaN column electrode is etched with the P-type GaN column electrode, the nanopattern contact layer, the nanopattern electrode is etched with the nanopattern, the.
Drawings
Fig. 1 is a schematic flow chart of a method for preparing a nanopillar according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a L ED wafer with a first thin film deposited thereon according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of depositing a second film on the top surface of the first film according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a plurality of assistant nanopatterns formed on the upper surface of a second thin film according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating etching of a second film to form a plurality of masks according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a middle nanorod according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of an L ED nanorod according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of a method for manufacturing a nanorod L ED device according to a second embodiment of the present invention;
fig. 9 is a schematic structural diagram of a nanorod L ED device according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a sub computer program, or the like.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first film can be referred to as a second film, and similarly, a second film can be referred to as a first film, without departing from the scope of the present application. The first film and the second film are both films, but they are not the same film. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a schematic flow chart of a method for preparing a nano-pillar according to an embodiment of the present invention, which is applicable to a scenario of preparing L ED nano-pillars.
As shown in fig. 1, a method for preparing a nano-pillar according to a first embodiment of the present invention includes:
s110, evaporating a first thin film on the upper surface of an L ED wafer, wherein the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the p-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate.
Wherein, the L ED wafer can be a GaN-based blue light L ED wafer, and can also be a GaN-based green light L ED wafer, the L ED wafer of the embodiment is not specifically limited, and can be selected as required, wherein, the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, wherein, the upper surface of the p-type GaN layer is used as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is contacted with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is contacted with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is contacted with the upper surface of the substratexGa1XAn N quantum well active layer or a GaN quantum well active layer, and this embodiment is not particularly limited. The substrate may be a smooth substrate made of sapphire material, and the embodiment is not particularly limited.
The first thin film may be a conductive transparent material, such as an ITO (indium tin oxide) thin film, and the like, and is not limited herein.
Referring to fig. 2, fig. 2 is a schematic diagram of evaporating a first thin film on the upper surface of an L ED wafer according to the present embodiment, it can be seen from fig. 2 that a L ED wafer 300 includes a p-type GaN layer 301, a quantum well active layer 302, an n-type GaN layer 303, and a substrate 304, wherein the upper surface of the p-type GaN layer 301 is the upper surface of the L ED wafer 300, the lower surface of the p-type GaN layer 301 is in contact with the upper surface of the quantum well active layer 302, the lower surface of the quantum well active layer 302 is in contact with the upper surface of the n-type GaN layer 303, the lower surface of the n-type GaN layer 303 is in contact with the upper surface of the substrate 304, and the first thin film 200 is in contact with the upper surface of the L ED wafer 300.
And S120, carrying out thermal annealing treatment on the L ED wafer evaporated with the first thin film so as to enable the first thin film and the p-type GaN layer to form ohmic contact.
In this step, after the thermal annealing treatment of the first film is performed, the first film can already form a good ohmic contact with the P-type GaN layer of the L ED wafer, optionally, the temperature of the thermal annealing treatment is 650 ℃ to 850 ℃, the annealing time is 0.5 minute to 10 minutes, the temperature and the time of the thermal annealing treatment can be selected according to needs, and the embodiment is not particularly limited.
In an alternative embodiment, the thermal annealing of the L ED wafer evaporated with the first thin film comprises:
placing the L ED wafer with the first film evaporated thereon in a closed space, wherein the closed space has a preset proportion of nitrogen and oxygen, and performing thermal annealing treatment on the L ED wafer with the first film evaporated thereon in the closed space.
In this embodiment, the L ED wafer with the first thin film deposited thereon is placed in a closed space with a predetermined ratio of nitrogen to oxygen for thermal annealing, alternatively, the predetermined ratio may be 4:1, and the predetermined ratio may be set as required to achieve the best annealing effect, which is not limited in this embodiment.
S130, depositing a second thin film on the upper surface of the first thin film, wherein the lower surface of the second thin film is in contact with the first thin film.
The second film may be an insulating film, such as silicon oxide or silicon dioxide, and is not limited herein. Alternatively, the second film may be a single layer or a plurality of layers, and is not particularly limited herein. Specifically, the second film may be deposited on the first film by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Referring to fig. 3, fig. 3 is a schematic diagram illustrating a second film deposited on the upper surface of the first film according to the present embodiment. As can be seen from fig. 3, the second film 100 is deposited on the upper surface of the first film 200, and the upper surface of the first film 200 is in contact with the lower surface of the second film 100.
And S140, preparing a plurality of auxiliary nano patterns on the upper surface of the second film.
Wherein, the auxiliary nano pattern is a nano pattern for assisting in etching the second film. Specifically, the auxiliary nanopattern may be prepared on the upper surface of the second thin film using a nanoimprint process. Referring to fig. 4, fig. 4 is a schematic diagram illustrating a plurality of auxiliary nanopatterns formed on an upper surface of a second film according to the present embodiment. As can be seen from fig. 4, a plurality of auxiliary nanopatterns 400 are formed on the upper surface of the second film 100.
S150, etching the second film through the auxiliary nanometer patterns to form a plurality of masks.
The mask is used for assisting in etching the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer. The mask may include an auxiliary nano-pattern and a second thin film; it is also possible to include only the second film. Specifically, when the mask comprises the auxiliary nano pattern and the second film, the auxiliary nano pattern and the second film are used as the mask after the second film is etched; when the mask includes the second film, the imprint resist of the auxiliary nano-pattern may be removed first, and the second film may be left as the mask.
In an alternative embodiment, etching the second thin film through the auxiliary nano-pattern to form a plurality of masks includes:
spraying a first etching gas along a first target direction, wherein the first target direction is a direction vertical to the upper surface of the second film, and the auxiliary nano pattern is used for blocking the first etching gas; and the second film forms a plurality of masks under the etching of the first etching gas.
Where the first etching gas is used to etch the second film, but the gas that is not capable of etching the auxiliary nano-patterns and the p-type GaN layer of the L ED wafer, may be selected as desired, and the second film forms a mask under the etching of the first etching gas3Or O2。
Referring to fig. 5, fig. 5 is a schematic diagram illustrating that the second film is etched to form a plurality of masks according to this embodiment. As can be seen from fig. 5, a plurality of masks 500 are formed after etching the second thin film.
And S160, etching the first thin film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through the mask to form a plurality of L ED nano columns, wherein two ends of the L ED nano columns are used for being connected with electrodes.
In this step, the L ED nanopillars include a first thin film, a p-type GaN layer, a quantum well active layer, and an n-type GaN layer.
In an alternative embodiment, etching the first thin film, the p-type GaN layer, the quantum well active layer, and the n-type GaN layer through the mask to form a plurality of L ED nanopillars includes:
the method comprises the steps of enabling a first film to be etched, enabling a first etching gas to be sprayed along a first target direction, enabling the first film to be perpendicular to the upper surface of the first film, enabling a mask to be used for blocking the first etching gas, enabling the first film, a p-type GaN layer, a quantum well active layer and an n-type GaN layer to form a plurality of middle nano columns under the etching of the first etching gas, and removing the mask of the middle nano columns to form a plurality of L ED nano columns.
Wherein the second etching gas is used for etching the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer, but cannot etch the mask and the substrateThe gas (c) may be selected as required. Optionally, the second etching gas includes, but is not limited to, Cl2Or Cl3B. The intermediate nano-pillar refers to a result obtained by etching the first thin film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through a mask, wherein the intermediate nano-pillar comprises the mask, the first thin film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a middle nanorod according to the present embodiment. As can be seen from fig. 6, the intermediate nanopillar 50 includes a mask 500, a first thin film 200, a p-type GaN layer 301, a quantum well active layer 302, and an n-type GaN layer 303.
Referring to fig. 7, fig. 7 is a schematic structural view of an L ED nanorod according to this embodiment, it can be seen from fig. 7 that the L ED nanorod 40 includes a first thin film 200, a p-type GaN layer 301, a quantum well active layer 302, and an n-type GaN layer 303, wherein the first thin film 200 has formed a good ohmic contact with the p-type GaN layer 301.
According to the technical scheme, a first thin film is evaporated on the upper surface of a L ED wafer, wherein the L ED wafer comprises a P-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the P-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the P-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate, the L ED wafer evaporated with the first thin film is subjected to thermal annealing treatment to enable the first thin film to be in ohmic contact with the P-type GaN layer, a second thin film is deposited on the upper surface of the first thin film, a plurality of auxiliary nano patterns are formed on the upper surface of the second thin film, the second thin film is etched through the auxiliary nano patterns to form a plurality of masks, the first thin film, the P-type GaN layer, the n-type GaN layer and the substrate are in contact with the quantum well, and the conductivity of the first thin film is improved by etching, and the quantum well.
Example two
Fig. 8 is a schematic flowchart of a method for manufacturing a nanorod L ED device according to a second embodiment of the present invention, where this embodiment is applicable to a scenario for manufacturing a nanorod L ED device.
As shown in fig. 8, the method for preparing the nanopillar L ED device provided in this embodiment may include:
s210, evaporating a first thin film on the upper surface of an L ED wafer, wherein the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the p-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate.
And S220, carrying out thermal annealing treatment on the L ED wafer evaporated with the first thin film so as to enable the first thin film and the p-type GaN layer to form ohmic contact.
And S230, depositing a second film on the upper surface of the first film, wherein the lower surface of the second film is in contact with the first film.
And S240, preparing a plurality of auxiliary nano patterns on the upper surface of the second film.
And S250, etching the second film through the auxiliary nano pattern to form a plurality of masks.
And S260, etching the first thin film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through the mask to form a plurality of L ED nano columns, wherein two ends of the L ED nano columns are used for being connected with electrodes.
And S270, preparing a first electrode at one end of the L ED nano-pillar carrying the first thin film, and preparing a second electrode at one end of the n-type GaN layer of the L ED nano-pillar to form a nano-pillar L ED device, wherein the quantum well active layer is not in contact with the first electrode and the second electrode.
In this step, a first electrode was fabricated at one end of the L ED nanopillar carrying the first thin film, and a second electrode was fabricated at one end of the n-type GaN layer of the L ED nanopillar.
In an alternative embodiment, preparing a first electrode at one end of the L ED nanopillar carrying the first thin film and preparing a second electrode at one end of the n-type GaN layer of the L ED nanopillar may include:
putting the substrate and the connected L ED nano-columns as a sample into a solution (such as alcohol or isopropanol), performing ultrasonic treatment in the alcohol or isopropanol, transferring the L ED nano-columns into the solution by using the energy of the ultrasonic treatment to form a suspension carrying the L ED nano-columns, dripping the suspension on an insulating substrate by using a burette or a pipette gun, and heating the insulating substrate to evaporate the solution to leave dried L ED nano-columns, putting the insulating substrate with the L ED nano-columns placed in a Focused Ion Beam (FIB) device or an electron beam exposure (EB L) device to prepare a first electrode at one end of the L ED nano-column carrying a first thin film and prepare a second electrode at one end of an n-type GaN layer of the L ED nano-column, thereby forming a nano-column L ED device.
Specifically, a scanning electron microscope in a Focused Ion Beam (FIB) device or an electron beam exposure (EB L) device finds two ends of a L ED nanopillar, then picks up a first electrode placed at one end of the L ED nanopillar carrying a first thin film, picks up a second electrode placed at one end of an n-type GaN layer of the L ED nanopillar, and bombards a region of the first electrode wrapped with the first thin film and a region of the second electrode wrapped with the n-type GaN layer by the focused ion beam or the electron beam, thereby obtaining a nanopillar L ED device.
Referring to fig. 9, fig. 9 is a schematic structural view of a nanorod L ED device provided in this embodiment, as can be seen from fig. 9, a nanorod L ED device includes a first electrode 10, a second electrode 20, and L ED nanorods 40, wherein the first electrode 10 is fabricated at one end of the L ED nanorods 40 carrying the first thin film 200, the second electrode 20 is fabricated at one end of the n-type GaN layer 303 of the L ED nanorods 40, and the quantum well active layer 302 is not in contact with the first electrode 10 and the second electrode 20, wherein the first thin film 200 may be in contact with the first electrode 10 alone, or the first thin film 200 and the p-type GaN layer 301 may be in contact with the first electrode 10 at the same time.
The technical scheme of the embodiment of the invention is that a first thin film is evaporated on the upper surface of a L ED wafer, wherein the L ED wafer comprises a P-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the P-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the P-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate, thermal annealing treatment is carried out on the L ED wafer evaporated with the first thin film to enable the first thin film to be in ohmic contact with the P-type GaN layer, a second thin film is deposited on the upper surface of the first thin film, the lower surface of the second thin film is in contact with the first thin film, a plurality of auxiliary nano patterns are prepared on the upper surface of the second thin film, the second thin film is etched to form a plurality of masks, the first thin film, the P-type GaN layer, the n-type GaN layer is in contact with the n-type GaN layer, the quantum well is etched to form a plurality of auxiliary nano-type GaN layer, the quantum-type GaN.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A method for preparing a nano-pillar, comprising:
evaporating a first thin film on the upper surface of an L ED wafer, wherein the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the p-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate;
performing thermal annealing treatment on the L ED wafer evaporated with the first thin film to enable the first thin film and the p-type GaN layer to form ohmic contact;
depositing a second film on the upper surface of the first film, wherein the lower surface of the second film is in contact with the first film;
preparing a plurality of auxiliary nano patterns on the upper surface of the second film;
etching the second film through the auxiliary nano-patterns to form a plurality of masks;
and etching the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through the mask to form a plurality of L ED nano-pillars, wherein two ends of the L ED nano-pillars are used for being connected with electrodes.
2. The method of claim 1, wherein said etching the second film through the auxiliary nanopattern to form a plurality of masks comprises:
spraying a first etching gas along a first target direction, wherein the first target direction is a direction vertical to the upper surface of the second film, and the auxiliary nano pattern is used for blocking the first etching gas;
and the second film forms a plurality of masks under the etching of the first etching gas.
3. The method of claim 2, wherein the first etching gas is CHF3Or O2。
4. The method of claim 1, wherein the etching the first film, the p-type GaN layer, the quantum well active layer, and the n-type GaN layer through the mask to form a plurality of L ED nanopillars comprises:
injecting a second etching gas along a second target direction, wherein the second target direction is a direction vertical to the upper surface of the first film, and the mask is used for blocking the second etching gas;
the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer form a plurality of middle nano columns under the etching of the second etching gas;
the mask of the intermediate nanopillars is removed to form a plurality L ED nanopillars.
5. The method of claim 4, wherein the second etching gas is Cl2Or Cl3B。
6. The method of claim 1, wherein the removing the mask of the intermediate nanopillars to form a plurality L ED nanopillars comprises:
the mask is removed by hydrofluoric acid to form a plurality of L ED nanopillars.
7. The method of any of claim 1, wherein the first film is a silicon oxide film.
8. The method of any of claim 1, wherein the second film is an ITO film.
9. The method according to any one of claims 1 to 8, wherein the thermal annealing treatment is carried out at a temperature of 650 ℃ to 850 ℃ and for an annealing time of 0.5 minutes to 10 minutes.
10. A method for preparing a nano-pillar L ED device, comprising:
evaporating a first thin film on the upper surface of an L ED wafer, wherein the L ED wafer comprises a p-type GaN layer, a quantum well active layer, an n-type GaN layer and a substrate, the upper surface of the p-type GaN layer serves as the upper surface of the L ED wafer, the lower surface of the p-type GaN layer is in contact with the upper surface of the quantum well active layer, the lower surface of the quantum well active layer is in contact with the upper surface of the n-type GaN layer, and the lower surface of the n-type GaN layer is in contact with the upper surface of the substrate;
performing thermal annealing treatment on the L ED wafer evaporated with the first thin film to enable the first thin film and the p-type GaN layer to form ohmic contact;
depositing a second film on the upper surface of the first film, wherein the lower surface of the second film is in contact with the first film;
preparing a plurality of auxiliary nano patterns on the upper surface of the second film;
etching the second film through the auxiliary nano-patterns to form a plurality of masks;
etching the first film, the p-type GaN layer, the quantum well active layer and the n-type GaN layer through the mask to form a plurality of L ED nano-pillars, wherein two ends of the L ED nano-pillars are used for being connected with electrodes;
a first electrode was fabricated at one end of the L ED nanopillar carrying the first thin film, and a second electrode was fabricated at one end of the n-type GaN layer of the L ED nanopillar to form a nanopillar L ED device, wherein the quantum well active layer was not in contact with the first and second electrodes.
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