200403122 玖、發明說明： 【發明所屬之技術領域】 及半導體裝置之製造 本發明係與研磨方法及研磨裝置 方法有關。 【先前技術】 隨著半導體設計法則的縮小化，在㈣4方面— 看到如下現象··配線材料由銘⑷）改使用銅（Cu)、又 膜使用介電率更低的材料。造成前述材料㈣的理由;^、.彖 在A说線及SiQ2等層間絕緣蘭料方面，在面對配線延遲 ，問越時’已經來到其能力的極限。就材料而t，在前述 變遷上半導體元件的開發有長足的進步，但隨著材料的變 更也使半導體製造之加工處理也有很大變遷。 譬如在使用Cu作為配線材料的情形時，在A1配線世代中 所廣X使用的配線之乾式姓刻法，並不適用於抗腐钱性低 的材料Cu上。因此，如針對以也採用和μ相同的乾式蝕刻 法進行加工時’則在低壓高溫的硬體裝置上，必須在接近 臨界狀態下實施才行，故並不適合於量產加工處理。因此， 現在在Cu配線加工處理中所廣泛使用的是被稱為金屬鑲嵌 法的技術’其係在層間絕緣膜201上形成阻擋膜202後，埋 入 Cu 203，接著利用 CMP (Chemical Mechanical Polishing， 化學機械研磨）法，把與配線無關的部份（場區部份）除去； 而該層間絕緣膜201係已經實施著溝、穴加工者。 CMP技術係從較早之0.5 μιη之設計法則起就被使用，係 屬於一般較成熟的技術。在CMP技術應用的初期階段，被 研磨材係使用層間絕緣膜。然而，在CMP技術上，係具有 84033 403122 :案：存性’尤其被稱為侵蝕現象者乃一大問題；而該圖 :!ί性係指’在配線密度不同的部位會產生研磨速度的 二井寺，而孩侵姓現象係指在配線較密的部位的研磨加速 現象。而前述各現象，、經由如下的各種改進，現在已經在 才街上達到適於I產水準的程度了，而前述改進係指， 更的改良、CMP消耗品(研磨液.研磨墊)的改善。而前述 改進係與被作為被研磨材之層間絕緣膜有關，特別是盘以 s1〇2為主之材料有_。“卩，其係與被研磨材叫屬於較 為硬質之材料，在CMP參數上具有較大自由度有關。 然而，金屬鑲嵌法的研磨材料為金屬材Cu ;其與Si〇2相 較’、係屬於軟質、具有黏性的材料。Ku具有容易與研 磨液中所含之酸或鹼反應的性質。基於前述Cu所具有的性 質，使用CMP之Cu配線過程中，會產生如下問題。 (1)侵姓 此亦為層間絕緣膜（氧化膜）之CMP上所存在的問題。在配 線密度大的圖案方面，係對研磨速度不同之異種材料進行 研磨，因此隨著研磨速度快的部份被研磨，研磨速度慢的 部份會被施加局部性壓力，基於此種相乘效果，會使研磨 速度的落差十分顯著。其結果則如圖19所示，在配線密度 大的圖案方面，會形成凹陷般的形狀。 (2)淺碟化 淺碟化係指，具有30 μιη寬度以上之寬配線部被加速度研 磨的現象，其配線形狀係如圖2〇所示，呈現凹入的形狀。 淺碟化係因研磨壓力的增加、及研磨墊的變形而呈加速度200403122 (ii) Description of the invention: [Technical field to which the invention belongs] and manufacturing of semiconductor devices The present invention relates to a polishing method and a polishing device method. [Prior art] With the shrinking of semiconductor design rules, in respect of ㈣4-see the following phenomenon ··························································· The use of copper (Cu) as a wiring material and a lower dielectric constant are used for the film. Reasons for the foregoing materials ㈣; ^,. 彖 In terms of interlayer insulation blues such as A-line and SiQ2, in the face of wiring delay, the time has elapsed 'has reached the limit of its ability. As far as materials are concerned, the development of semiconductor components has made great progress in the aforementioned changes, but with the change of materials, the processing of semiconductor manufacturing has also changed greatly. For example, when Cu is used as a wiring material, the dry-type engraving method of wiring used by X in the A1 wiring generation is not applicable to Cu, which is a material with low corrosion resistance. Therefore, when processing is performed using the same dry etching method as that of µ, it is necessary to implement the processing at a near-critical state on a hardware device having a low pressure and a high temperature, so it is not suitable for mass production processing. Therefore, a technique called a damascene method is widely used in Cu wiring processing. It is a method in which a barrier film 202 is formed on an interlayer insulating film 201, and then Cu 203 is embedded. Then, CMP (Chemical Mechanical Polishing, The chemical-mechanical polishing) method removes portions (field areas) that are not related to the wiring; and the interlayer insulating film 201 has been processed with grooves and holes. CMP technology has been used since the earlier design rules of 0.5 μm, and is a generally mature technology. In the initial stage of CMP technology application, the material to be polished uses an interlayer insulating film. However, in the CMP technology, the system has 84033 403122: the case: the existence of 'especially known as the phenomenon of erosion is a major problem; and the figure:! Ί refers to' the polishing speed will occur at different locations of wiring density Erjing Temple, and the phenomenon of child invasion of surname refers to the phenomenon of accelerated grinding in the densely-wired parts. The above-mentioned phenomena have now reached a level suitable for the I production level on the street through various improvements as described below, and the aforementioned improvements refer to further improvements, improvements in CMP consumables (polishing liquids, polishing pads). . The aforementioned improvement is related to the interlayer insulation film used as the material to be polished, especially the material mainly composed of s1 02. "Well, it is related to the material being ground being a harder material, which has a greater degree of freedom in CMP parameters. However, the grinding material of the metal inlay method is the metal material Cu; it is compared with Si02. It is a soft and viscous material. Ku has the property of easily reacting with acids or bases contained in the polishing liquid. Based on the properties of the aforementioned Cu, the following problems occur during the Cu wiring process using CMP. (1) This is also a problem in the CMP of the interlayer insulating film (oxide film). In the pattern of high wiring density, the different materials with different polishing speeds are polished, so the parts with high polishing speeds are polished. Local pressure is applied to the slow grinding speed. Based on this multiplication effect, the drop in grinding speed is very significant. As a result, as shown in Figure 19, in the pattern with high wiring density, depressions will be formed. (2) Shallow dishing Shallow dishing refers to a phenomenon in which a wiring portion having a width of 30 μm or more is subjected to acceleration grinding, and the shape of the wiring is concave as shown in FIG. 20. It was due to increased dishing of the polishing pressure, the polishing pad and the deformation of the shape acceleration
84033 200403122 進行為了抑制淺碟化，採取低加重研磨雖具有效果，但 採低加重研磨的情形時，其研磨速度會下降，無法適應量 產加工處理的要求。 (3) 配線（Cu)凹入 如圖21所不，配線（c…凹入係指，配線在層間絕緣膜 形成的配線溝或穴中，未填滿層間絕緣膜高度的狀態。因 此上述铋蝕、淺碟化也都是凹入的一部份。侵蝕、淺碟 化係主要依存於研磨壓力，此外，構成研磨液之酸或鹼所 產生之化學性浸蝕，會造成。的凹入（受到浸蝕）。如前所 ^由於提高壓力會加速侵#、淺碟化，因此如欲使用於 量產加工處理時，則有必要針對為了提升研磨速度而提高 化學性反應速度進行檢討研究。然而，就壞處而言，即^ 之化學性浸蝕所產生之浸蝕會發產成凹入現象。 (4) 層間絕緣膜的破壞 就配線延遲的對策而言1了使配線低阻抗化外，還可 降低層間絕緣膜的容量；而具體的方法為在層間絕緣膜使 用低介電率材料。-般而言，層間絕緣膜之低介電率化係 傾向於把材料做成多孔膜，但使材料多孔膜化的同時，卻 會導致材料的脆弱化，進而造成機械性強度劣化。而且， 就其壞處而T，如圖22所示，由於在實施CuCMp時的施加 壓力，而使層間絕緣膜的之低介電率材料有遭破壞之虞。 如上所述，在利用金屬鑲嵌法的Cu配線之形成方面，係 具有如下問題：因侵蝕、淺碟化、凹入等而導致配線部膜 厚減小及平坦化之劣化。在配線部膜厚減小方面，由於對 84033 200403122 配線施加了設計值以上之電流密纟，因Λ，譬#會導致電 子遷移(ΕΜ)耐性的劣化’或造成配線可靠度的極：傷害。 再者，具有侵料非平坦性之形狀會謗發圖案形成不良 現象。此外，在微影王序上，絕對階差的增大會使膽㈣化 of Focus，焦點深度）減小，故無法形成所希望的圖案。此 一傾向，在被更微細化的圖案上尤其顯著。又，絕對階差 係隨著配線層數的增加而會被更凸顯出來。譬如，在堆積 有階差部之佈局的情形，其凹陷加上階差量，使絕對階差 變大。而JL ’階差的增加係相當於層間絕緣膜的溝部，因 此在實施Cu CMP時，在其階差部會殘留Cu;結果如圖23 所示，會形成半導體元件配線短路的致命性缺陷。 此外，如在層間絕緣膜使用低介電率材料時，如上所述， 由於低介電率材料係脆弱的材料，CMp所施加的加重會破 壞低介電率材料，造成致命性的破壞。 最近，在可支援低介電率材料之研磨、平坦化方法方面， 已經開發出使用電解研磨之Cu研磨方法；而該電解研磨係 採用低壓或無壓者。該技術係利用電解施加，把作為被研 磨膜之Cu表面改變為容易研磨之變質層，或無研磨即溶解 的變質層’來達到Cu的平坦化。然而，前述低壓電解研磨 技術，屬於CMP延長線上之硬體型態者仍然很多；足以解 決上述問題點的低壓電解研磨技術尚未問世。 因此，就現況而言，足以解決如下問題，且可形成具有 良好形狀且可靠度高之鑲嵌配線的手法係尚未確立；而前 述問題係··侵蝕、淺碟化、凹入等之形狀缺陷，及脆弱之 -10- 84033 200403122 低介電率材料易受破壞等問題。 針對雨述先前之種種問題，因而有了本發明的產生；本 發明之目的在於提供—種研磨方法及研磨裝置，其係在利 用研磨方式使金屬膜平坦化之際， 可谷易且有效地除去多 餘的金屬膜，且具有高精度者。 ^又百又，本發明之目的在於提 供一種半導體裝置之製造方法，並 、 係使用則述研磨方法及 研磨裝置者。 【發明内容】 為了達成上述目的，與本發明有關之研磨方法之特徵係 在於：在電解液中，使形成有金屬膜之基板與對向電極呈 對向配置，並介以電解液對金屬膜進行通電，同時以硬質 研磨墊研磨金屬膜表面，來把金屬膜研磨。 如上所述，在與本發明有關 > 府、 、十叔啕關又研曆万法中，係使用硬皙 研磨墊：利用比CMP更低上許多的低壓力來研磨金屬膜， 因此可防止金屬膜之過度研磨’可避免侵姓、淺碟化、凹 入等之形狀缺陷的產生。再者’可減輕對基板的壓力，故 不會有對脆弱材料造成破壞等缺點之虞。因此，可達成更 高精度的研磨。 又，為了達成上述目的，與本發明有關之研磨裝置之特 徵為：在電解液中把形成絲板上之金屬膜進行研磨的研 磨裝置；其係具備：對向電極，其係與基板呈對向配置者； 電源，其係以基板為陽極、以對向電極為陰極，來施加電 壓者；及硬質研磨塾，JL係方其k μ、见# + /、乐在基板上h動來研磨金屬膜者。 具有上述結構之與本發明有關之研磨裝置，係使用硬質 -11 - 84033 200403122 研磨墊為研磨墊，利用比CMp更低上許多的低壓力來研磨 至屬膜Q此可防止金屬膜之過度研磨，可避免侵蝕、淺 碟化、凹人等4形狀缺陷的產生。再者，可減輕對基板的 壓力，故不會有對脆弱材料造成破壞等缺點之虞。因此， 可達成更fSJ精度的研磨。 又，為了達成上述目的，與本發明有關之半導體裝置之 製造方法，其特徵係具有··配線溝形成工序，其係用於在 絕緣胰上形成金屬配線者，而該絕緣膜係形成於基板上 者；金屬膜形成工序，其係在絕緣膜上形成金屬膜，來把 配線溝埋入者；及金屬膜研磨工序；其係用於把形成於絕 緣膜上之金屬膜進行研磨者；在金屬膜研磨工序方面，係 在電解液中，使形成有金屬膜之基板與對向電極呈對向配 置，並介以電解液對金屬膜進行通電，同時以硬質研磨墊 研磨金屬膜表面，來把金屬膜研磨。 上述與本發明有關之半導體裝置之製造方法，在形成金 屬配線之際，係使用硬質研磨墊，以比先前之CMP更低上 許多的低壓力來研磨金屬膜，因此可防止金屬膜之過度研 磨，如此則可避免侵蝕、淺碟化、凹入等之形狀缺陷的產 生；該金屬膜係形成於絕緣膜上者。再者，由於可減輕對 基板的壓力，故不會有對脆弱材料造成破壞等缺點之虞。 因此，可達成更高精度的研磨，形成良好的金屬配線。 【實施方式】 以下，參考圖式，針對與本發明有關之研磨方法及研磨 裝置，及半導體裝置之製造方法作說明。又，為了容易了 -12- 84033 200403122 解，以下之圖式可能會與實際之縮尺有不同之處。再者， =發明並不受限於下列說明，只要在不超出本發明要旨的 範圍内，則可進行適當變更。 與本發明有關之研磨方法之特徵係在於：在電解液中， 使办成有金屬膜之基板與對向電極呈對向配置，並介以電 解液對金屬膜進行通電，同時以硬質研磨塾研磨金屬膜表 面’來把金屬膜研磨。 ，又，與本發明有關之研磨裝置之特徵4:在電解液中把 形成於基板上（金屬膜進行研磨的研磨裝置；其係且備： 對向電極，其係與基板呈對向配置者；電源，其係絲板 為陽極、以上述對向電極為陰極，來施加電壓者；及硬質 研磨墊，其係在基板上滑動來研磨金屬膜者。 又，與本發明有關之半導體裝置之製造方法，其特徵係 具有：配線溝形成工序，其係用於在絕緣膜上形成金屬配 線者，而ΐ亥絕緣膜係形成於基板上者；金屬膜形成工序， 係在絶緣胰上形成金屬膜，來把配線溝埋入者；及金屬 膜研磨工序’其係用於把形成於絕緣膜上之金屬膜進行研 厝者；在金屬膜研磨工序方Φ，係在電解液中，使形成有 金屬膜之基板與對向電極呈對向配置，並介以電解液對全 屬膜進行通電，同時以硬f研磨塾研磨金屬膜表面， 金屬膜研磨。 以下係以半導體配線工序的Cu配線之平坦化的情形，亦 即，以在基板上形成之金屬膜為Cu膜的情形為例作說明。 首先，針對以先前技術CuCMp把在基板上形成之Cu膜進行 84033 -13 - 200403122 研磨、平坦化時所發生之問題作說明。以Cu CMP把在基板 上形成之Cu膜進行研磨、平坦化後，會發生如下缺點。亦 即，在以Cu CMP把Cu膜進行研磨、平坦化的情形時，會發 生如:钱、淺碟化、配線凹入、及層間絕緣膜的破壞等加工 處理不良，及導致半導體元件之明顯缺陷。 以下，以侵银發生時之情形為例，來說明加工處理不良 所造成的影響。譬如，在半導體基板上形成以配線時，如 發生侵蝕，則侵蝕會使層間絕緣膜及Cu膜減小，因而導致 配、、泉纠面和的減小。譬如，寬〇12 、高〇12 之配線的 6形，如因侵蝕而減小〇 〇5 μιη膜厚，則被侵蝕後之配線上 被她加的電流密度為設計電流密度的丨7倍。如以布拉克之 公式來計算配線壽命的話，則#電流密度電流密度增加到 1.7么的h形，假设電流密度指數n=2，則被侵蝕後之配線 =配線壽命約為設計上之配線壽命的1/3。又，由於配線容 里〈低介甩率化’使配線層間絕緣膜（配線高度）及配線寬朝 向薄膜化及縮小化方向發展，因而使電子遷移（腸)更一步 加速化H配線壽命之設計邊際幾乎處於零的狀態， Q此’配線*命的減少_配線可靠度而言，有成為致命性 缺陷之虞。 卜由万、配、、泉層數的增加，使得侵蝕等配線形成不良 2集成化時引起配線間短路（配線短路）；X，在Cu CMP 鑲嵌加工處理上，亦可 ^ T此發生層間絕緣膜剥離（破壞）現象。 s如，在製作丰壤#曲^ 、岐衣置的情形時，前述缺陷會大幅度影 響半導體晶片之功能由+ 艮率，而陷入無法確保良品晶片的狀 84033 -14- 200403122 況。其可使半導體晶片之生產力日月顯變差，而招徠極大損 害亦即，使用Cu配線及低介電率膜來製造微細化之半導 體元件時，如使用CuCMP鑲嵌加工處理，則在上述製造加 工處理中會產生缺陷；且在配線可靠度方面，也會產生因 配線膜厚之薄膜化所導致的EM耐性之劣化問題。 因此，為了解決上述問題，本發明提供如下之研磨方法 及研磨裝置，而其係以取代CuCMp之電解研磨技術來作為84033 200403122 In order to suppress shallow dishing, low-heavy grinding is effective. However, when low-heavy grinding is used, the grinding speed will decrease and it cannot meet the requirements of mass production processing. (3) Wiring (Cu) is recessed as shown in Figure 21. Wiring (c ... recession) refers to the state where the wiring is not filled with the height of the interlayer insulating film in the wiring trench or hole formed by the interlayer insulating film. Therefore, the above bismuth Erosion and shallow dishing are also part of the recession. Erosion and shallow dishing are mainly dependent on the grinding pressure. In addition, the chemical erosion caused by the acid or alkali that constitutes the polishing liquid will cause the recession ( Etching). As previously mentioned, increasing pressure will accelerate invasion and shallow dishing. Therefore, if you want to use it for mass production processing, it is necessary to conduct a review and study to increase the chemical reaction speed in order to increase the polishing speed. However, In terms of the disadvantages, that is, the etching caused by the chemical etching of ^ will produce a concave phenomenon. (4) The destruction of the interlayer insulation film is a measure of the delay of the wiring. In addition to reducing the resistance of the wiring, it can also Reduce the capacity of the interlayer insulating film; the specific method is to use a low dielectric material for the interlayer insulating film.-Generally speaking, the low dielectric constant of the interlayer insulating film tends to make the material a porous film, but makes the material While the porous membrane is being formed, It will cause the material to be fragile, which will cause the deterioration of mechanical strength. In addition, as shown in Figure 22, due to the pressure applied during the implementation of CuCMp, the low-dielectric material of the interlayer insulating film has a disadvantage. As described above, the formation of Cu wiring by the damascene method has the following problems: the reduction of the thickness of the wiring portion and the deterioration of the planarization due to erosion, shallow dishing, and recession. In terms of reducing the film thickness of the wiring part, because a current density of more than the design value is applied to the 84033 200403122 wiring, Λ, such as # will cause deterioration in the resistance to electron migration (EM), or extreme reliability of the wiring: injury. In addition, shapes with intrusive non-flatness will illuminate the formation of bad patterns. In addition, in the lithography king sequence, the increase of the absolute step will reduce the gallbladder of Focus, so it cannot be formed. The desired pattern. This tendency is particularly noticeable in a pattern that is more refined. In addition, the absolute step system becomes more prominent as the number of wiring layers increases. For example, in the case where a layout with step difference portions is stacked, the depression is added to the step amount to increase the absolute step difference. The increase in the step difference of JL 'is equivalent to the groove portion of the interlayer insulating film. Therefore, when Cu CMP is performed, Cu remains in the step portion; as shown in FIG. 23, a fatal defect of a short circuit of a semiconductor element wiring may be formed. In addition, if a low-dielectric material is used for the interlayer insulating film, as described above, since the low-dielectric material is a fragile material, the aggravation applied by the CMP will destroy the low-dielectric material and cause fatal damage. Recently, a Cu polishing method using electrolytic polishing has been developed to support a method of polishing and flattening a low-dielectric-constant material, and the electrolytic polishing is performed using a low voltage or a non-pressure one. This technology uses electrolytic application to change the surface of Cu, which is the film to be ground, to a deteriorated layer that can be easily polished, or a modified layer that dissolves without polishing, to achieve Cu flattening. However, the aforementioned low-voltage electrolytic polishing technology still has many hardware types belonging to the CMP extension line; low-voltage electrolytic polishing technology that is sufficient to solve the above problems has not yet come out. Therefore, as far as the current situation is concerned, it is enough to solve the following problems, and the technique system that can form a good shape and high reliability damascene wiring has not been established; and the aforementioned problems are: · shape defects such as erosion, shallow dishing, recession, etc. And fragile -10- 84033 200403122 low dielectric constant materials are vulnerable to damage and other problems. The present invention has been made in view of various problems previously mentioned in the rain report. The object of the present invention is to provide a polishing method and a polishing device, which can be easily and effectively used when the metal film is flattened by a polishing method. Remove excess metal film with high accuracy. The object of the present invention is to provide a method for manufacturing a semiconductor device, and to describe a polishing method and a polishing device using the method. [Summary of the Invention] In order to achieve the above-mentioned object, the polishing method related to the present invention is characterized in that: in the electrolytic solution, the substrate on which the metal film is formed is opposed to the counter electrode, and the metal film is interposed with the electrolytic solution. When the current is applied, the surface of the metal film is polished with a hard polishing pad to polish the metal film. As described above, in the Fuchu, Shishu, Shishuguan and other methods related to the present invention, a hard polishing pad is used: the metal film is polished with a lower pressure than CMP, which can prevent it Excessive grinding of the metal film can avoid the occurrence of shape defects such as surrogacy, shallow dishing, and depression. Furthermore, since it can reduce the pressure on the substrate, there is no risk of causing damage to fragile materials. Therefore, more accurate polishing can be achieved. In addition, in order to achieve the above-mentioned object, the polishing device related to the present invention is characterized in that: a polishing device for polishing a metal film formed on a wire plate in an electrolytic solution; the polishing device is provided with a counter electrode which is opposed to a substrate To the configurator; the power supply, which uses the substrate as the anode and the counter electrode as the cathode, to apply voltage; and hard grinding 塾, JL is square k μ, see # + /, please move on the substrate to grind Metal film person. The polishing device related to the present invention having the above structure uses a hard -11-84033 200403122 polishing pad as a polishing pad, and uses a much lower pressure than CMP to grind to a metal film. This can prevent excessive polishing of the metal film. It can avoid the occurrence of 4 shape defects such as erosion, shallow dish, and concave. Furthermore, since the pressure on the substrate can be reduced, there is no risk of causing damage to fragile materials. Therefore, polishing with more fSJ accuracy can be achieved. In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a wiring groove forming step for forming a metal wiring on an insulating pancreas, and the insulating film is formed on a substrate. The former; a metal film forming process that forms a metal film on an insulating film to bury wiring trenches; and a metal film polishing process that is used to polish a metal film formed on an insulating film; In terms of the metal film polishing process, the substrate on which the metal film is formed is opposed to the counter electrode in the electrolyte, and the metal film is energized through the electrolyte. At the same time, the surface of the metal film is polished with a hard polishing pad. Grind the metal film. In the method for manufacturing a semiconductor device related to the present invention, when forming metal wiring, a hard polishing pad is used to polish the metal film with a much lower pressure than the previous CMP, so it can prevent excessive polishing of the metal film. In this way, the occurrence of shape defects such as erosion, shallow dishing, and recessing can be avoided; the metal film is formed on the insulating film. Furthermore, since the pressure on the substrate can be reduced, there is no risk of causing damage to fragile materials. Therefore, it is possible to achieve more accurate polishing and form a good metal wiring. [Embodiment] Hereinafter, a polishing method and a polishing apparatus related to the present invention, and a manufacturing method of a semiconductor device will be described with reference to the drawings. Also, to make it easier to understand -12- 84033 200403122, the following drawings may differ from the actual scale. In addition, the invention is not limited to the following description, and may be appropriately changed as long as it does not exceed the gist of the invention. The polishing method related to the present invention is characterized in that: in the electrolytic solution, the substrate provided with the metal film and the counter electrode are arranged opposite to each other, and the metal film is energized through the electrolytic solution, and at the same time hard grinding is performed. The metal film surface is polished to grind the metal film. Also, the polishing device related to the present invention is characterized in 4: a polishing device formed on a substrate (a metal film for polishing in an electrolytic solution; its system and preparation): a counter electrode, which is arranged opposite to the substrate A power supply, which uses a wire plate as an anode and the counter electrode as a cathode to apply voltage; and a hard polishing pad, which slides on a substrate to polish a metal film. Also, the semiconductor device related to the present invention The manufacturing method is characterized in that: a wiring trench forming step is used to form metal wiring on an insulating film, and a holamine insulating film is formed on a substrate; a metal film forming step is to form a metal on an insulating pancreas Film, to bury wiring trenches; and the metal film polishing process, which is used to study the metal film formed on the insulating film; in the metal film polishing process, the Φ is formed in the electrolyte to form The substrate with the metal film and the counter electrode are oppositely arranged, and all the films are energized through the electrolyte, and the surface of the metal film is polished with hard f grinding and polishing, and the metal film is polished. The following is based on semiconductor wiring The case of sequential Cu wiring planarization, that is, a case where a metal film formed on a substrate is a Cu film is described as an example. First, a Cu film formed on a substrate is subjected to 84033 -13 with the prior art CuCMp. -200403122 Explains the problems that occur during polishing and planarization. After Cu film is used to polish and planarize a Cu film formed on a substrate, the following disadvantages occur. That is, when Cu film is polished, In the case of flattening, processing failures such as money, shallow dishing, wiring recession, and destruction of interlayer insulating films, and obvious defects in semiconductor devices may occur. The following is the case of silver invasion as an example. To explain the impact caused by poor processing. For example, when wiring is formed on a semiconductor substrate, if erosion occurs, the erosion will reduce the interlayer insulation film and the Cu film, which will result in a reduction in the distribution, the spring correction surface, and the reduction. For example, if the shape of the wiring of width 〇12 and height 〇12 is reduced by 0.05 μm due to erosion, the current density applied to the wiring after erosion is 7% of the design current density. If you calculate the wiring life by using Braque's formula, the #current density current density will increase to 1.7? H, if the current density index n = 2, then the wiring after erosion = the wiring life is about the wiring on the design The life is 1/3. Moreover, the "low dielectric loss rate" of the wiring capacity makes the wiring interlayer insulation film (wiring height) and wiring width develop toward thinning and reducing, thus accelerating the electron migration (gut). The design margin of the H wiring life is almost zero, and the reduction of the wiring life is the risk of a fatal defect in wiring reliability. The increase in the number of layers, distribution, and springs makes the Defective formation of wiring such as erosion 2 Short circuit between wirings (wiring short circuit) during integration; X, Cu Cu CMP damascene processing can also cause interlayer insulation film peeling (destruction). For example, in the case of making Feng Yang # 曲 ^, Qi clothing, the aforementioned defects will greatly affect the function of the semiconductor wafer, and fall into the state of failure to ensure a good wafer 84033 -14- 200403122. It can make the productivity of semiconductor wafers worsen day by day, and attracts great damage, that is, when using Cu wiring and low dielectric film to manufacture fine-grained semiconductor elements, if using CuCMP damascene processing, the above manufacturing processing Defects occur during processing, and in terms of wiring reliability, the problem of deterioration in EM resistance due to thinning of the wiring film thickness also occurs. Therefore, in order to solve the above-mentioned problems, the present invention provides the following grinding method and grinding device, which are replaced by electrolytic grinding technology instead of CuCMp.
Cu研磨技術者。首先，針對與本發明有關之研磨裝置作說 明。圖1係與本發明有關之研磨裝置u之概略結構圖。如圖 1所717，研磨裝置11係在電解液槽16内配置有基板17 ;而該 電解液槽16係儲存有電解液£者；而該基板17係表面形成有Cu grinding technician. First, a grinding apparatus related to the present invention will be described. FIG. 1 is a schematic configuration diagram of a polishing apparatus u related to the present invention. As shown in Figure 717, the polishing device 11 is configured with a substrate 17 in an electrolytic solution tank 16; and the electrolytic solution tank 16 stores an electrolytic solution; and the substrate 17 is formed on the surface thereof.
Cu膜18，且係以未在圖中顯示之基板保持構件所保持者。 又，在電解液槽16内，在基板17上以特定之間隔，研磨墊 Μ係與定盤13呈對向配置；而該定盤13係形成圓盤狀，2 系對向％極（陰極）15之保持構件。在此，研磨墊Μ係被固 疋及保持於疋盤13上之基板丨7側。又，定盤13係利用未在 ，中顯示之移動手段，可朝上下方向進行移動；亦即，在 維持與基板17之平行之狀態下接近，或往離開方向移動。 此外，定盤13亦利用未在圖中顯示之旋轉手段，以定盤^ <中心軸為中心可進行旋轉。又，在定盤13上之内徑侧之 垃置，係固定配置有對向電極（陰極）15。而且，在基板17與 子向私極1 5上係連接有用於與兩者連接之電解施加電 12。 ·、 以下，針對利用前述研磨裝置u來研磨以膜18之研磨方 84033 15 200403122 法作說明；而該Cu膜18係在基板17上形成者。 、:先，在裝滿電解㈣之電解液槽16中設置作為被 接著，以該基板17為陽極，介以電解液E，^ ㈣之間施加電解電壓，使電解電流流通，來對c: 二Γτ:電。如此一來’作為陽極接受電解作用之⑽ 接三 知極氧化，而在表層形成铜氧化物覆膜_)。 孩銅氧化物和電解液种所含的銅絡合體形成劑進行 反應，料形成銅絡合體；經由該銅絡合體形成劑物質， 而在c_18表㈣成高電性阻抗層、非溶性絡合體覆膜、 覆膜等變質層。如上所述，利用電解施加電源12, ::板17與對向電極之間施加電壓，可使銅絡合體化速度 卜在本發明（研磨万法中，在進行上述電解研磨的 同時，利用研磨塾14把⑽18表面實施磨平。前述磨平作 業係利用研磨墊14，以特定之壓力按壓被陽極氧化之Cu膜 18的表面’並進行滑動，以此方式來除去變質層覆膜，使 底材CU露出’ ^後把該Cu所露出的部份進行再電解；而該 變質層覆膜係存在於具有凹凸之⑽18之凸部的表層者。 雖”、：也依照銅絡合體的種類而有所不同，但銅絡合體與 未絡合體化之銅（下稱未絡合體化銅）之間的密接性非常 ^ '由笔解液槽16中電解液E的對流，銅絡合體從未絡合 化銅（亦即，基板17上之未絡合體化銅）脫離，而進入電解 液E中呈浮游狀。然而，光靠電解液£的對流，銅絡合體從 未絡合體化銅脫離的速度遲緩；4了提升銅絡合體除去之 84033 -16- 200403122 速度’因此對基板1 7按壓、滑動研磨塾14，來磨平cu膜1 § 表面；而該研磨墊14係安裝於定盤13上者。具體而言，係 以特定之壓力把定盤13對Cu膜18表面進行按壓，以該定盤 13之中心軸為中心，使之在與基板17平行的面内進行旋轉。 如此，則可提高銅絡合體從基板17脫離的速度，使銅絡合 月豆以良好效率從基板17脫離，使基板17表面變為平坦化。 又，本發明中之磨平作業係包含：擦動功能、削平功能、 擦拭功能。 接著，反覆實施前述電解研磨、磨平作業之週期，則可 使形成於基板17上之Cii膜18被研磨，邁向平坦化。 、=上述研磨方法來研磨以膜18，則可用安定、均一之電 “在度分佈貫施通電，及以自将沾 、 ^心私及以艮妤的研磨率、研磨條件進行 在上述研磨方法中，為了提高平坦化能力，如圖】所示， 可使用含有研磨粒19之電解液。在電解液中混入研磨液來 =仃磨平，則可以良好效率使銅絡合體從基㈣脫離，使 基板1 7表面平坦化。 又，磨平作業係在—邊驅動研磨墊14本身旋轉等，一邊 進订者。在進行磨平時，亦、 向旋轉。 土板11任研磨墊之驅動方 .此外’在本發明中’以上逑方式進行電解研磨之際，研 研磨的^ 在本發明中，基於低壓 汗㈣硯點，使用硬質材料作為研磨塾， 精度的研磨與平坦化。 5見更π 84033 200403122 而在先前之Cu CMP方面，由於要施加高壓，且為了应被 研磨材之間具有良好追雜，而使用軟研磨塾，來提高被 研磨材之面内的均一性。因，匕，實際上犧牲了若干程度的 平坦性。 相對的，在採用所謂低壓電解研磨的情形時，由於電解 液與電解施加電源的作用，而形成與未絡合體化銅密接性 弱的銅絡合體；而該低壓電解研磨係指，利用上述研磨原 理，把基板上所形成之金屬膜進行電解研磨的同時，以研 磨，進行磨平，來使之平坦化。目此，採用低壓電解研磨 的h开y時，可用比Cu CMP所施加的研磨電壓4 PM〜7 psi (1 PSI約為70 g/cm2)更低的低壓力來進行研磨。此外，以 1·5 PSI以下之研磨壓力亦可進行研磨，及可充份達到量產 適用範圍之研磨速度（> 500 nm/min);而該15psi以下之研 磨壓力係被視為破壞多孔系低介電率材料的界限值。再 者，即使使用1·0 PSI以下之研磨壓力，亦可達成適合量產 之研磨速度（> 5000 A/min)。 然而，通常之低壓電解研磨係沿襲CMP技術者，為了顧 及對被研磨材之追從性，而使用聚氨酯泡或鞣絨系等較為 軟之研磨墊，因此難以實現更高精度之平坦性。 在此，把焦點放在低壓電解研磨中之研磨墊上；由於低 壓電解研磨可如上述般，以極低壓進行研磨，因此不需要 為了確保被研磨材之面内的均一性，而考慮被研磨材與研 磨塾之間的追從性。而前述確保被研磨材之面内的均一 性’在CMP技術上係屬一項問題。亦即，在低壓電解研磨 -18- 84033 200403122 方面，在设計時是可以忽視研磨之均一性的。 因此’在本發明中，為了實現更高精度的研磨及平坦化， 而使用硬S研磨墊來作為研磨墊。由於使用硬質研磨墊， 故可有效抑制在Cu CMp中常見之侵蝕、淺碟化、凹入及低 介電率材料之破壞問題，而實現更高精度的平坦性。 以下以具體例說明本發明中可使用的硬質研磨塾之物性 及型態。 <研磨墊之物性> (常溫時） 硬度 ··蕭氏D硬度為60以上 全度 ：〇_80 g/cm3以上 壓縮率 ：1.0以下 彈性恢復率：70%以下 壓縮強度：7 kPa以下（每1 111111厚度進行0 01%壓縮時） 才污氏率 ：10 kPa以上 <研磨墊之表面狀態> 表面粗度：與研磨粒之大小約相同，標準為0.2 μιη以下 表面形狀：可任意進行溝之加工。但形成溝時，溝之加 工邵應維持在晶片尺寸之30%以下。又，溝加工寬度為5 nm 、溝高度為研磨墊高度之80%以下，或1〇 nm以下為佳。 <研磨墊之型態> 尺寸：晶片面積之4倍以上 <代表性之研磨墊材料> 可使用··熱可塑性樹脂（聚乙缔、聚苯乙烯、氟樹脂、聚 氯乙烯、聚酯、聚丙烯、甲基丙烯樹脂、聚碳酸鹽、聚醯 -19- 84033 200403122 亞胺、聚乙縮酸等）、PTFE (聚四氟乙晞）、PBI (聚苯並咪旬 、PEI (聚·醯亞胺）、pps (聚苯硫醚）、pEEK (聚醚醚酮）、 盖龍、超高分子聚乙烯、酞青、氟化石墨、二硝化鉬、二 硫化鎢、二硫化鉬。又，在金屬係方面，以使用比a離子 化傾向小的材料，譬如，銀、鈀、銥、白金、金等。 <研磨墊及對向電極之結構例> 研磨塾14及對向電極丨5譬如可採取如下例丨至例7之結構。 圖2係顯不各結構例之基本剖面結構之剖面圖；在以下結構 例中，係利用從圖2箭頭Α方向所見之平面圖來作說明。 結構例1 結構例1係如圖3之平面圖所示，在呈略環型之研磨墊l4a 之中，嵌合配置著呈圓盤狀之對向電極15a;而該對向電極 15a之外徑係略等於該研磨墊14a之内徑者。 結構例2 結構例2係如圖4之平面圖所示，在長方體之研磨墊丨讣 之中’嵌合配置著呈板狀之對向電極…；而該長方體係在 其中心部被呈略長方形切開者；而該板狀係略等於前述被 切開之略長方形者。 結構例3 ’在呈略圓盤狀之對向電 狀之研磨墊1 4c ;而該研 1 5 c為小，且配置時係與 結構例3係如圖5之平面圖所示 極15c之外周部，配置著呈略圓盤 磨墊14c之直徑係遠比該對向電極 該對向電極1 5 c之外周呈接觸狀。 結構例4 84033 -20- 200403122 結構例4係如圖6 & + @ @ ^ 一 之中，嵌合配置著呈圓心、不’在長方體之研磨墊14d 在其中心部被、夂。 對向電極15d;而該長方體係 研廇執14d、圓形切開者；而該圓盤狀係略等於前述 研磨墊14d又被切開之形狀。 ^ 結構例5 結構例5係如圖7乏平而 一 口心千面圖所不，在呈略圓盤狀之對向雷 極1 5e之主面上之中邱 ^ #及外周邵，以略均等狀配置著圓般 狀之研磨塾14e ;而兮和：府‘，/ 風 、 而3研磨墊14 e之直徑係遠比該對向電極 1 5 e為小者。 結構例6 、口構例6係如圖8〈平面圖所示，在呈略圓盤狀之對向電 梪^ π α與對向電極15f分離方式ϋ配置著呈略長 方體狀之研磨塾14 f。 結構例7 結構例7係如圖9之平面圖所示，在呈略圓盤狀之對向電 私g之外周近旁，配置著呈圓盤狀之研磨墊14g ;而該研 磨i 14g係以輪替方式在電極範圍内移動者，且該研磨墊 14g之直徑係遠比該對向電極15§為小者。 土 在本毛明中，係使用上述硬質研磨墊作為研磨墊，因此 在Cu CMP上成為問題之侵蝕、淺碟化、凹入及低介電率材 料之損傷都得以防止；以下係本發明可獲得之功效。 首先，與先前之方法相較，本發明可實現更高精度的平 坦性，因此可提升半導體元件之平坦性，在提升微影方面 <加工精度上、及減少因配線層數增加在集成化時所產生 84033 -21 - 200403122 短路等）上，都可獲得良好效果。此外，基於前 、 文在半導體量產加工處理時，可提高良率。 ’纟GUG戰㈣㈣發生之侵触 因此 、"、曰間、纟巴緣腠义破壞等問題都可獲得解決， 4 (〈半導體晶圓可製作出更多良品晶片，提高半 導體晶圓之自盘# ^ ^ 製作出附加严值入…果為，可貫質上提升晶片之單價’ 助於抑制不 。再者’上述良率之提升係有 ，不艮品晶片之廢棄，因此亦具有高環境附加價值。 、又，根據本發明，配線高度可按照原先之設計進行高精 ::工。因此’電流密度並不會超過設計範圍，而流入配 -部’所以不會使電子遷移（EM)耐性劣化，可確保之 可靠度。 π即，在CUCMP之平坦化方面，由於侵蝕等原因，會使 配線形狀與元件設計產生極大差異，故無法確保原先設計 〈兀件特性及可靠度；而如使用本發明，則由於配線形狀 可形成與元件設計值約同等的形狀，故可確保元件 及 可靠度。 此外，本發明可使用用於迴避配線延遲之低介電率材 =，因此使高速元件之開發，量產都變為可能；進而也可 實現賦予高附加價值之製品設計。亦即，在本發明中，可 用伴卩过半導體元件咼速化之低介電率膜的層間絕緣膜， Q此可凸頭與不適用低介電率膜之元件之間的差異性。 此外，在設計法則上，不用設定如先前般之禁止規則， 因而可貝現具有南自由度之設計。亦即，在以Cu CMp進行 84033 -22- 200403122The Cu film 18 is held by a substrate holding member (not shown). In the electrolytic solution tank 16, the polishing pad M is arranged opposite to the fixed plate 13 at a specific interval on the substrate 17, and the fixed plate 13 is formed in a disc shape, and 2 is opposed to the% electrode (cathode). ) 15 retaining members. Here, the polishing pad M is fixed and held on the substrate 7 side on the disk 13. In addition, the fixed plate 13 can be moved in the up and down direction by using a moving means not shown in;, that is, approached or moved away from the substrate while maintaining a parallel state with the substrate 17. In addition, the fixed plate 13 is also rotatable around a central axis of the fixed plate ^ < using a rotating means not shown in the figure. A counter electrode (cathode) 15 is fixedly disposed on the inner diameter side of the fixed plate 13. Furthermore, an electrolytically applied electricity 12 is connected to the substrate 17 and the sub-to-private electrodes 15 for connection therewith. · Hereinafter, the method of polishing the polishing method 84033 15 200403122 by the aforementioned polishing device u will be described; and the Cu film 18 is formed on the substrate 17. : First, an electrolytic cell 16 filled with electrolytic rhenium is set as a substrate, and the substrate 17 is used as an anode, and an electrolytic voltage is applied between the electrolytic solutions E and ^ ， to cause an electrolytic current to flow to c: Two Γτ: electricity. In this way, as the anode undergoes electrolysis, it is subsequently oxidized, and a copper oxide film is formed on the surface layer). The copper complex and the copper complex-forming agent contained in the electrolyte species react to form a copper complex; through the copper complex-forming agent substance, a high electrical resistance layer and an insoluble complex are formed on the surface of c_18. Deterioration layer such as film, film. As described above, by applying a voltage between the electrolytic power supply 12, :: plate 17, and the counter electrode, the copper complexing speed can be achieved in the present invention (grinding method, while performing the above-mentioned electrolytic polishing, using polishing塾 14 smoothes the surface of ⑽18. The aforementioned smoothing operation uses the polishing pad 14 to press the surface of the anodized Cu film 18 'under a specific pressure and slides to remove the coating of the deterioration layer and make the bottom After the material CU is exposed, the exposed portion of Cu is re-electrolyzed; and the modified layer coating film exists on the surface layer of the convex portion of the ⑽18 which is concave and convex. Although "," also depends on the type of copper complex It is different, but the adhesion between the copper complex and the uncomplexed copper (hereinafter referred to as the uncomplexed copper) is very close ^ 'From the convection of the electrolyte E in the pen solution tank 16, the copper complex has never been The complexed copper (that is, the uncomplexed copper on the substrate 17) is detached and enters into the electrolytic solution E. However, the copper complex is not detached from the complexed copper by the convection of the electrolytic solution alone. Slow speed; 4 improved copper complex removal 8 4033 -16- 200403122 Speed 'so press and slide the polishing pad 14 on the substrate 17 to smooth the surface of the cu film 1 § The polishing pad 14 is mounted on the fixed plate 13. Specifically, it is specified The pressure plate 13 presses the surface of the Cu film 18, and rotates in a plane parallel to the substrate 17 with the center axis of the plate 13 as the center. In this way, it is possible to improve the detachment of the copper complex from the substrate 17. The speed makes the copper complex moon beans detach from the substrate 17 with good efficiency, and flattens the surface of the substrate 17. In addition, the smoothing operation in the present invention includes: a rubbing function, a flattening function, and a wiping function. The cycle of the electrolytic polishing and flattening operations described above can be used to polish the Cii film 18 formed on the substrate 17 toward flattening. When the film 18 is polished by the above-mentioned polishing method, stable and uniform electricity can be used. " In the degree distribution, the current is applied, and the polishing rate and polishing conditions are used to improve the planarization ability in the above-mentioned polishing method. As shown in FIG. Electrolyte of 19. The electricity The polishing solution is mixed with the polishing solution to smooth the surface, and the copper complex can be detached from the substrate with good efficiency, and the surface of the substrate 17 can be flattened. The polishing operation is driven by rotating the polishing pad 14 itself, etc. One side of the orderer. When grinding, it also rotates in the same direction. The soil plate 11 is the driving side of the polishing pad. In addition, in the present invention, the electrolytic polishing is performed in the above manner. In the present invention, Based on the low-pressure sweat point, a hard material is used as the grinding pad for precise grinding and flattening. 5 See more π 84033 200403122. In the previous Cu CMP, due to the high pressure applied, and in order to have good In order to improve the uniformity in the surface of the material to be polished, soft grinding mill is used. Because of this, flatness is actually sacrificed to some degree. In contrast, in the case of the so-called low-pressure electrolytic polishing, a copper complex with weak adhesion to uncomplexed copper is formed due to the action of the electrolyte and the power applied to the electrolysis. The low-voltage electrolytic polishing refers to the use of the above-mentioned polishing In principle, while the metal film formed on the substrate is electrolytically polished, it is polished and flattened to flatten it. For this reason, when using low-voltage electrolytic polishing, the polishing can be performed at a lower pressure than the polishing voltage of 4 PM to 7 psi (1 PSI is about 70 g / cm2) applied by Cu CMP. In addition, grinding can be performed at a grinding pressure of 1 · 5 PSI or less, and the grinding speed (> 500 nm / min) can be fully reached for mass production; and the grinding pressure of 15 psi or less is considered to be porous This is the threshold for low dielectric materials. In addition, even if a grinding pressure of 1.0 PSI or less is used, a grinding speed suitable for mass production can be achieved (> 5000 A / min). However, the conventional low-pressure electrolytic polishing system follows the CMP technology. In order to take into account the followability to the material to be polished, it is difficult to achieve flatness with higher accuracy because it uses a softer polishing pad such as polyurethane foam or tanning. Here, the focus is on the polishing pad in low-voltage electrolytic polishing; since low-voltage electrolytic polishing can be polished at extremely low pressure as described above, there is no need to consider the material to be polished in order to ensure the uniformity in the surface of the material to be polished. Follow-up with grinding mill. The aforementioned insuring uniformity in the surface of the material to be polished is a problem in CMP technology. That is, in terms of low-voltage electrolytic grinding -18- 84033 200403122, the uniformity of grinding can be ignored in the design. Therefore, in the present invention, a hard S polishing pad is used as a polishing pad in order to achieve more accurate polishing and planarization. Due to the use of a hard polishing pad, it can effectively suppress the erosion, shallow dishing, concave and low dielectric material damage problems commonly found in Cu CMp, and achieve higher precision flatness. The physical properties and types of the hard abrasives that can be used in the present invention will be described below with specific examples. < Physical properties of the polishing pad > (at normal temperature) Hardness · Shore D hardness is 60 or more full degree: 0_80 g / cm3 or more Compression ratio: 1.0 or less Elastic recovery ratio: 70% or less Compression strength: 7 kPa or less (When the compression ratio is 0.01% per 1 111111 thickness) The soiling rate: 10 kPa or more < Surface state of the polishing pad > Surface roughness: Approximately the same as the size of the abrasive grains, the standard is 0.2 μιη or less Arbitrary trench processing. However, when a trench is formed, the processing of the trench should be maintained below 30% of the wafer size. The groove processing width is preferably 5 nm, and the groove height is preferably 80% or less of the polishing pad height, or 10 nm or less. < Type of polishing pad > Size: 4 times more than wafer area < Typical polishing pad material > Thermoplastic resin (polyethylene, polystyrene, fluororesin, polyvinyl chloride, Polyester, polypropylene, methacrylic resin, polycarbonate, polyfluorene-19-84033 200403122 imine, polyacetic acid, etc.), PTFE (polytetrafluoroacetamidine), PBI (polybenzimid, PEI (Polyimide), pps (Polyphenylene sulfide), pEEK (Polyetheretherketone), Gailong, ultra-high molecular polyethylene, phthalocyanine, fluorinated graphite, molybdenum dinitrate, tungsten disulfide, disulfide Molybdenum. For metals, materials with a lower ionization tendency than a, such as silver, palladium, iridium, platinum, gold, etc. are used. ≪ Examples of the structure of polishing pads and counter electrodes > The counter electrode 5 can adopt the structure of the following examples 丨 7 for example. Fig. 2 is a cross-sectional view showing a basic cross-sectional structure of each structural example; in the following structural examples, a plan view seen from the direction of arrow A in Fig. 2 is used Structure Example 1 Structure Example 1 is shown in the plan view of FIG. Among them, a disc-shaped counter electrode 15a is fitted and arranged, and the outer diameter of the counter electrode 15a is slightly equal to the inner diameter of the polishing pad 14a. Structure Example 2 Structure Example 2 is a plan view as shown in FIG. As shown, in the rectangular parallelepiped polishing pads, a plate-shaped counter electrode is arranged in a fitting manner; and the rectangular system is cut in a rectangular shape at the center of the rectangular system; Cut slightly rectangular. Structure Example 3 'In a slightly disc-shaped opposite electric polishing pad 1 4c; and this research 1 5 c is small, and the layout is as shown in Figure 5 with the structure example 3 The outer periphery of the pole 15c shown is provided with a slightly disc-shaped pad 14c having a diameter much larger than that of the counter electrode and the counter electrode 15c. The outer periphery is in contact with the outer periphery. Structure Example 4 84033 -20- 200403122 Structure Example 4 As shown in Fig. 6 & + @ @ ^ one, the polishing pad 14d fitted with a circle center and not in the rectangular parallelepiped is quilted at its center. The counter electrode 15d; and the rectangular system research and execution 14d And circular incisions; and the disc-like system is slightly equal to the shape in which the aforementioned polishing pad 14d was cut again. ^ Structure Example 5 Structure The 5 series is as shown in Figure 7 without a flat and heart-shaped thousand-face map. On the main surface of the slightly disc-shaped opposite Lei Ji 1 5e, Qiu ^ # and the peripheral Shao are arranged in a circle with a slightly equal shape. The shape of the polishing pad 14e; and Xihe: Fu ', / wind, and the diameter of the 3 polishing pad 14e is much smaller than that of the counter electrode 15e. Structure example 6 and mouth structure example 6 are shown in Figure 8. <As shown in the plan view, in a manner of separating the counter-electrode 略 π α and the counter-electrode 15f in a substantially disc shape, a slightly rectangular-shaped grind 塾 14 f is arranged. Structural example 7 Structural example 7 is shown in the plan view of FIG. 9, and a disc-shaped polishing pad 14g is arranged near the periphery of the opposite disc-shaped counter-electrode g. The grinding i 14g is a wheel Alternatively, the person moving within the electrode range, and the diameter of the polishing pad 14g is much smaller than that of the counter electrode 15§. In Ben Maoming, the above-mentioned hard polishing pad is used as the polishing pad, so the erosion, shallow dishing, recession and damage of low dielectric materials which are problems on Cu CMP can be prevented; the following are obtainable by the present invention efficacy. First, compared with the previous method, the present invention can achieve higher precision flatness, and therefore can improve the flatness of the semiconductor element, improve the lithography < processing accuracy, and reduce integration due to the increase in the number of wiring layers. 84033 -21-200403122 short circuit, etc.), good results can be obtained. In addition, based on the previous and the text, in the semiconductor mass production processing, the yield can be improved. 'The invasion of the GUG trenches can therefore be solved, such as the destruction of the righteousness of the quotient, the time, and the border between the two countries. 4 (<Semiconductor wafers can produce more good-quality wafers, improving the self-discipline of semiconductor wafers. # ^ ^ Created additional stringent value ... As a result, the unit price of wafers can be increased qualitatively 'to help suppress the failure. Furthermore,' the above-mentioned improvement in yield is due to the discarding of unqualified wafers, so it also has a high environment Added value. Also, according to the present invention, the wiring height can be high-precision according to the original design :: work. Therefore, the 'current density does not exceed the design range, but flows into the distribution-portion' so it does not cause electron migration (EM) Deterioration of resistance can ensure reliability. Π That is, in the planarization of CUCMP, due to erosion and other reasons, the wiring shape and component design will be greatly different, so the original design cannot be guaranteed. With the present invention, since the shape of the wiring can be formed to be approximately the same as the design value of the element, the element and reliability can be ensured. In addition, the present invention can use a low dielectric for avoiding wiring delay. Rate material =, so that the development and mass production of high-speed components are possible; furthermore, product designs that give high added value can also be realized. That is, in the present invention, a low-level device that can speed up semiconductor devices can be used. The interlayer insulating film of the permittivity film, this can be a difference between the bump and the component that is not applicable to the low permittivity film. In addition, in the design rule, there is no need to set a prohibition rule as before, so it can have Design of South Degree of Freedom. That is, in Cu CMp 84033 -22- 200403122
Cu平坦化的情形，必須 元件設計。*^、—/叙形狀變化，來進行 ，由於可完全按照元件i=:進行的cu平坦化方面 制之設計。並且在提汽丁、工故可|現無邊際限 的附帶設計。…以自由度的同時，也免除了多餘 向且 :二用硬質研磨塾，因此研磨塾14本身之消耗 又 r來，因延長了消耗品之研磨塾14之妄人 可降低製造成本。 β 土！4炙可〒，故 睡著、^對把上述研磨万法使用^半導體裝置之製造方 厂⑼用在銅配線形成加工處理中的情形為例作說明； 線形成加工處理係採用半導體裝置之金屬㈣法 米貫施者。 首先如圖1 0所不，在晶圓基板1 〇 1上，譬如以CVD (Chemical Vap〇r Deposition，^ ^ ) ^ ^ ^ ^ 緣膜102 ;而在該晶圓基板1〇1上係適當形成有未在圖中顯 ^之雜質擴散區域，且係包含矽等；而該層間絕緣膜1〇2係 譬如由氧化矽所形成者。就層間絕緣膜102而言，除了可使 用以 CVD 法所形成之 TE〇s (tetra ethyi 〇rth〇 silicate，正石圭 酉艾乙酯）膜或矽氮化膜之外，還可使用所謂Low-k (低介電率 膜）材料等。在此，低介電率絕緣膜有：SiF、SiOCH、聚芳 基乙酸、多孔矽化物、聚醯亞胺等。 接著’如圖11所示，使用公知之感光微影技術及蝕刻技 術’來形成接觸孔CH及配線溝Μ ;而該接觸孔CH係通往晶 圓基板101之雜質擴散區域者；而該配線溝Μ係形成有特定 84033 -23 - 200403122 之圖案之配線者；而該特定之圖案之配線係與晶圓基板101 之雜質擴散區域呈電性連接者。 接著，如圖12所示，在層間絕緣膜1〇2之表面、接觸icH 及配線溝Μ内形成阻擋膜103。該阻擋膜1〇3,係譬如用丁a、 Ti、TaN、TiN等材料，以公知之濺鍍法所形成。當構成配 線I材料為銅，且層間絕緣膜1〇2係由氧化矽所構成之情形 寺由表銅對氧化石夕之擴散係數較大，容易氧化，為了阻 止此一現象，因此設置阻擋膜丨〇3。 接著，如圖13所示，在阻擋膜1〇3上，利用公知之濺鍍法， 以特疋之膜厚把銅進行沉積，而形成籽晶膜丨〇4。形成籽晶 膜1 04之目的在於，當把銅埋入配線溝M及接觸孔〔η之際， 其可促進銅粒之成長。 接著如圖14所示，形成Cu膜105，使銅埋入接觸孔cpj =配線溝Μ中。以膜105譬如可用電鍍法、CVD法、濺鍍法 等來形成。又籽晶膜104係與CuM1〇5形成一體。a膜ι〇5 之表面g因夕餘之Cu膜1〇5而形成凹凸，而該多餘之以膜 1 05係因接觸孔ch及配線溝μ之埋入所產生者。 接著，以研磨方式，把層間絕緣膜1〇2表面上之多餘Cu 膜1除去，使之平坦化。亦即，針對形成有上述Cu膜1〇5 <晶圓基板101實施研磨工序；而在該研磨工序中之研磨， 係同時把上述電解研磨及利用研磨墊之磨平作業同時實施。 亦即，如圖15所不，在電解槽£中，使Cl^^1〇5及對象電極 1〇6呈對向配置狀態；接著，如圖16所示，把Cu膜ι〇5作為 陽極進行通電，使電解電流流通，實施電解研磨；如此則 84033 -24- 200403122 可使Cu膜105表面陽極氧化，形成含有銅絡合體1〇7之變質 層。同時，如圖17所示，以特定壓力，具體而言，以2 psi (1 PSI約為70 g/cm2)以下的壓力按壓研磨墊1〇8，且進行滑 動，來貫施磨平作業；除去含有銅絡合體i 〇7之變質層，如 圖18所示，露出。膜1〇5之底層銅1〇化。在此，研磨墊1〇8 係使用如上所述之硬質研磨塾。 在利用該研磨墊108所實施之磨平作業上，僅以膜1〇5之 凸4的’又貝層被除去，而凹邵之變質層則依然以原樣殘 存。接著繼續進行研磨，使底層銅1〇5a更進一步陽極氧化。 此時，如上所述，Cu膜1〇5之凹部由於殘存著含有銅絡合體 107之變質層，故不會被電解研磨，如此則僅使膜丨〇5之 凸部被研磨。如上所述，經由電解研磨而形成變質層，且 經由磨平作業而除去變質層，不斷反覆進行前述動^，則In the case of Cu planarization, element design is required. * ^,-// shape change to carry out, because it can be completely designed according to the cu flattening aspect of the component i = :. And it can be used in lift steam, industrial accidents, and now there is no marginal incidental design. … With the freedom, it also eliminates the need for redundant grinding: the second use of hard grinding 塾, so the consumption of grinding r14 itself again, because prolonged consumption of consumable grinding 妄 14 can reduce manufacturing costs. β soil! 4 can be burned, so fall asleep, ^ the use of the above-mentioned grinding method ^ semiconductor device manufacturing plant ⑼ used in copper wiring forming processing as an example to explain; wire forming processing using semiconductor device metal ㈣Family implementers. First, as shown in FIG. 10, on the wafer substrate 101, for example, a CVD (Chemical Vapor Deposition, ^ ^) ^ ^ ^ ^ edge film 102; and on the wafer substrate 101, it is appropriate Impurity diffusion regions not shown in the figure are formed, and are formed of silicon or the like; and the interlayer insulating film 10 is formed of, for example, silicon oxide. As for the interlayer insulating film 102, a so-called Low-k can be used in addition to a TE0s (tetra ethyi 〇silicate) film or a silicon nitride film formed by a CVD method. (Low dielectric film) materials. Here, the low-dielectric-constant insulating film includes SiF, SiOCH, polyarylacetic acid, porous silicide, polyfluorene, and the like. Next, as shown in FIG. 11, a well-known photolithography technology and etching technology are used to form a contact hole CH and a wiring trench M; and the contact hole CH is one that leads to the impurity diffusion region of the wafer substrate 101; and the wiring The trench M is a wiring formed with a specific pattern of 84033 -23-200403122; and the wiring of the specific pattern is electrically connected to the impurity diffusion region of the wafer substrate 101. Next, as shown in FIG. 12, a barrier film 103 is formed on the surface of the interlayer insulating film 102 and in the contact icH and the wiring trench M. The barrier film 103 is formed by a known sputtering method using materials such as butadiene a, Ti, TaN, and TiN. When the material of the wiring I is copper, and the interlayer insulating film 10 is composed of silicon oxide, the diffusion coefficient of the surface copper to the oxide stone is large, and it is easy to oxidize. In order to prevent this phenomenon, a barrier film is provided.丨 〇3. Next, as shown in FIG. 13, on the barrier film 10, copper is deposited with a special film thickness by a known sputtering method to form a seed film 104. The purpose of forming the seed film 104 is to promote the growth of copper particles when copper is buried in the wiring trench M and the contact hole [η]. Next, as shown in FIG. 14, a Cu film 105 is formed so that copper is buried in the contact hole cpj = wiring trench M. The film 105 can be formed by, for example, a plating method, a CVD method, or a sputtering method. The seed film 104 is integrated with CuM105. The surface g of the a film ι05 is uneven due to the Cu film 105 in the evening, and the excess is caused by the embedding of the contact hole ch and the wiring groove μ. Next, the excess Cu film 1 on the surface of the interlayer insulating film 102 is removed by polishing to flatten it. That is, the polishing process is performed on the Cu substrate 105 < wafer substrate 101 formed; and the polishing in this polishing process is performed simultaneously with the electrolytic polishing and the polishing operation using a polishing pad. That is, as shown in FIG. 15, in the electrolytic cell, Cl ^ 105 and the target electrode 106 are placed in a state of facing each other. Next, as shown in FIG. 16, Cu film 05 is used as the anode. The current is applied to cause electrolytic current to flow and electrolytic polishing is performed. In this case, 84033 -24- 200403122 can anodize the surface of the Cu film 105 to form a modified layer containing copper complex 107. At the same time, as shown in FIG. 17, the polishing pad 108 is pressed with a specific pressure, specifically, a pressure of 2 psi (1 PSI is about 70 g / cm2) or less, and slides to perform the smoothing operation; As shown in FIG. 18, the deteriorated layer containing the copper complex i 〇07 was removed and exposed. The underlying copper of the film 105 is 10%. Here, the polishing pad 108 uses a hard polishing pad as described above. In the flattening operation performed by using the polishing pad 108, only the ′ -shell layer of the convex portion 4 of the film 105 was removed, and the deformed layer of the concave portion was left as it is. Next, grinding is continued to further anodize the underlying copper 105a. At this time, as described above, the concave portion of the Cu film 105 does not undergo electrolytic polishing because the modified layer containing the copper complex 107 remains, so that only the convex portion of the film 105 is polished. As described above, the deteriorated layer is formed by electrolytic polishing, and the deteriorated layer is removed by the smoothing operation, and the aforementioned movement is performed repeatedly.
Cu腠1〇5變為平坦，並在配線溝M及接觸％ch内形成a配 線。 _ 半導體裝置在上述研磨工序之後，進行阻擋膜1〇3之研磨 及洗淨，並在已經形成線之晶圓基板1〇1上形成封蓋 膜。接著，反覆進行從上述層間絕緣膜1Q2的形成（如圖ι〇 所示)到封蓋膜的形成之各工序，如此則可形成多層配線。 如上所述，在半導體裝置之製造工序中，使用包含電解 研磨及磨平作業之研磨方法，因此可以安定、均一之電流 分佈進行通電，且以良好的研磨率、研磨條件，直到研磨 終點為止進行電解研磨；經由此—方式，可達成&膜ι〇5 的平坦化，並可抑制Cu殘留及過度研磨等的產生。因此， 84033 -25- 200403122 =抑制Cu配線之短路及開路等之產生的同時，亦 )月且配線電性阻抗安定的面。 ^成千 又，變質層之研磨作業係以比CMP更低上 力，具體而言，即利用多孔# »夕的按壓 、 矽化物寺低介電率材料所形士 又低強度層間絕緣膜1 〇2之比破垵茂夬 乂成 如，2 PSI以下之壓力)來：;破：厂t力更低的按壓壓力(譬 之剝離、龜裂等破壞。τ 万止層間絕緣膜1〇2 J，在上述半導體裝置之製造方法中，為了提高平坦化 月匕力，在上述研磨工序上，可使用含有研磨粒之電解液。 又，當然並不限於半導體裝置製造中之研磨工序， s金屬胺研磨工序之其他所有製造工序中均可實施。 與本發明有關之研磨方法係在電解液中，使：成有全屬 膜之基板與對向電極呈對向配置，並介以上述電解=2 述金屬膜進行通電，同時以硬質研磨塾研磨 :面，來把上述金屬膜研磨者。 焉胰录 又、，與本發明有關之研磨裝置係在電解液中把形成於基 板上（金屬膜進行研磨的研磨裝置；其係具備：對向電極， ^係與上述基板呈對向配置者；電源，其係以上述基板為 以上述對向電極為陰極，來施加電壓者，·及硬質研 磨土 /、係在上述基板上滑動來研磨上述金屬膜者。 6與本發明有關之半導體裝置之製造方法，其係具有·配 、泉溝Φ成工序’其係用於在絕緣膜上形成金屬配線者，而 該絕緣膜係形成於基板上者；金屬膜形成工序，其係在上 述系巴緣膜上形成金屬膜，來把上述配線溝埋入者；及金屬 84033 -26- 200403122 膜rt序；其係用於把形成於上述絕緣膜上之金屬膜進 订磨，在上述金屬膜研磨工序方面，係在電解液中， 使形成有上述金屬膜之基板與對向電極呈對向配置，並介 以上逑電解液對上述金屬膜進行通電，同時以硬質研磨塾 研磨上述金屬膜表面，來把上逑金屬膜研磨。 在上述與本發明有關之研磨方法及研磨裝置中，係利用 甩角千研磨與磨平作業之複合作用來研磨金屬膜，因此，與 使用先前之CMP進行金屬膜之平坦化的情形相較，可非常 有效地把金屬膜之凸部進行選擇性除去，及實施平坦化。 此外’在上述與本發明有關之研磨裝置及研磨方法中， 由於使用硬質研磨塾’以低研磨壓力進行磨平及研磨，故 可抑制侵姓、淺碟仆、、 、 果C凹入寺的產生，同時可實現更高精 度的研磨。 、又根據本發明，即使以非常低的研磨壓力亦可獲得充 Μ、汗磨率因此，如從半導體裝置之低耗電化及高速化 等々觀玷，為了減低介電率而使用機械性強度較低的低介 兒率膜的情形，本發明亦可適用。 此=，在使用上述研磨方法之與本發明有關之半導體裝 、、方去方面’由於可獲得和上述研磨方法同樣的效 果故可簡便且確貫地形成具有可靠度且形狀良好的金屬 配線。 【圖式簡單說明】 固係與本务明有關之研磨裝置之概略結構圖。 圖2係硬質研磨墊之基本結構例之剖面圖。 84033 -27- 200403122 圖3係與結構例!有關之硬質研磨墊及 平面圖。 t向电極之配置的 圖4係與結構例2有關之硬質研磨塾及 平面圖。 f向电極之配置的 圖5係與結構例3有關之硬質研磨塾及對 平面圖。 电桎之配置的 圖6係與結構例4有關之硬質研磨塾 平面圖。 Π兒極义配置的 平Γ:。與結構例5有關之硬質研磨墊及對向電極之配置的 ^係與結構例6有關之硬質研磨墊及對向電極之配置的 干面圖。 圖9係與結構例7有關之硬質研磨整及姆向電極之配置的 平面圖。 .圖_、與本發明有關之半導體裝置之製造方法的說明圖 ，且係頭π層間絕緣膜形成狀態之要部的剖面圖。 •圖11:與本發明有關之半導體裝置之製造方法的說明圖 ’且係顯#配線溝及接觸孔形成狀態之要部的剖面圖。 圖12係與本發明有關之半導體裝置之製造方法的說明圖 •，且係顯示阻擋膜形成狀態之要部的剖面圖。 圖13係與本發明有關之半導體裝置之製造方法的說明圖 •’且係顯示籽晶膜形成狀態之要部的剖面圖。 圖14係與本發明有關之半導體裝置之製造方法的說明圖 ，且係顯示Cu膜形成狀態之要部的剖面圖。 84033 -28- 200403122 圖15係與本發明有關之半導體 ;且係顯示配線溝及接觸孔形成狀態之要：：法的說明圖 •圖16耐發明有關之半導體震置之製造方明圖 ，且係用於說明研磨工序之圖。 、 β 圖1 7係與本發明有關之半導 ;且係祕說明研磨工序之圖。置<“万法的說明圖 .圖18係與本發明有關之半導體裝置之製造方法的說明圖 ，且係用於說明研磨工序之圖。 圖19係以先則（CMP之配線加工處理所形成之a配線之 一例的要部剖面圖。 圖20係以先前之CMP之配線加工處理所形成之&配線之 其他例的要部剖面圖。 圖21係以先前之CMP之配線加工處理所形成之cu配線之 其他例的要部剖面圖。 圖22係層間絕緣膜之低介電率材料之被破壞狀態之圖。 圖23係以先前之CMP之配線加工處理所形成之Cu配線之 一例的要部剖面圖。 【圖式代表符號說明】 11 研 磨裝置 12 解施加 電源 13 定 盤 14， 14a， 14b ，14c， 14d， 14e， 14f， 14g 研 磨 墊 15， 15a， 15b ，1 5c， 15d， 15f， 15g， 106 對 向 16 電 解液槽 84033 -29- 200403122 17 基板 18 ， 105 Cu膜 101 晶圓基板 102 ， 201 層間絕緣1 103 ， 202 阻檔膜 104 籽晶膜 105a 底層銅 107 銅絡合體 203 Cu E 電解液 CH 接觸孔 M 配線溝 -30 84033Cu 腠 105 is flattened, and a wiring is formed in the wiring trench M and the contact% ch. _ After the semiconductor device has been polished as described above, the barrier film 10 is polished and cleaned, and a capping film is formed on the wafer substrate 101 where the lines have been formed. Next, the steps from the formation of the interlayer insulating film 1Q2 (as shown in FIG. 10) to the formation of the capping film are repeatedly performed, so that a multilayer wiring can be formed. As described above, in the manufacturing process of the semiconductor device, a polishing method including electrolytic polishing and flattening is used. Therefore, the current can be applied with a stable and uniform current distribution, and the polishing can be performed with good polishing rate and polishing conditions until the polishing end point. Electrolytic polishing; Through this method, the & film 〇05 can be flattened, and the occurrence of Cu residue and excessive polishing can be suppressed. Therefore, 84033 -25- 200403122 = the surface where the electrical impedance of the wiring is stable while suppressing the occurrence of short-circuit and open-circuit of the Cu wiring. ^ Thousands of times, the polishing operation of the modified layer is performed at a lower force than CMP, specifically, using a porous # »press, a low-intensity interlayer insulating film formed by a silicide temple low dielectric material 1 The ratio of 〇2 is less than 2 PSI, and the pressure is less than 2 PSI :; Breaking: the pressing force of the factory is lower (for example, peeling, cracking, etc.). Τ 万 止 Interlayer insulation film 10 J. In the method for manufacturing a semiconductor device, in order to increase the flattening force, an electrolytic solution containing abrasive particles may be used in the polishing step. Of course, it is not limited to the polishing step in the manufacturing of a semiconductor device. S metal The amine polishing process can be implemented in all other manufacturing processes. The polishing method related to the present invention is in an electrolytic solution, so that: the substrate with the entire film and the counter electrode are arranged opposite to each other, and the above-mentioned electrolytic = 2 The metal film is energized, and the above-mentioned metal film is polished with a hard polishing surface. At the same time, the polishing device related to the present invention is formed on a substrate (metal film in an electrolytic solution). Grind The device includes: a counter electrode, which is arranged opposite to the substrate; a power source, which applies a voltage to the substrate using the counter electrode as a cathode, and a hard abrasive soil, Those who slide on the substrate to polish the metal film. 6 A method for manufacturing a semiconductor device related to the present invention, which has a process of forming, forming, and forming a metal wiring on an insulating film, and The insulating film is formed on a substrate; the metal film forming step is to form a metal film on the aforementioned edge film to bury the wiring trench; and the metal 84033 -26- 200403122 film rt sequence; its system It is used for ordering and grinding the metal film formed on the insulating film. In the metal film polishing step, the substrate is formed in the electrolyte with the counter electrode disposed opposite to the substrate, and the above is interposed.逑 The electrolyte applies electricity to the metal film, and at the same time, the surface of the metal film is polished with a hard polishing 塾 to grind the upper metal film. In the above-mentioned polishing method and polishing device related to the present invention, it is advantageous The metal film is polished by the combined action of the angle-thousand grinding and flattening operations. Therefore, compared with the case of using the previous CMP to planarize the metal film, the convex portion of the metal film can be selectively removed very effectively. In addition, in the above-mentioned grinding apparatus and grinding method related to the present invention, since a hard grinding mill is used for smoothing and grinding at a low grinding pressure, it is possible to suppress invasion of surnames, shallow dishes, and other fruits. The generation of C recessed temples can achieve more accurate polishing at the same time. According to the present invention, the charge and sweat rate can be obtained even with a very low polishing pressure. Therefore, for example, from the low power consumption of semiconductor devices and The present invention is also applicable to a case where a low-dielectric film having a low mechanical strength is used to reduce the dielectric constant, such as a high-speed semiconductor device. Since the same effect as that of the above-mentioned polishing method can be obtained, it is possible to easily and consistently form a metal wiring having good reliability and good shape. [Brief description of the drawings] This is a schematic structural diagram of a grinding device related to this matter. Fig. 2 is a cross-sectional view of a basic structural example of a hard polishing pad. 84033 -27- 200403122 Figure 3 is a rigid polishing pad and a plan view related to the structural example! Fig. 4 shows the arrangement of the t-direction electrodes and a plan view of the hardened grinding pad and structural example 2. Fig. 5 shows the arrangement of the f-direction electrodes. Fig. 5 is a plan view of the hardened grindstone and the structure of the third example. Fig. 6 is a plan view of a hardened polishing pad related to the structure example 4 of the electric pad. Π Er pole configuration: Γ :. The arrangement of the hard polishing pad and the counter electrode related to the structural example 5 is a dry plan view of the arrangement of the hard polishing pad and the counter electrode related to the structural example 6. Fig. 9 is a plan view showing the arrangement of the hardened polishing and omnidirectional electrodes according to the seventh structural example. Figure _, an explanatory diagram of a method for manufacturing a semiconductor device related to the present invention, and is a cross-sectional view of a main part of a state in which a head π interlayer insulating film is formed. • FIG. 11 is an explanatory diagram of a method of manufacturing a semiconductor device according to the present invention, and is a cross-sectional view of a main part showing a state where a #wiring trench and a contact hole are formed. FIG. 12 is an explanatory diagram of a method for manufacturing a semiconductor device according to the present invention, and is a cross-sectional view of a main part showing a state in which a barrier film is formed. Fig. 13 is an explanatory view of a method of manufacturing a semiconductor device according to the present invention. Fig. 13 is a cross-sectional view of a main part showing a seed film formation state. FIG. 14 is an explanatory diagram of a method for manufacturing a semiconductor device according to the present invention, and is a cross-sectional view of a main part showing a state in which a Cu film is formed. 84033 -28- 200403122 Figure 15 shows the semiconductors related to the present invention; and shows the formation state of wiring trenches and contact holes :: an explanatory diagram of the method; Figure 16 is a clear manufacturing diagram of the semiconductor shock-resistant device related to the invention, and It is a figure for demonstrating a grinding process. , Β Figure 17 is a semiconductor related to the present invention; and it is a diagram illustrating the grinding process. <Explanation diagram of Wanfa. FIG. 18 is an explanatory diagram of a manufacturing method of a semiconductor device related to the present invention, and is a diagram for explaining a polishing process. FIG. 19 is based on a rule (CMP wiring processing station of CMP). A cross-sectional view of a main part of an example of a wiring formed. Fig. 20 is a cross-sectional view of a main part of another example of & wiring formed by a previous CMP wiring process. Fig. 21 is a previous CMP wiring process Sectional view of the main part of other examples of the formed cu wiring. Fig. 22 is a diagram showing the damaged state of the low dielectric material of the interlayer insulating film. Fig. 23 is an example of the Cu wiring formed by the previous CMP wiring processing process The main part of the section. [Illustration of the symbols of the drawings] 11 Grinding device 12 De-energize 13 Fixing plate 14, 14a, 14b, 14c, 14d, 14e, 14f, 14g Polishing pad 15, 15a, 15b, 15c, 15d 15f, 15g, 106 opposite 16 electrolyte bath 84033 -29- 200403122 17 substrate 18, 105 Cu film 101 wafer substrate 102, 201 interlayer insulation 1 103, 202 barrier film 104 seed film 105a Copper electrolyte layer 203 Cu E 107 CH copper complex body contact hole wiring grooves -3084033 M