CN108780763A - 各向异性导电连接构造体 - Google Patents
各向异性导电连接构造体 Download PDFInfo
- Publication number
- CN108780763A CN108780763A CN201780017937.1A CN201780017937A CN108780763A CN 108780763 A CN108780763 A CN 108780763A CN 201780017937 A CN201780017937 A CN 201780017937A CN 108780763 A CN108780763 A CN 108780763A
- Authority
- CN
- China
- Prior art keywords
- electrode terminal
- anisotropic conductive
- protruding portion
- electroconductive particle
- connecting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
- H01B5/16—Non-insulated conductors or conductive bodies characterised by their form comprising conductive material in insulating or poorly conductive material, e.g. conductive rubber
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29399—Coating material
- H01L2224/294—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29438—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29399—Coating material
- H01L2224/294—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29438—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29499—Shape or distribution of the fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
- H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9211—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Combinations Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
提供能够减少电极端子彼此的各向异性导电连接部分的连接电阻并提高可靠性、且能够提高连接强度的、新颖且改良的各向异性导电连接构造体。为了解决上述课题,依据本发明的某一观点,提供各向异性导电连接构造体,具备:在表面形成有突出部的第1电极端子;第2电极端子;以及包含使第1电极端子与第2电极端子导通的导电性粒子的各向异性导电粘接剂层,突出部的高度相对于导电性粒子的压缩前粒径之比小于60%,第1电极端子的开口面积率为55%以上,第2电极端子的高度为6μm以上。
Description
技术领域
本发明涉及各向异性导电连接构造体。
背景技术
作为连接具有电极端子的多个电子部件(例如,IC芯片、硬性(rigid)基板、柔性基板等)彼此的方法,已知倒装接合法。在倒装接合法中,使多个电子部件的电极端子彼此相对的状态下,连接电极端子彼此。
作为这样的倒装接合法的例子,已知超声波连接法。在该方法中,使多个电子部件的电极端子彼此接触。接着,利用超声波来使电极端子的接触部分振动。由此,使电极端子彼此连接。在该方法中,用金构成双方电子部件的电极端子。接着,向连接部分周边的空间填充填充剂(所谓的底部填充剂(underfill)),并加以固化。
另外,作为倒装接合法的其他例子,已知共晶法。在该方法中,使多个电子部件的电极端子彼此接触。接着,加热电极端子的接触部分。由此,电极端子彼此共晶并连接。在该方法中,例如,用金构成一个电子部件的电极端子,而由锡构成另一个电子部件的电极端子。接着,向连接部分周边的空间填充填充剂(所谓的底部填充剂),并加以固化。
然而,在超声波连接法中,因超声波而电极端子大幅度振动,因此有可能会发生连接不良或短路等。另外,能够适用超声波连接法的电极端子,需要用金等的高价材料构成,因此会增大成本。另外,需要填充剂的填充、固化,因此这一点也会增大成本。另外,还增大工时数。
另一方面,共晶法中,加热电极端子的连接部分,但此时的加热温度会非常高。例如,加热温度成为400℃左右。因此,在电子部件为柔性基板的情况下,加热时柔性基板有可能会变形。若柔性基板变形,则存在柔性基板上的电极端子的位置等偏离的情况。因而,有可能发生连接不良、短路等。进而,与超声波连接法同样还存在与填充剂有关的问题。
因此,近年来,例如专利文献1、2中公开的那样,作为倒装接合法,采用各向异性导电膜来各向异性导电连接电极端子彼此的方法倍受瞩目。在该方法中,不需要超声波,因此不会发生与超声波有关的问题。另外,采用各向异性导电膜的连接方法中也需要加热的工艺,但是加热温度比共晶法低。进而,构成各向异性导电膜的固化性树脂作为填充剂发挥功能,因此不需要另行填充并固化填充剂的工艺。
先前技术文献
专利文献
专利文献1:日本特开平11-31698号公报;
专利文献2:日本特开2005-93978号公报。
发明内容
发明要解决的课题
此外,在电子部件为IC芯片的情况下,在IC芯片作为电极端子形成有凸点(bump)。在该凸点的表面(即,与其他电子部件的电极端子对置的面)的周缘部分,大多形成突出部。进而,突出部往往遍及凸点表面的外缘全周而形成。一直以来,认为这样的突出部会成为连接不良的原因,所以认为最好尽量减小。具体而言,在导电性粒子填埋到因突出部而形成的凹部(所谓的凹痕)内的情况下,导电性粒子有可能没有被充分地压缩。因此,有可能会引起连接不良。因此,在专利文献1、2公开的技术中,想要尽量减小突出部。
然而,在专利文献1、2公开的技术中,为了减小突出部而要花费非常大的工夫。具体而言,在专利文献1公开的技术中,为了减小突出部,使形成在绝缘层的开口部分的开口面积非常小。在此,绝缘层为覆盖IC芯片的功能面的层,开口部分形成在IC芯片的电极焊盘上。而且,凸点经由绝缘层的开口部分而与电极焊盘连接。在专利文献1公开的技术中,通过减小这样的开口部分的开口面积,来减小突出部。然而,减小开口面积的工序也非常花费工夫。另一方面,在专利文献2公开的技术中,为了减小突出部,需要另行将超声波照射到突出部的工序。
进而,本发明人对减小突出部的技术进行了研究,知晓了只是单单减小突出部,反而可能引起连接电阻的增大或可靠性的下降。而且,近年来,强烈要求进一步提高各向异性导电连接部分的连接强度。
因此,本发明鉴于上述问题而构思,本发明的目的在于提供能够减少电极端子彼此的各向异性导电连接部分的连接电阻并提高可靠性、且能够提高连接强度的、新颖且改良的各向异性导电连接构造体。
用于解决课题的方案
为了解决上述课题,依据本发明的某一观点,提供各向异性导电连接构造体,具备:在表面形成有突出部的第1电极端子;第2电极端子;以及包含使第1电极端子与第2电极端子导通的导电性粒子的各向异性导电粘接剂层,突出部的高度相对于导电性粒子的压缩前粒径之比小于60%,第1电极端子的开口面积率为55%以上,第2电极端子的高度为6μm以上。
依据本观点,突出部能够将更多的导电性粒子捕获到突出部内的凹部。而且,凹部内的导电性粒子被充分地压缩。因而,连接电阻降低,可靠性提高。进而,由于在第2电极端子之间有充分量的粘接剂流入,因此能使第1电极端子与第2电极端子牢固地粘接。
在此,也可以使第1电极端子的硬度相对于第2电极端子的硬度之比大于10%。
另外,也可以在第1电极端子的表面形成被突出部包围的凹部,导电性粒子的压缩前粒径相对于第1电极端子的凹部的短边长度之比小于10%。
另外,也可以在第1电极端子的表面形成被突出部包围的凹部,存在于第1电极端子的凹部的导电性粒子的平均占用面积率小于20%。
另外,突出部也可以遍及第1电极端子的表面的外缘全周而形成。
另外,第1电极端子也可为形成在第1电子部件的凸点。
发明效果
如以上说明的那样,依据本发明,能够减少电极端子彼此的各向异性导电连接部分的连接电阻,提高可靠性,且,能够提高连接强度。
附图说明
[图1]是示出本实施方式所涉及的各向异性导电连接构造体10的概略结构的侧截面图。
[图2]是示出同实施方式所涉及的第1电极端子的表面构造的俯视图。
具体实施方式
以下,一边参照附图,一边对本发明的优选的实施方式详细地进行说明。此外,在本说明书及附图中,对于具有实质上相同的功能结构的结构要素,标注相同标号而省略重复说明。
<1.各向异性导电连接构造体的结构>
首先,基于图1及图2,对本实施方式所涉及的各向异性导电连接构造体10的结构进行说明。
各向异性导电连接构造体10具备:第1电子部件20;形成在第1电子部件20上的第1电极端子21;第2电子部件30;形成在第2电子部件30上的第2电极端子32;以及粘接剂层40。
第1电子部件20例如为电子电路基板。不用特别管电子电路基板的种类,可为IC芯片、各种硬性基板(例如,环氧玻璃基板等)、柔性基板等。第1电子部件20例如为IC芯片。在第1电子部件20为IC芯片的情况下,第1电极端子21为凸点。在凸点容易形成突出部22。
第1电极端子21形成在第1电子部件20上。另外,第1电极端子21与构成第1电子部件20的电子电路导通。在第1电极端子21的表面(即,与第2电子部件30对置的面)形成有突出部22。在第1电子部件20为IC芯片的情况下,第1电极端子21为凸点。但是,第1电极端子21只要形成有突出部22即可。因而,第1电极端子21并不限定于凸点。
构成第1电极端子21的材料,只要具有导电性就无特别限制。作为构成第1电极端子21的材料,优选例如由铝、银、镍、铜、及金等的金属构成。
突出部22形成在第1电极端子21的表面。如图2所示,突出部22遍及第1电极端子21的表面的外缘全周而形成。此外,在第1电极端子21为凸点的情况下,突出部22往往遍及第1电极端子21的表面的外缘全周而形成。当然,突出部22的形状并不限于图1所示的形状,优选为图2的形状。在该情况下,突出部22能够更加可靠地捕获导电性粒子42。
另外,在第1电极端子21的表面,形成有被突出部22包围的凹部23(所谓的凹痕)。一直以来,认为这样的突出部22及凹部23成为连接不良的原因,因此认为最好尽量减小。然而,在本实施方式中,积极地活用突出部22。具体而言,通过利用突出部22捕获导电性粒子42,能够将导电性粒子42保持在第1电极端子21及第2电极端子32之间。在此,导电性粒子42被粘接剂层40所包含。由此,在本实施方式中,能够减少连接电阻,且提高可靠性。具体而言,能够降低初始电阻,且能够降低冷热循环实验后的不良率。
第2电子部件30例如为电子电路基板。不用特别管电子电路基板的种类,可为IC芯片、各种硬性基板(例如,环氧玻璃基板等)、柔性基板等。第2电子部件30例如为柔性基板。在第2电子部件30为柔性基板的情况下,第2电极端子32的高度H2容易满足后述的要件。柔性基板的种类也没有特别限制,可为例如聚酰亚胺基板。
第2电极端子31形成在第2电子部件30上。另外,第2电极端子31与构成第2电子部件30的电子电路导通。构成第2电极端子31的材料,只要具有导电性就无特别限制。作为构成第2电极端子31的材料,可举出例如铝、银、镍、铜、及金等的金属。构成第2电极端子31的金属也可以被各种金属镀敷。
粘接剂层40是固化的各向异性导电粘接剂,具备固化树脂层41和导电性粒子42。即,粘接剂层40将第1电极端子21和第2电极端子31进行各向异性导电连接。
各向异性导电粘接剂具备固化性树脂和导电性粒子42。固化性树脂包含聚合性化合物及固化引发剂。聚合性化合物是通过固化引发剂来固化的树脂。固化后的聚合性化合物即固化树脂层41,在粘接剂层40内粘接第1电极端子21和第2电极端子31,并且将导电性粒子42保持在粘接剂层40内。作为聚合性化合物,可举出例如环氧聚合性化合物及丙烯聚合性化合物等。环氧聚合性化合物是分子内具有一个或两个以上的环氧基的单体、低聚物、或预聚物。作为环氧聚合性化合物,可举出:各种双酚型环氧树脂(双酚A型、F型等);酚醛清漆型环氧树脂;橡胶及尿烷等的各种改性环氧树脂;萘型环氧树脂;联苯型环氧树脂;苯酚酚醛清漆型环氧树脂;芪型环氧树脂;三酚甲烷型环氧树脂;二聚环戊二烯型环氧树脂;三苯基甲烷型环氧树脂;以及这些的预聚物等。
丙烯聚合性化合物是在分子内具有一个或两个以上的丙烯基的单体、低聚物、或预聚物。作为丙烯聚合性化合物,能举出例如丙烯酸甲酯、丙烯酸乙酯、丙烯酸异丙酯、丙烯酸异丁酯、环氧丙烯酸酯、乙二醇二丙烯酸酯、二甘醇丙烯酸酯、三羟甲基丙烷三丙烯酸酯、二羟甲基三环葵烷二丙烯酸酯、1,4-丁二醇四丙烯酸酯、2-羟基-1,3-二丙烯酰氧基丙烷、2,2-双[4-(丙烯酰氧基甲氧基)苯基]丙烷、2,2-双[4-(丙烯酰氧基乙氧基)苯基]丙烷、二环戊烯基丙烯酸酯、三环葵基丙烯酸酯、树状(丙烯酰氧基乙基)异氰脲酸酯、尿烷丙烯酸酯等。在本实施方式中,既可以采用上述列举的聚合性化合物之中任意一种,也可以任意组合2种以上而采用。
固化引发剂例如为热固化引发剂。热固化引发剂是利用热来与上述聚合性化合物一起固化的材料。热固化引发剂的种类也无特别限制。作为热固化引发剂,可举出例如使环氧聚合性化合物固化的热固化阴离子固化引发剂或热固化阳离子固化引发剂、使丙烯聚合性化合物固化的热自由基聚合型固化剂等。在本实施方式中,根据聚合性化合物选择适当的热固化引发剂即可。此外,作为固化引发剂的其他例子,可举出光固化引发剂。作为光固化引发剂,可举出例如使环氧聚合性化合物固化的光固化阴离子固化引发剂或光固化阳离子固化引发剂、使丙烯聚合性化合物固化的光自由基聚合型固化剂等。在本实施方式中,根据聚合性化合物选择适当的光固化引发剂即可。
另外,各向异性导电粘接剂中,除了上述成分之外,也可以包含膜形成树脂、各种添加剂等。在为了使各向异性导电粘接剂容易处理而想要做成膜形状时向各向异性导电粘接剂添加膜形成树脂。作为膜形成树脂,能够采用例如环氧树脂、苯氧基树脂、聚酯尿烷树脂、聚酯树脂、聚氨酯树脂、丙烯树脂、聚酰亚胺树脂、丁缩醛树脂等的各种树脂。另外,在本实施方式中,可以只使用这些膜形成树脂之中任意一种,也可以任意组合2种以上而使用。此外,从要使膜形成性及粘接可靠性良好的观点来看,膜形成树脂优选为苯氧基树脂。此外,将各向异性导电粘接剂做成膜形状的情况下,膜(即,各向异性导电膜)的厚度无特别限制。但是,若膜过厚则不要的树脂量过多而在流动性等方面出现问题。因此优选100μm以下,更优选40μm以下。若过薄则难以处理,因此优选5μm以上,更优选12μm以上。
作为能够向各向异性导电粘接剂添加的添加剂,可举出硅烷偶联剂、无机填充剂、着色剂、防氧化剂、及防锈剂等。硅烷偶联剂的种类无特别限制。作为硅烷偶联剂,可举出例如环氧类、氨类、巯基/硫化物类、酰脲类的硅烷偶联剂等。在向各向异性导电粘接剂添加这些硅烷偶联剂的情况下,能够根据基体材料的材质提高粘接性。
另外,无机填充剂是用于调整各向异性导电粘接剂的流动性及膜强度、特别是后述的最低熔化粘度的添加剂。无机填充剂的种类也无特别限制。作为无机填充剂,可举出例如硅石、滑石、氧化钛、碳酸钙、氧化镁等。
导电性粒子42是在粘接剂层40内将第1电极端子21和第2电极端子31各向异性导电连接的材料。具体而言,在粘接剂层40内被第1电极端子21和第2电极端子31挟持的导电性粒子42,使第1电极端子21和第2电极端子31导通。另一方面,其他导电性粒子42(例如,进入到第1电极端子21彼此的间隙的导电性粒子42、进入到第2电极端子31彼此的间隙的导电性粒子42等)都不使任何端子间导通(即,在第1电极端子21间不会出现因导电性粒子42连续的形态导致的短路、在第2电极端子31间不会出现因导电性粒子42连续的形态造成的短路等)。
因而,导电性粒子42一边在粘接剂层40内维持第1电极端子21彼此及第2电极端子31彼此的绝缘性,一边能够使第1电极端子21和第2电极端子31导通。即,导电性粒子42在粘接剂层40内被第1电极端子21和第2电极端子31挟持而使它们导通,并各向异性导电连接。导电性粒子42既可以不造成短路的程度分散在各向异性导电剂,也可以以各自独立的方式配置。该配置可根据各电极端子的尺寸或电极端子的排列方向上的距离等而适当设定,但该配置也可以是规则的。另外,导电性粒子42满足后述的要件。此外,导电性粒子42的压缩前粒径只要满足后述的要件就无特别限制,作为一个例子为1~10μm。在此,如上述,各向异性导电连接前的各向异性导电粘接剂,也可以预先作为膜体而形成。
<2.各向异性导电连接构造体应当满足的要件>
接着,对各向异性导电连接构造体10应当满足的要件进行说明。在各向异性导电连接构造体10满足以下要件的情况下,突出部22能够捕获导电性粒子42。其结果,能够降低连接电阻,并提高可靠性。进而,粘接剂层40能够将第1电极端子21和第2电极端子31牢固地粘接。此外,各向异性导电连接构造体10需要至少满足要件1~3。各向异性导电连接构造体10进一步优选满足要件4以后的要件。此外,在评价是否满足以下要件时,各电极的构造等可以通过SEM(扫描型电子显微镜)等进行观察。例如,突出部22的高度H1能够通过用SEM观察第1电极端子21来测定。另外,以下的参数,既可为对多个各向异性导电连接构造体10测定的测定值的算术平均值,也可以将任一作为代表值而使用。
(2-1.要件1)
突出部22的高度H1相对于导电性粒子42的压缩前粒径之比(以下,还称为“突出部高度/粒径比”)小于60%。在此,压缩前粒径为压缩导电性粒子42之前的粒径。在突出部高度/粒径比成为60%以上的情况下,突出部22会阻碍导电性粒子42的压缩。即,被捕获到凹部23内的导电性粒子42不会被充分地压缩。其结果,增大连接电阻,使可靠性变差。在突出部高度/粒径比小于60%的情况下,突出部22能够将导电性粒子42捕获到凹部23内。进而,导电性粒子42不会被充分地压缩。突出部高度/粒径比优选小于50%。
此外,突出部高度/粒径比的下限值无特别限制,若太过于小则有可能突出部22不能充分地捕获导电性粒子42。因此,突出部高度/粒径比优选为30%以上,更优选为40%以上,进一步优选为42%以上。
(2-2.要件2)
第1电极端子21的开口面积率为55%以上。在此,开口面积率是凹部23的开口面的面积相对于第1电极端子21的表面的整个面积之比。在开口面积率小于55%的情况下,在凹部23内不能捕获充分数量的导电性粒子42。开口面积率优选为70%以上。开口面积率的上限值没有特别限制,若开口面积率过大则有可能降低突出部22的刚性。因此,开口面积率优选为90%以下。
(2-3.要件3)
第2电极端子31的高度H2为6μm以上。由此,在第2电极端子31间也流入充分量的粘接剂,因此第1电极端子21和第2电极端子31能牢固地粘接。进而,第1电极端子21的突出部22即便与第2电极端子31接触,在第1电极端子21的下方也存在充分量的固化树脂层41。因而,突出部22、甚至第1电极端子21被固化树脂层41充分地保护。其结果,连接电阻降低,且可靠性提高。高度H2的上限值没有特别限制,但优选为35μm以下。
(2-5.要件4)
第1电极端子21的硬度相对于第2电极端子31的硬度之比(以下,还称为“电极端子的硬度比”)优选大于10%。这是因为在第1电极端子21与第2电极端子31相比过软的情况下,压缩时(即,各向异性导电连接时)第1电极端子21变形较大。在变形量大的情况下,第1电极端子21彼此接触,有可能短路。此外,各电极端子的硬度为例如维氏硬度。电极端子的硬度比更优选为大于15%,进一步优选为大于30%。电极端子的硬度比的上限值没有特别限制,但是也可为1左右(即,两者的硬度大致一致)。
(2-6.要件5)
导电性粒子42的压缩前粒径相对于凹部23的短边长度之比(以下,还称为“粒径/开口短边长度比”)优选小于10%。在此,凹部23的短边长度为凹部23的俯视形状(例如图2所示的形状)的短边长度。在粒径/开口短边长度比小于10%的情况下,能够将更多的导电性粒子42捕获到凹部23内。粒径/开口短边长度比更优选小于9%,而进一步优选小于8.5%。此外,粒径/开口短边长度比的下限值根据要件1进行确定。即,若粒径/开口短边长度比过小,则导电性粒子42的粒径会过小,不能满足要件1。
(2-7. 要件6)
另外,优选存在于凹部23内的导电性粒子42的平均占用面积率小于20%。平均占用面积率的下限优选为1个以上压缩的导电性粒子的占用面积率,更优选为2个以上压缩的导电性粒子的占用面积率,进一步更优选为3个以上压缩的导电性粒子的占用面积率。在此,各导电性粒子42的占用面积是在水平面投影压缩的导电性粒子42时所得到的面积。另外,平均占用面积率能够用以下的工序进行测定。即,从各向异性导电连接构造体10剥下第1电极端子21,或者,将各向异性导电连接构造体10研磨至连接部分,从而露出第1电极端子21和第2电极端子31的连接部分。接着,选择50个露出的连接部分。接着,以面视角观察各连接部分,测定各连接部分中的导电性粒子42的占用面积。此外,以SEM(扫描型电子显微镜)等进行观察即可。而且,测定存在于各连接部分的凹部23内的全部导电性粒子42的占用面积,它们的总面积除以凹部23的开口面的面积。由此,测定各连接部分中的占用面积率。再者,通过对这些占用面积率取算术平均,测定平均占用面积率。在平均占用面积率处于上述范围内的情况下,在凹部23内会捕获到充分量的导电性粒子42。
导电性粒子42在回弹力过大的情况下,有可能对可靠性等产生影响。因此,各向异性导电连接构造体优选满足上述要件之外,还满足以下的要件。即,导电性粒子42变形30%时的压缩硬度(K值)优选小于6000N/mm2,更优选为5500N/mm2以下。在此,变形30%时的压缩硬度(K值)是一种成为导电性粒子42的压缩强度的指标的参数。变形30%时的压缩硬度(K值)可由以下的工序算出。即,将导电性粒子42沿一个方向压缩,直至导电性粒子42的粒径(直径)比原来的粒径短30%。然后,基于此时的负荷、位移量、及压缩前的导电性粒子42的半径和以下的数学式(1),算出变形30%时的压缩硬度(K值)。根据数学式(1),K值越小则导电性粒子42成为越软的粒子。
数学式(1)中,F为导电性粒子42压缩变形30%时的负荷,S为压缩造成的导电性粒子42的位移量(mm),R为导电性粒子42的压缩前的半径(mm)。
通过以上方式,并依据本实施方式,突出部22的高度H1等满足既定要件,因此运用突出部22能够提高各向异性导电连接构造体10的质量。具体而言,突出部22能够使更多的导电性粒子42捕获到突出部22内的凹部23。进而,凹部23内的导电性粒子被充分地压缩。因而,连接电阻降低,且提高可靠性。进而,第2电极端子31的高度H2成为既定范围内的值,因此有充分量的粘接剂流入第2电极端子31之间。因而,第1电极端子和第2电极端子会牢固地粘接。进而,本实施方式只要有ACF的压接线就能适用。因而,能够容易引入本实施方式。
实施例
<1.实施例1>
(1-1.第1电子部件的准备)
作为第1电子部件20,准备IC芯片。在该IC芯片中,作为第1电极端子21形成有多个凸点。在第1电极端子21形成有高度H1=1.5μm的突出部22。另外,凸点尺寸(即,第1电极端子21的平面形状)为50μm×50μm的正方形状。另外,开口面积率为73.96%。因而,满足了要件2。另外,第1电极端子21的维氏硬度为50Hv。
(1-2.第2电子部件的准备)
作为第2电子部件30,准备柔性基板。具体而言,对厚度25μm的聚酰亚胺基板(新日铁(鐵)化学社制CS12-25-00CE)进行Cu蚀刻后,实施Ni/Au镀敷,从而形成了第2电极端子31。通过以上的工序,制作了柔性基板。Ni/Au镀敷是通过电解镀敷法来进行。第2电极端子31的高度H1为12μm。因而,满足了要件3。另外,第2电极端子31的宽度为50μm。因而,第1电极端子21和第2电极端子31的有效连接面积为1849μm2。在此,有效连接面积意味着相对于第1电极端子21的开口面积而言第2电极端子31所占的面积。
另外,第2电极端子31的维氏硬度为150Hv。因而,电极端子的硬度比为33.3%。因而,满足了要件4。
(1-3.各向异性导电膜(ACF)的准备)
通过混合苯氧基树脂(品名:YP50,新日铁化学社制)36质量份、环氧固化剂(品名:HP3941HP,Asahi-KASEI(旭化成ケミカルズ)公司制)36质量份、环氧单体(品名:HP4032D,DIC公司制)5质量份、橡胶改性环氧树脂(品名:XER-91,JSR公司制)15质量份、橡胶成分(品名:SG80H,Nagase ChemteX(长瀬ケムテックス)公司制)7质量份、偶联剂(品名:A-187,Momentive Performance Materials Inc(モメンティブ・パフォ一マンス・マテリアルズ・ジヤパン合同会社))、导电性粒子42(日本化学株式会社制),制作了粘接剂组合物。在此,导电性粒子42是以个数密度成为3,500,000个/mm3的方式混合到粘接剂组合物中。而且,利用棒涂机来向另行准备的厚度38μm的剥离处理PET膜涂敷粘接剂组合物,并进行干燥,从而得到了厚度40μm的各向异性导电膜。
导电性粒子42的压缩前粒径为3.5μm,实施了Ni/Au镀敷。因而,突出部高度/粒径比为42.85%。因而,满足了要件1。另外,粒径/开口短边长度比为8.14%。因而,满足了要件5。通过以上方式,实施例1能够确认满足要件1~5。另外,导电性粒子42变形30%时的压缩硬度为5500N/mm2。变形30%时的压缩硬度利用岛津制作所制微小压缩试验机来测定。此外,在以下的各实施例、比较例中使用的导电性粒子42,变形30%时的压缩硬度均为5500N/mm2。
(1-4.各向异性导电连接构造体的制作)
依次层叠第1电子部件20、各向异性导电膜、及第2电子部件30。在此,以使第1电极端子21和第2电极端子31的位置对齐的方式进行了第1电子部件20及第2电子部件30的对位。接着,隔着缓冲材料将加热工具顶到第2电子部件30上。接着,采用加热工具将第1电极端子21和第2电极端子31热压接。通过以上工序,制作了各向异性导电连接构造体10。在此,热压接的条件设为200℃-10sec-100MPa。即,一边以使加热工具的温度从开始压接起10秒钟内成为200℃的方式使加热工具升温,一边在100MPa的压力下将第1电极端子21和第2电极端子31热压接10秒钟。各向异性导电连接构造体10为了进行后述的评价而制作多个。将各向异性导电连接构造体10的结构汇总示于表1中。
(1-5.初始电阻)
采用数字万用表(商品名:数字万用表7561,横河电机社制)测定了按照1-4.制作的各向异性导电连接构造体10的连接电阻。将结果汇总示于表1中。此外,测定了多个连接部分上的初始电阻。在表1示出测定值的范围。
(1-6.可靠性评价)
通过进行按照1-4.制作的各向异性导电连接构造体10的冷热循环实验,评价了可靠性。在冷热循环实验中,使各向异性导电连接构造体10在-40℃及100℃的气氛中各自曝露30分钟,将以此作为1个循环的冷热循环循环500次。接着,提取400个部位的各向异性导电连接构造体10的连接部分,并计数这些中出现不良(显示100mΩ以上的电阻的线路(channel))的部位的数量。将结果汇总示于表1中。
(1-7.占用面积率等的测定)
从各向异性导电连接构造体10剥下第1电极端子21,从而使连接部分露出。接着,以SEM观察连接部分,测定了凹部23内存在的导电性粒子42的数量(即,捕获粒子数)、及导电性粒子42的平均占用面积率。平均占用面积率的测定是通过上述的方法进行的。即,以面视角观察成为测定对象的50个连接部分,并测定了粒子占用的面积、即占用面积。然后,基于该占用面积,算出占用面积率。另外,导电性粒子42的捕获粒子数,设为对于50个连接部分进行测定的粒子数的算术平均值。将结果汇总示于表1中。
<2.实施例2>
实施例2中,除了使第1电极端子21的维氏硬度为90Hv以外,进行了与实施例1同样的处理。实施例2中,电极端子的硬度比成为60%。因而,在实施例2也满足要件4。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<3.实施例3>
实施例3中,除了使第1电极端子21的维氏硬度为20Hv以外,进行了与实施例1同样的处理。实施例3中,电极端子的硬度比成为13.3%。因而,实施例3中也满足要件4。但是,硬度比成为30%以下,因此确认到第1电极端子21有若干变形。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<4.实施例4>
在实施例4中,除了使第2电极端子31的维氏硬度为500Hv以外,进行了与实施例1同样的处理。具体而言,以非电解镀进行第2电极端子31的镀敷,从而得到了上述维氏硬度。在实施例4中,电极端子的硬度比成为10%。因而,在实施例4未满足要件4。因此,压接后第1电极端子21变形较大。然而,由于第1电极端子21的间距较宽,所以未发生短路。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<5.实施例5>
在实施例5中,除了使第2电极端子31的宽度为40μm以外,进行了与实施例1同样的处理。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<6.实施例6>
在实施例6中,除了使导电性粒子42的粒径为3.0μm以外,进行了与实施例1同样的处理。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<7.实施例7>
除了使第2电极端子31的宽度为30μm以外,进行了与实施例1同样的处理。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<8.实施例8>
除了使第2电极端子31的宽度为20μm以外,进行了与实施例1同样的处理。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<9.实施例9>
除了使第2电极端子31的高度H2为6μm以外,进行了与实施例1同样的处理。将各向异性导电连接构造体10的结构及评价结果汇总示于表1中。
<10.比较例1>
除了使导电性粒子42的压缩前粒径为2.5μm以外,进行了与实施例1同样的处理。因而,突出部高度/粒径比成为60%,因此未能满足要件1。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
<11.比较例2>
除了使第1电极端子21的开口面积率为51.84%以外,进行了与实施例1同样的处理。因而,在比较例2中未能满足要件2。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
<12.比较例3>
除了使突出部22的高度H1为3.0μm以外,进行了与实施例1同样的处理。因而,在比较例3中,突出部高度/粒径比成为85.71%,因此未能满足要件1。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
<13.比较例4>
除了利用研磨从第1电极端子21除去突出部22,并使第2电极端子31的宽度为20μm以外,进行了与实施例1同样的处理。因而,在比较例4中,至少未能满足要件1。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
<14.比较例5>
除了使第2电子部件30为玻璃基板以外,进行了与实施例1同样的处理。在该玻璃基板上,形成有由ITO构成的第2电极端子31,第2电极端子31的高度H2为1μm以下。因而,在比较例5中,未能满足要件3。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
<15. 参考例1>
除了利用研磨从第1电极端子21除去突出部22,并使第2电极端子31的宽度为40μm以外,进行了与实施例1同样的处理。因而,在参考例1中,至少未能满足要件1。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
<16. 参考例2>
除了利用研磨从第1电极端子21除去突出部22,并使第2电极端子31的宽度为30μm以外,进行了与实施例1同样的处理。因而,在参考例1中,至少未能满足要件1。将各向异性导电连接构造体10的结构及评价结果汇总示于表2中。
[表1]
[表2]
实施例1~3、5~9全部满足要件1~6,因此关于初始电阻、不良率、及剥离强度均得到良好的结果。在这些实施例中,通过突出部22能够在凹部23内捕获充分数量的导电性粒子42。进而,能够充分地压缩这些导电性粒子42。因此,推测为能得到良好的结果。
但是,在实施例3中,在第1电极端子21观察到若干变形。实施例3中,电极端子的硬度比成为30%以下。即,实施例3中,虽然满足要件4,但成为30%以下的值。另外,在实施例4也得到良好的结果,但是第1电极端子21的变形进一步变大。实施例4中,电极端子的硬度比成为10%以下。因而,不满足要件4。因而,从抑制电极端子的变形的观点来看,可知优选满足要件4。
另一方面,比较例1~5中,可靠性的评价特别差。推测为由于在比较例1~5中不满足要件1~3的哪一个,所以得到这样的结果。在参考例1、2中没有形成突出部22。因此,捕获粒子数相对于实施例变少。然而,得到了大体上不逊于实施例的评价结果。一方面,同样没有形成突出部22的比较例4中,评价结果差。作为该理由,可举出参考例1、2中有效连接面积较大一项。然而,在参考例1、2中另行需要除去突出部22的作业,因此在各向异性导电连接上会花费工夫。因而,可以说实施例1~9更优选。
以上,一边参照附图一边对本发明的优选实施方式详细地进行了说明,但是本发明并不局限于这些例子。如果是本发明所属的技术领域内具有普通知识的人员,在权利要求书记载的技术思想的范畴内,能够想到各种变更例或修正例是显而易见的,关于这些,也应当理解为属于本发明的技术范围。
标号说明
10 各向异性导电连接构造体;20 第1电子部件;21 第1电极端子;22 突出部;23 凹部;30 第2电子部件;31 第2电极端子;40 粘接剂层;41 固化树脂层;42 导电性粒子。
Claims (6)
1.一种各向异性导电连接构造体,具备:
在表面形成有突出部的第1电极端子;
第2电极端子;以及
包含使所述第1电极端子和所述第2电极端子导通的导电性粒子的各向异性导电粘接剂层,
所述突出部的高度相对于所述导电性粒子的压缩前粒径之比小于60%,
所述第1电极端子的开口面积率为55%以上,
所述第2电极端子的高度为6μm以上。
2.如权利要求1所述的各向异性导电连接构造体,其中,
所述第1电极端子的硬度相对于所述第2电极端子的硬度之比大于10%。
3.如权利要求1或2所述的各向异性导电连接构造体,其中,
在所述第1电极端子的表面,形成有被所述突出部包围的凹部,
所述导电性粒子的压缩前粒径相对于所述第1电极端子的凹部的短边长度之比小于10%。
4.如权利要求1~3的任一项所述的各向异性导电连接构造体,其中,
在所述第1电极端子的表面,形成有被所述突出部包围的凹部,
存在于所述第1电极端子的凹部的所述导电性粒子的平均占用面积率小于20%。
5.如权利要求1~4的任一项所述的各向异性导电连接构造体,其中,
所述突出部遍及所述第1电极端子的表面的外缘全周而形成。
6.如权利要求1~5的任一项所述的各向异性导电连接构造体,其中,
所述第1电极端子是形成在第1电子部件的凸点。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-073087 | 2016-03-31 | ||
JP2016073087A JP6945276B2 (ja) | 2016-03-31 | 2016-03-31 | 異方性導電接続構造体 |
PCT/JP2017/012408 WO2017170412A1 (ja) | 2016-03-31 | 2017-03-27 | 異方性導電接続構造体 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108780763A true CN108780763A (zh) | 2018-11-09 |
CN108780763B CN108780763B (zh) | 2022-12-06 |
Family
ID=59964518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780017937.1A Active CN108780763B (zh) | 2016-03-31 | 2017-03-27 | 各向异性导电连接构造体 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10602619B2 (zh) |
JP (1) | JP6945276B2 (zh) |
KR (1) | KR102081570B1 (zh) |
CN (1) | CN108780763B (zh) |
TW (1) | TWI759290B (zh) |
WO (1) | WO2017170412A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111179750A (zh) * | 2019-12-12 | 2020-05-19 | 武汉华星光电技术有限公司 | 显示面板的结构和其制作方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6945276B2 (ja) * | 2016-03-31 | 2021-10-06 | デクセリアルズ株式会社 | 異方性導電接続構造体 |
CN108987439A (zh) * | 2018-06-21 | 2018-12-11 | 武汉华星光电半导体显示技术有限公司 | 显示面板和显示装置 |
TWI671921B (zh) * | 2018-09-14 | 2019-09-11 | 頎邦科技股份有限公司 | 晶片封裝構造及其晶片 |
JP7334198B2 (ja) | 2021-02-01 | 2023-08-28 | プライムプラネットエナジー&ソリューションズ株式会社 | 電極端子および該電極端子を備えた二次電池 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0997814A (ja) * | 1995-09-28 | 1997-04-08 | Nec Corp | 電子部品の接続構造及び製造方法 |
US6222281B1 (en) * | 1998-04-06 | 2001-04-24 | Seiko Epson Corporation | IC chip, IC assembly, liquid crystal device, and electric apparatus |
JP2004186411A (ja) * | 2002-12-03 | 2004-07-02 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2004214374A (ja) * | 2002-12-27 | 2004-07-29 | Toshiba Matsushita Display Technology Co Ltd | 半導体素子及び液晶表示パネル |
JP2008047943A (ja) * | 2007-11-01 | 2008-02-28 | Renesas Technology Corp | 半導体装置 |
JP2012049398A (ja) * | 2010-08-27 | 2012-03-08 | Fujifilm Corp | 導電接合構造、実装構造体及び導電接合方法 |
CN104145329A (zh) * | 2012-03-05 | 2014-11-12 | 迪睿合电子材料有限公司 | 使用各向异性导电材料的连接方法及各向异性导电接合体 |
JP2015028920A (ja) * | 2013-06-26 | 2015-02-12 | 積水化学工業株式会社 | 接続構造体 |
WO2015115657A1 (ja) * | 2014-02-03 | 2015-08-06 | デクセリアルズ株式会社 | 接続体 |
JP2016029698A (ja) * | 2014-07-22 | 2016-03-03 | デクセリアルズ株式会社 | 接続体、及び接続体の製造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1131698A (ja) | 1997-07-14 | 1999-02-02 | Texas Instr Japan Ltd | 半導体装置、その製造方法及び実装構造 |
KR100539060B1 (ko) * | 1997-10-28 | 2007-04-25 | 소니 케미카루 가부시키가이샤 | 이방도전성접착제및접착용막 |
KR20000057810A (ko) * | 1999-01-28 | 2000-09-25 | 가나이 쓰토무 | 반도체 장치 |
JP2001028280A (ja) * | 1999-07-13 | 2001-01-30 | Three Bond Co Ltd | 回路接続部材 |
US6451875B1 (en) * | 1999-10-12 | 2002-09-17 | Sony Chemicals Corporation | Connecting material for anisotropically electroconductive connection |
JP2002151551A (ja) * | 2000-11-10 | 2002-05-24 | Hitachi Ltd | フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法 |
US7154206B2 (en) * | 2002-07-31 | 2006-12-26 | Kyocera Corporation | Surface acoustic wave device and method for manufacturing same |
JP2005093978A (ja) | 2003-08-12 | 2005-04-07 | Seiko Instruments Inc | 半導体装置の製造方法 |
US7393771B2 (en) * | 2004-06-29 | 2008-07-01 | Hitachi, Ltd. | Method for mounting an electronic part on a substrate using a liquid containing metal particles |
JP3964911B2 (ja) * | 2004-09-03 | 2007-08-22 | 松下電器産業株式会社 | バンプ付き基板の製造方法 |
JP4084834B2 (ja) * | 2005-03-29 | 2008-04-30 | 松下電器産業株式会社 | フリップチップ実装方法およびバンプ形成方法 |
KR20100009540A (ko) * | 2007-05-15 | 2010-01-27 | 히다치 가세고교 가부시끼가이샤 | 회로 접속 재료 및 회로 부재의 접속 구조 |
CN102206480A (zh) * | 2007-10-02 | 2011-10-05 | 日立化成工业株式会社 | 连接材料作为电路连接材料的应用 |
US20090278213A1 (en) * | 2008-05-08 | 2009-11-12 | International Business Machines Corporation | Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array |
EP2326155A4 (en) * | 2008-09-29 | 2012-01-11 | Sharp Kk | SUBSTRATE MODULE AND METHOD FOR THE PRODUCTION THEREOF |
JP5533665B2 (ja) * | 2008-11-28 | 2014-06-25 | 富士通株式会社 | 電子装置の製造方法、電子部品搭載用基板及びその製造方法 |
CN107254263A (zh) * | 2012-08-24 | 2017-10-17 | 迪睿合电子材料有限公司 | 各向异性导电膜的制造方法和各向异性导电膜 |
JP6321910B2 (ja) * | 2013-03-26 | 2018-05-09 | 日東電工株式会社 | 封止シート、半導体装置の製造方法及び封止シート付き基板 |
KR101628440B1 (ko) * | 2013-10-31 | 2016-06-08 | 제일모직주식회사 | 이방성 도전 필름 및 이를 이용한 반도체 장치 |
CN106415938B (zh) * | 2014-03-31 | 2019-09-06 | 迪睿合株式会社 | 各向异性导电膜及其制备方法 |
KR101900175B1 (ko) * | 2014-06-02 | 2018-09-18 | 후지필름 가부시키가이샤 | 산화물 입자 및 그 제조 방법, 산화물 입자 분산액, 산화물 입자 박막의 형성 방법, 박막 트랜지스터, 그리고 전자 소자 |
JP6750197B2 (ja) * | 2015-07-13 | 2020-09-02 | デクセリアルズ株式会社 | 異方性導電フィルム及び接続構造体 |
JP6945276B2 (ja) * | 2016-03-31 | 2021-10-06 | デクセリアルズ株式会社 | 異方性導電接続構造体 |
-
2016
- 2016-03-31 JP JP2016073087A patent/JP6945276B2/ja active Active
-
2017
- 2017-03-27 CN CN201780017937.1A patent/CN108780763B/zh active Active
- 2017-03-27 KR KR1020187013065A patent/KR102081570B1/ko active IP Right Grant
- 2017-03-27 US US16/077,785 patent/US10602619B2/en active Active
- 2017-03-27 WO PCT/JP2017/012408 patent/WO2017170412A1/ja active Application Filing
- 2017-03-29 TW TW106110549A patent/TWI759290B/zh active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0997814A (ja) * | 1995-09-28 | 1997-04-08 | Nec Corp | 電子部品の接続構造及び製造方法 |
US6222281B1 (en) * | 1998-04-06 | 2001-04-24 | Seiko Epson Corporation | IC chip, IC assembly, liquid crystal device, and electric apparatus |
JP2004186411A (ja) * | 2002-12-03 | 2004-07-02 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2004214374A (ja) * | 2002-12-27 | 2004-07-29 | Toshiba Matsushita Display Technology Co Ltd | 半導体素子及び液晶表示パネル |
JP2008047943A (ja) * | 2007-11-01 | 2008-02-28 | Renesas Technology Corp | 半導体装置 |
JP2012049398A (ja) * | 2010-08-27 | 2012-03-08 | Fujifilm Corp | 導電接合構造、実装構造体及び導電接合方法 |
CN104145329A (zh) * | 2012-03-05 | 2014-11-12 | 迪睿合电子材料有限公司 | 使用各向异性导电材料的连接方法及各向异性导电接合体 |
JP2015028920A (ja) * | 2013-06-26 | 2015-02-12 | 積水化学工業株式会社 | 接続構造体 |
WO2015115657A1 (ja) * | 2014-02-03 | 2015-08-06 | デクセリアルズ株式会社 | 接続体 |
JP2015146379A (ja) * | 2014-02-03 | 2015-08-13 | デクセリアルズ株式会社 | 接続体 |
JP2016029698A (ja) * | 2014-07-22 | 2016-03-03 | デクセリアルズ株式会社 | 接続体、及び接続体の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111179750A (zh) * | 2019-12-12 | 2020-05-19 | 武汉华星光电技术有限公司 | 显示面板的结构和其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
CN108780763B (zh) | 2022-12-06 |
TWI759290B (zh) | 2022-04-01 |
TW201804583A (zh) | 2018-02-01 |
WO2017170412A1 (ja) | 2017-10-05 |
KR20180066178A (ko) | 2018-06-18 |
KR102081570B1 (ko) | 2020-02-26 |
US10602619B2 (en) | 2020-03-24 |
US20190053383A1 (en) | 2019-02-14 |
JP2017183664A (ja) | 2017-10-05 |
JP6945276B2 (ja) | 2021-10-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108780763A (zh) | 各向异性导电连接构造体 | |
KR101886909B1 (ko) | 이방성 도전 접속 재료, 접속 구조체, 접속 구조체의 제조 방법 및 접속 방법 | |
WO2012005144A1 (ja) | 異方性導電接着剤、その製造方法、接続構造体及びその製造方法 | |
KR101994507B1 (ko) | 이방성 도전 재료를 사용한 접속 방법 및 이방성 도전 접합체 | |
KR20120042635A (ko) | 실장체의 제조 방법, 접속 방법 및 이방성 도전막 | |
JP5738013B2 (ja) | 異方性導電フィルム、異方性導電フィルムの製造方法、電子部品の接続方法、異方性導電接続体 | |
US10435601B2 (en) | Adhesive agent and connection structure | |
JP6196131B2 (ja) | プレス接着用金属箔及び電子部品パッケージ | |
JP2010251336A (ja) | 異方性導電フィルム及びこれを用いた接続構造体の製造方法 | |
JP6430148B2 (ja) | 接着剤及び接続構造体 | |
WO2018150897A1 (ja) | 異方性導電接続構造体、異方性導電接続構造体の製造方法、異方性導電フィルム、及び異方性導電ペースト | |
WO2020203295A1 (ja) | 接着剤組成物 | |
JP7386773B2 (ja) | 異方性導電接着剤、接続構造体、異方性導電接続方法、及び接続構造体の製造方法 | |
JP6431572B2 (ja) | 接続フィルム、接続フィルムの製造方法、接続構造体、接続構造体の製造方法及び接続方法 | |
JP6196132B2 (ja) | プレス接着用金属箔及び電子部品パッケージ | |
CN105814675B (zh) | 电子部件、连接体、连接体的制造方法及电子部件的连接方法 | |
KR20150034645A (ko) | 접속 필름, 접속 구조체, 접속 구조체의 제조 방법, 접속 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1260562 Country of ref document: HK |
|
GR01 | Patent grant | ||
GR01 | Patent grant |