TWI754689B - 溝槽式閘極igbt - Google Patents

溝槽式閘極igbt Download PDF

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TWI754689B
TWI754689B TW106136833A TW106136833A TWI754689B TW I754689 B TWI754689 B TW I754689B TW 106136833 A TW106136833 A TW 106136833A TW 106136833 A TW106136833 A TW 106136833A TW I754689 B TWI754689 B TW I754689B
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trench
gate
emitter
channel layer
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TW201839999A (zh
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神田良
松浦仁
菊地修一
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日商瑞薩電子股份有限公司
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Abstract

本發明提供一種高性能之溝槽式閘極IGBT。 本實施形態之溝槽式閘極IGBT具備：半導體基板11；通道層15，其設置於半導體基板11；浮動P層12，其為設置於通道層15之兩側之2個浮動P型層12，且較通道層15更深；射極溝槽13，其為配置於2個浮動P層12之間之2個射極溝槽13，且與浮動P層12分別相接；至少2個閘極溝槽14，其等配置於2個射極溝槽13之間；及源極擴散層19，其配置於2個閘極溝槽14之間，與閘極溝槽14分別相接。

Description

溝槽式閘極IGBT
本發明關於一種溝槽式閘極IGBT。
於專利文獻1中揭示有溝槽式閘極IGBT(Insulated Gate Bipolar Transistor：絕緣閘雙極電晶體)。專利文獻1之圖31之IGBT係具備配置於P型浮動區域之間的溝槽式閘極。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2013-140885號公報
於此種溝槽式閘極IGBT中，有欲進而提高性能之期望。
其他課題與新穎之特徵將由本說明書之記述及附加圖式而明確。
根據一實施形態，溝槽式閘極IGBT具備：2個浮動層；2個射極溝槽，其以與浮動層相接之方式配置於2個浮動層之間；及至少2個閘極溝槽，其等配置於上述2個射極溝槽之間。
根據上述一實施形態，可提供一種高性能之溝槽式閘極IGBT。
1:溝槽式閘極IGBT
2:溝槽式閘極IGBT
3:溝槽式閘極IGBT
11:半導體基板
12:FLP層
13:射極溝槽
14:閘極溝槽
14a:閘極溝槽
15:通道層
15a:通道層
15b:通道層
17:絕緣膜
18:射極電極
19:源極
21:接點
21a:接點
21b:接點
31:閘極電極
32:P型井
35:多晶矽電極
36:接點
X:方向
Y:方向
Z:方向
圖1係模式性顯示本實施形態1之IGBT之構成之俯視圖。
圖2係模式性顯示本實施形態1之IGBT之構成之剖視圖。
圖3係模式性顯示變化例1之IGBT之構成之剖視圖。
圖4係模式性顯示本實施形態2之IGBT之構成之剖視圖。
圖5係模式性顯示本實施形態3之IGBT之構成之剖視圖。
為了說明之明確化，以下之記載及圖式進行適當省略、及簡略化。另，於各圖式中，對同一要件標註同一符號，且根據需要省略重複說明。
首先，對於專利文獻1所示之溝槽式閘極IGBT(Insulated Gate Bipolar Transistor)進行說明。專利文獻1之溝槽式閘極IGBT(以下，亦簡稱為IGBT)係具有P型浮動區域(亦稱為浮動P型層，以下，作為FLP層)。可藉由提高載子蓄積效果，而降低集極、射極間電壓Vce(sat)降低。
進而，如專利文獻1之圖31所示之IGBT係具有與金屬射極電極連接之溝槽(以下，為射極溝槽)、及與金屬閘極電極連接之溝槽(以下，為閘極溝槽)。且，閘極溝槽配置於2個射極溝槽之間。即，於2個FLP層之間，以射極溝槽、閘極溝槽、射極溝槽之順序配置。因藉由該構造(以下，為EGE構造)，可降低反饋電容Cres，故可提高開關特性。
於專利文獻1之溝槽式閘極IGBT中，可進行集極、射極間電壓Vce(sat)之降低與開關特性之提高。另，FLP層較溝槽變得更深之理由在於，緩和溝槽底端部之電場，並提高耐壓BVces。若FLP層較淺，FLP層之寬度擴大，則耐壓BVces降低。另，嚴謹而言，對於輸入電容Cies，使 反饋電容Cres縮小較為重要。
如專利文獻1之圖31所示之溝槽式閘極IGBT中，與通常之單元相比，閘極溝槽之佔有率變小。因此，存在輸入電容Cies變小，而易受雜訊影響之問題、及ESD(ElectroStatic Discharge：靜電放電)耐受量降低等之問題。該情況，於電流帶越小(即，晶片尺寸越小)之產品中越嚴重。
本實施形態之溝槽式閘極IGBT係以兼顧特性提高、與雜訊耐受性、ESD耐受量提高兩者為目的而發明者。本實施形態之溝槽式閘極IGBT於小電流用途中尤其有效。另，本實施形態之溝槽式閘極IGBT之基本構造、及製造方法，可適當參照專利文獻1所揭示之內容。
實施形態1.
對於本實施形態1之溝槽式閘極IGBT，使用圖1、及圖2進行說明。圖1係模式性顯示溝槽式閘極IGBT1(以下，簡稱為IGBT1)之單元之主要部分之構成之俯視圖。圖2係圖1之II-II剖視圖，顯示了2個相鄰之浮動P型層12之間之構成。另，於圖中，為了說明之明確化，而將半導體基板11之厚度方向(深度方向)設為Z方向，將與Z方向正交之平面設為XY平面。於XY平面中，Y方向為後述之線狀之閘極溝槽14之長邊方向，X方向為閘極溝槽14之短邊方向。X方向與Y方向正交。
IGBT1具備半導體基板11、浮動P型層(以下，為FLP層)12、射極溝槽13、閘極溝槽14、通道層15、絕緣膜17、射極電極18、源極擴散層19、接點21、閘極電極31、P型井32、及接點36。
半導體基板11為例如單晶矽晶圓，為導入了磷(P)等雜質之N型基板。於半導體基板11，形成有FLP層12、射極溝槽13、閘極溝槽14、及通道層15。於半導體基板11之上，形成有絕緣膜17、及射極電極18。另， 雖省略圖示，但半導體基板11之背面側為P型之集極。
FLP層12係導入了硼等雜質之P型井。FLP層12之電位為浮動。如圖1、2所示，於單元中，設置有2個浮動P層12。2個FLP層12係於X方向隔開設置。各FLP層12於XY俯視時為矩形狀。
如圖2所示，於相鄰之2個FLP層之間，設置有2個射極溝槽13。2個射極溝槽13於X方向隔開設置。射極溝槽13係以與FLP層12相接之方式配置。即，2個射極溝槽13之一者(例如，+X側之射極溝槽13)與2個FLP層12之一者(例如，+X側之FLP層12)相接，2個射極溝槽13之另一者(例如，-X側之射極溝槽)與2個FLP層12之另一者(例如，-X側之FLP層12)相接。
於圖1所示之XY俯視時，FLP層12形成為矩形狀。於XY俯視時，射極溝槽13形成為
Figure 106136833-A0305-02-0006-8
字狀。且，於XY俯視時，
Figure 106136833-A0305-02-0006-9
之字形狀之射極溝槽13與矩形狀之FLP層12之3邊相接。FLP層12較射極溝槽13更深。藉此，可使溝槽底端部之電場緩和，且使耐壓BVces提高。
進而，如圖1所示，於FLP層12之上，形成有多晶矽電極35。於X方向中，多晶矽電極35以跨越FLP層12之方式形成。因而，X方向中之多晶矽電極35之端部，形成於射極溝槽13之上。
且，多晶矽電極35係為了獲取射極電位，而與射極溝槽13連接。多晶矽電極35，例如由多晶矽膜形成。於多晶矽電極35之上設置有接點36。接點36與多晶矽電極35接觸。因此，接點36經由多晶矽電極35與射極溝槽13連接。射極溝槽13經由接點36，與射極電位連接。
如圖2所示，於2個射極溝槽13之間，配置有2個閘極溝槽14。2個閘極溝槽14於X方向隔開配置。
如圖1所示，閘極溝槽14係將Y方向設為長邊方向之線狀之溝槽。於 XY俯視時，閘極溝槽14係自2個射極溝槽13之間之位置至與閘極電極31重疊之位置，沿Y方向延伸。即，閘極溝槽14之+Y方向之端部，與閘極電極31重疊。
進而，於閘極溝槽14之+Y方向之端部，2個閘極溝槽14經由閘極溝槽14a而連接。經由閘極電極31，對閘極溝槽14供給閘極電位。閘極電極31，例如，由與多晶矽電極35同層之多晶矽膜形成。閘極電極31形成於P型井32之上。
另，閘極溝槽14係例如具備：閘極氧化膜，其形成於溝槽之內表面；及矽膜，其嵌設於溝槽。射極溝槽13可藉由與閘極溝槽14同樣之製程而形成。
進而，如圖2所示，於半導體基板11之表面形成有通道層15。通道層15配置於2個射極溝槽13之間。通道層15成為導入了硼等雜質之P+型井。通道層15成為較FLP層12更淺之井。即，FLP層12形成得較通道層15更深。
於半導體基板11上，形成有絕緣膜17。絕緣膜17為矽氧化膜等。於絕緣膜17上形成有射極電極18。射極電極18為例如多晶矽膜，可於與多晶矽電極35相同之層形成。絕緣膜17具有接點21。於接點21，埋設有射極電極18。即，射極電極18經由設置於絕緣膜17之接點21，而與通道層15連接。如圖1所示之XY俯視所示，接點21形成為將Y方向設為長邊方向之線狀。
進而，於2個閘極電極14之間，形成有FET(Field Effect Transistor：場效電晶體)之源極擴散層19。源極擴散層19形成於半導體基板11之通道層15之表面。源極擴散層19與閘極溝槽14相接。源極擴散層19為N+型之 射極擴散層，經由接點21，而與射極電位連接。
如此，於2個射極溝槽13之間，配置有2個閘極溝槽14。IGBT1於X方向中，於相鄰之2個FLP層12之間，具有以射極溝槽13、閘極溝槽14、閘極溝槽14、射極溝槽13之順序配置之構造(以下，為EGGE構造)。於EGGE構造中，於2個FLP層之間12，配置2個射極溝槽13，於2個射極溝槽13之間，至少配置2個閘極溝槽14。
藉由EGGE構造，可維持EGE構造之優點，且增加閘極溝槽14之佔有率。藉此，可增加輸入電容Cies。因此，雜訊耐受量，ESD耐受量提高。該情況例如於晶片尺寸較小之低電流用途中更為有效。尤其，IGBT1適於小電流用途之變流器。
當然，配置於2個射極溝槽13之間之閘極溝槽14之數量未限於2條，亦可為3條以上。因於EGGE構造中配置有複數條閘極溝槽14，故可具有電容值或電流密度之控制性。藉由浮動構造，可使集極、射極間電壓Vce(sat)降低。又，構成為不使FLP12層藉由射極溝槽13而與閘極溝槽14接觸。即，射極溝槽13介於閘極溝槽14與FLP層12之間。因此，可保持反饋電容Cres之降低效果，且具有設計之柔軟性。
變化例1.
對於實施形態1之變化例1之溝槽式閘極IGBT1a(以下，簡稱為IGBT1a)，使用圖3進行說明。圖3係模式性顯示IGBT1a之構成之XZ剖視圖。另，因IGBT1a之基本構成與圖1、圖2所示之IGBT1同樣，故適當省略說明。於圖3中，將配置於射極溝槽13與閘極溝槽14之間之通道層15顯示為通道層15a、15b。
IGBT1a進而具備：源極擴散層19，其配置於射極溝槽13與閘極溝槽 14之間。於溝槽式閘極。IGBT1a中，除2個閘極溝槽14之間之領域外，源極擴散層19亦設置於閘極溝槽14與射極溝槽13之間之區域。即，於通道層15a、15b之表面形成有源極擴散層19。於X方向中，於1個閘極溝槽14之兩側配置有源極擴散層19。藉此，可提高源極密度，且可流通更大之電流。對於設置於閘極溝槽14與射極溝槽13之間之源極擴散層19以外，因與實施形態1同樣而省略說明。
另，於實施形態1之圖2所示之構成中，成為未於閘極溝槽14與射極溝槽13之間之領域設置源極擴散層19之構成。即，僅於2個閘極溝槽14之間，設置有源極擴散層19。該情形時，可使閘極溝槽14與射極溝槽13之間之無效區域變窄。因而，可收縮無效區域，並使面積變小。
源極擴散層19之大小只要根據流動之電流調整即可。例如，藉由增大源極擴散層19之面積，可增大電流，藉由減小源極擴散層19，可減小電流。藉由減小源極擴散層19，可減小負載短路時流動之短路電流。可根據源極擴散層19之大小，調整短路耐受量。
實施形態2.
對於本實施形態之溝槽式閘極IGBT2(以下，簡稱為IGBT2)，使用圖4進行說明。圖4係模式性顯示IGBT2之構成之剖視圖。對於圖4，亦與圖3同樣，將配置於射極溝槽13與閘極溝槽14之間之通道層15顯示為通道層15a、15b。
於本實施形態中，設置於絕緣膜17之接點21之配置不同。另，對於接點21之配置以外之基本構成，因與實施形態1之IGBT1同樣，而省略說明。
於本實施形態中，於通道層15a、15b之上未形成接點21，即，通道 層15a、15b由絕緣膜17覆蓋。因此，配置於射極溝槽13與閘極溝槽14之間之通道層15a、15b為浮動。
藉由將通道層15a、15b設為浮動，蓄積載子(電洞)不會被接點吸收。因此，蓄積效果提高，可降低集極、射極間電壓Vce(sat)。
實施形態2.
對於本實施形態之IGBT3，使用圖5進行說明。圖5係模式性顯示IGBT3之構成之剖視圖。於本實施形態中，設置於絕緣膜17之接點21之配置不同。另，對於接點21之配置以外之基本構成，因與實施形態1同樣，而省略說明。
於圖5中，亦與圖3，圖4同樣，將配置於射極溝槽13與閘極溝槽14之間之通道層15顯示為通道層15a、15b。進而，將通道層15a之上之接點21顯示為接點21a，將通道層15b之上之接點21顯示為接點21b。
接點21a自射極溝槽13之上延伸至通道層15a之上。即，接點21a跨越射極溝槽13與通道層15a之邊界。接點21b，自射極溝槽13之上延伸至通道層15b之上。即，接點21a跨越射極溝槽13與通道層15a之邊界。
藉此，可縮短自射極溝槽13至閘極溝槽之無效區域之距離。因此，可收縮無效區域，並可減小面積。
例如，於上述實施形態之半導體裝置中，亦可構成為使半導體基板、半導體層、擴散層(擴散區域)等之導電型(P型或N型)反轉。因此，亦可於將N型及P型之一者之導電型設為第1導電型，將另一者之導電型設為第2導電型之情形下，將第1導電型設為P型，將第2導電型設為N型，又可與之相反，將第1導電型設為N型，第2導電型設為P型。
以上，雖基於實施形態而具體地說明由本發明者完成之發明，但本 發明並非限定於已述之實施形態，在未脫離其主旨之範圍內，亦可進行各種變更。
1‧‧‧溝槽式閘極IGBT
11‧‧‧半導體基板
12‧‧‧FLP層
13‧‧‧射極溝槽
14‧‧‧閘極溝槽
15‧‧‧通道層
17‧‧‧絕緣膜
18‧‧‧射極電極
19‧‧‧源極擴散層
21‧‧‧接點
X‧‧‧方向
Z‧‧‧方向

Claims (15)

  1. 一種溝槽式閘極IGBT(Insulated Gate Bipolar Transistor)，其具備：基板；第1導電型之通道層，其設置於上述基板；2個第1導電型之浮動層，其等係於上述通道層之兩側的各個側設置1個浮動層，且該等第1導電型之浮動層較上述通道層深；射極溝槽，其為配置於上述2個浮動層之間之2個射極溝槽，且與上述浮動層分別相接；至少2個閘極溝槽，其等配置於上述2個射極溝槽之間；源極擴散層，其配置於上述2個閘極溝槽之間，與上述閘極溝槽分別相接；及絕緣膜，其位於以下之頂面上：上述通道層、上述2個浮動層、上述2個射極溝槽、上述至少2個閘極溝槽之各個及上述源極擴散層；其中上述絕緣膜具有：複數個通孔(via hole)以提供接點(contact)至上述通道層之上述頂面，其中包括：第1通孔，用以相接(contact)至上述至少2個閘極溝槽之各個之間的上述通道層；第2通孔，用以相接至上述2個閘極溝槽之第1個與上述2個射極溝槽之第1個之間之上述通道層；及第3通孔，用以相接至上述2個閘極溝槽之第2個與上述2個射極溝槽之第2個之間之上述通道層。
  2. 如請求項1之溝槽式閘極IGBT，其中於上述射極溝槽與上述閘極溝 槽之間，未配置上述源極擴散層。
  3. 如請求項1之溝槽式閘極IGBT，其中進而具備配置於上述射極溝槽與上述閘極溝槽之間的源極擴散層。
  4. 如請求項1之溝槽式閘極IGBT，其中配置於上述閘極溝槽與上述射極溝槽之間的上述通道層為浮動。
  5. 如請求項1之溝槽式閘極IGBT，其中上述接點自上述射極溝槽之上延伸至上述射極溝槽與上述閘極溝槽之間之上述通道層之上。
  6. 如請求項1之溝槽式閘極IGBT，其中上述浮動層形成為較上述射極溝槽深。
  7. 如請求項1之溝槽式閘極IGBT，其進而具備：於上述絕緣膜之頂面上之射極電極，其中至上述通道層之上述頂面之上述接點包括：上述射極電極至上述通道層之接點。
  8. 如請求項1之溝槽式閘極IGBT，其中於俯視時，各個浮動層係形成為矩形狀，且與各個浮動層分別關聯之射極溝槽係形成為：與關聯之浮動層之3個側相接之
    Figure 106136833-A0305-02-0014-6
    字狀。
  9. 一種溝槽式閘極IGBT(Insulated Gate Bipolar Transistor)，其具 備：基板；第1導電型之通道層，其設置於上述基板；第一第1導電型之浮動層，其設置於上述通道層之第一側；第二第1導電型之浮動層，其設置於上述通道層之與上述第一側相對之第二側；第一射極溝槽，其配置於上述第一第1導電型之浮動層與上述通道層之上述第一側之間的上述通道層中，上述第一射極溝槽與上述第一第1導電型之浮動層及上述通道層之上述第一側兩者連接；第二射極溝槽，其配置於上述第二第1導電型之浮動層與上述通道層之上述第二側之間的上述通道層中，上述第二射極溝槽與上述第二第1導電型之浮動層及上述通道層之上述第二側兩者連接；第一閘極溝槽及第二閘極溝槽，其等配置於上述第一與第二射極溝槽之間的上述通道層中；第一源極擴散區域及第二源極擴散區域，其等配置於上述第一與第二閘極溝槽之間的上述通道層中，上述第一源極擴散區域與上述第一閘極溝槽相接，且上述第二源極擴散區域與上述第二閘極溝槽相接；絕緣膜，其位於上述通道層之頂面、上述第一及第二浮動層之頂面、上述第一及第二射極溝槽之頂面、上述第一及二閘極溝槽之頂面，及上述第一及第二源極擴散區域之頂面；及射極電極，其位於上述絕緣膜之頂面；其中上述第一及第二浮動層較上述通道層深；且上述絕緣膜具有：複數個通孔以提供上述射極電極之接點至上述通 道層之上述頂面，其中包括：第1通孔，用以相接至上述2個閘極溝槽之各個之間之上述通道層；第2通孔，用以相接至上述第一閘極溝槽與上述第一射極溝槽之間之上述通道層；及第3通孔，用以相接至上述第二閘極溝槽與上述第二射極溝槽之間之上述通道層。
  10. 如請求項9之溝槽式閘極IGBT，其中於上述第一射極溝槽與上述第一閘極溝槽之間或於上述第二射極溝槽與上述第二閘極溝槽之間，未配置源極擴散區域。
  11. 如請求項9之溝槽式閘極IGBT，其中於上述第一射極溝槽與上述第一閘極溝槽之間配置有第三源極擴散區域，於上述第二射極溝槽與上述第二閘極溝槽之間配置有第四源極擴散區域。
  12. 如請求項9之溝槽式閘極IGBT，其中配置於上述閘極溝槽與上述射極溝槽之間的上述通道層為浮動。
  13. 如請求項9之溝槽式閘極IGBT，其中對於上述第一及第二射極溝槽之各者，上述射極電極係與上述射極溝槽之上述頂面之一部分及上述射極溝槽與相關之閘極溝槽之間之上述通道層之上述頂面之一部分兩者相接。
  14. 如請求項9之溝槽式閘極IGBT，其中上述第一及第二浮動層係形成為較上述第一及第二射極溝槽深。
  15. 如請求項9之溝槽式閘極IGBT，其中於俯視時，上述第一及第二浮動層之各者係形成為矩形狀，且與上述第一及第二浮動層分別關聯之上述第一及第二射極溝槽之各者係形成為：與關聯之浮動層之3個側相接之
    Figure 106136833-A0305-02-0017-7
    字狀。
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