CN108231865B - 沟槽栅极igbt - Google Patents

沟槽栅极igbt Download PDF

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CN108231865B
CN108231865B CN201711263226.0A CN201711263226A CN108231865B CN 108231865 B CN108231865 B CN 108231865B CN 201711263226 A CN201711263226 A CN 201711263226A CN 108231865 B CN108231865 B CN 108231865B
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trench
gate
emitter
layer
trenches
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CN108231865A (zh
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神田良
松浦仁
菊地修一
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Renesas Electronics Corp
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Abstract

本公开涉及沟槽栅极IGBT。提供了一种高性能的沟槽栅极IGBT。根据一个实施例的沟槽栅极IGBT包括：半导体衬底(11)；设置在半导体衬底(11)上的沟道层(15)；设置在沟道层(15)两侧的两个浮置P型层(12)，浮置P型层(12)比沟道层(15)深；设置在两个浮置P型层(12)之间的两个发射极沟槽(13)，发射极沟槽(13)分别与浮置P型层(12)接触；设置在两个发射极沟槽(13)之间的至少两个栅极沟槽(14)；和设置在两个栅极沟槽14之间的源极扩散层(19)，源极扩散层(19)与栅极沟槽(14)中的每一个接触。

Description

沟槽栅极IGBT
相关申请的交叉引用
本申请基于2016年12月22日提交的日本专利申请No.2016-249360并要求其优先权利益，该申请的全部内容通过引用整体地并入本文。
技术领域
本发明涉及沟槽栅极IGBT。
背景技术
日本未审查专利申请公开No.2013-140885公开了沟槽栅极IGBT(绝缘栅双极晶体管)。日本未审查专利申请公开No.2013-140885的图31中所示的IGBT包括设置在P型浮置区域之间的沟槽栅极。
发明内容
需要进一步改善这种沟槽栅极IGBT的性能。
从下面的描述和附图中，本发明要解决的其它问题和新颖特征将变得明显。
根据一个实施例，沟槽栅极IGBT包括两个浮置层、设置在两个浮置层之间以与浮置层接触的两个发射极沟槽以及设置在两个发射极沟槽之间的至少两个栅极沟槽。
根据这个实施例，可以提供高性能沟槽栅极IGBT。
附图说明
从以下结合附图对特定实施例的描述中，上述和其它方面、优点和特征将更加明显，在附图中：
图1是示意性示出根据第一实施例的IGBT的构造的平面图；
图2是示意性示出根据第一实施例的IGBT的构造的截面图；
图3是示意性示出根据第一变形例的IGBT的构造的截面图；
图4是示意性示出根据第二实施例的IGBT的构造的截面图；和
图5是示意性示出根据第三实施例的IGBT的构造的截面图。
具体实施方式
以下的描述和附图被适当地省略和简化以阐明说明。在所有附图中，相同的元件由相同的附图标记表示，并且根据需要省略重复的说明。
首先，将描述在日本未审查专利申请公开No.2013-140885中公开的沟槽栅极IGBT(绝缘栅双极晶体管)。在日本未审查专利申请公开No.2013-140885中公开的沟槽栅极IGBT(下文中也简称为IGBT)包括P型浮置区域(也被称为浮置P型层；下文中称为FLP层)。可以通过增强载流子存储效应来减小集电极-发射极电压Vce(sat)。
此外，日本未审查专利申请公开No.2013-140885的图31中所示的IGBT包括连接到金属发射极电极的沟槽(该沟槽在下文中被称为发射极沟槽)以及连接到金属栅极电极的沟槽(该沟槽在下文中被称为栅极沟槽)。栅极沟槽设置在两个发射极沟槽之间。具体而言，在两个FLP层之间按顺序设置发射极沟槽、栅极沟槽和发射极沟槽。利用该结构(以下称为EGE结构)，可以减小反馈电容Cres，这导致开关特性的改善。
在日本未审查专利申请公开No.2013-140885中公开的沟槽栅极IGBT中，可以减小集电极-发射极电压Vce(sat)，并且可以改善开关特性。注意，FLP层比沟槽深。这是为了放松每个沟槽底端的电场，从而改善鲁棒性BVces。由于FLP层较浅，所以如果FLP层的宽度较宽，则鲁棒性BVces下降。更具体地说，减小反馈电容Cres相对于输入电容Cies是重要的。
在日本未审查专利申请公开No.2013-140885的图31中所示的沟槽栅极IGBT中，栅极沟槽的占有率小于典型单元的占有率。这导致输入电容Cies减小和IGBT可能受到噪声影响并且ESD(静电放电)容限降低的问题。在具有小电流带(即，具有小芯片尺寸)的产品中，这些问题变得更为严重。
根据本实施例的沟槽栅极IGBT已经被设计为既实现特性的改善又实现抗噪声性和ESD容限的改善。根据该实施例的沟槽栅极IGBT对于小电流应用特别有效。至于根据本实施例的沟槽栅极IGBT的基本构造及其制造方法，根据需要参见日本未审查专利申请公开No.2013-140885中公开的内容。
第一实施例
将参照图1和图2描述根据第一实施例的沟槽栅极IGBT。图1是示意性示出沟槽栅极IGBT 1(以下简称为IGBT 1)的单元的主要部分的构造的平面图。图2示出了沿着图1中所示的线II-II截取的截面图，并示出了两个相邻的浮置P型层12之间的构造。在图中，半导体衬底11的厚度方向(深度方向)被定义为Z方向，并且与Z方向垂直的平面被定义为XY平面，以用于阐明说明。在XY平面中，Y方向对应于下面将描述的线性栅极沟槽14的纵向方向，并且X方向对应于栅极沟槽14的短轴方向。X方向和Y方向相互垂直。
IGBT 1包括半导体衬底11、浮置P型层(以下称为FLP层)12、发射极沟槽13、栅极沟槽14、沟道层15、绝缘膜17、发射极电极18、源极扩散层19、接触件21、栅极电极31、P型阱32和接触件36。
半导体衬底11例如是单晶硅晶片，并被用作其中引入了诸如磷(P)的杂质的N型衬底。在半导体衬底11上，形成FLP层12、发射极沟槽13、栅极沟槽14和沟道层15。在半导体衬底11上方，形成绝缘膜17和发射极电极18。尽管未示出，但是半导体衬底11的背表面用作p型集电极。
每个FLP层12是其中引入了诸如硼的杂质的P型阱。FLP层12的电位是浮置的。如图1和图2所示，单元设置有两个浮置P型层12。两个FLP层12被设置为在X方向上彼此间隔开。在XY平面图中，每个FLP层12具有矩形形状。
如图2所示，在两个相邻的FLP层之间设置两个发射极沟槽13。两个发射极沟槽13被设置为在X方向上彼此间隔开。每个发射极沟槽13被布置为与对应的FLP层12接触。具体地，两个发射极沟槽13中的一个(例如，+X侧发射极沟槽13)与两个FLP层12中的一个(例如，+X侧FLP层12)接触，并且两个发射极沟槽13中的另一个(例如，-X侧发射极沟槽)与两个FLP层12中的另一个(例如，-X侧FLP层12)接触。
在图1中所示的XY平面图中，FLP层12各自形成为矩形形状。在XY平面图中，发射极沟槽13各自形成为U形。在XY平面图中，具有U形的每个发射极沟槽13与矩形FLP层12的三个侧面接触。FLP层12比发射极沟槽13深。利用该构造，可以放松沟槽底端的电场并可以改善鲁棒性BVces。
此外，如图1中所示，分别在FLP层12上形成多晶硅电极35。在X方向上，多晶硅电极35各自形成为跨过对应的FLP层12。因此，每个多晶硅电极35的X方向上的端部分别形成在发射极沟槽13上。
每个多晶硅电极35连接到发射极沟槽13以获得发射极电位。每个多晶硅电极35由例如多晶硅膜形成。接触件36形成在多晶硅电极35上。每个接触件36与对应的多晶硅电极35接触。因此，每个接触件36通过对应的多晶硅电极35连接到发射极沟槽13。发射极沟槽13各自通过对应的接触件36连接到发射极电位。
如图2中所示，两个栅极沟槽14设置在两个发射极沟槽13之间。两个栅极沟槽14设置为在X方向上彼此分开。
如图1中所示，栅极沟槽14是纵向方向对应于Y方向的线性沟槽。在XY平面图中，栅极沟槽14在Y方向上从两个发射极沟槽13之间的位置延伸到与栅极电极31重叠的位置。换句话说，每个栅极沟槽14的+Y方向上的一端与栅极电极31重叠。
此外，在每个栅极沟槽14的+Y方向上的一端，两个栅极沟槽14通过栅极沟槽14a连接。栅极沟槽14通过栅极电极31被供应有栅极电位。栅极电极31由例如多晶硅膜形成，该多晶硅膜形成每个多晶硅电极35。栅极电极31形成在P型阱32上。
注意，栅极沟槽14每个都包括例如形成在沟槽的内表面上的栅极氧化物膜和掩埋在沟槽中的硅膜。每个发射极沟槽13可以通过与用于形成栅极沟槽14类似的过程来形成。
另外，如图2中所示，在半导体衬底11的表面上各自形成沟道层15。各沟道层15设置在两个发射极沟槽13之间。各沟道层15是其中引入了诸如硼的杂质的P+型阱。各沟道层15是比FLP层12浅的阱。换句话说，FLP层12形成在比沟道层15深的位置处。
绝缘膜17形成在半导体衬底11上方。绝缘膜17例如是氧化硅膜。发射极电极18形成在绝缘膜17上。发射极电极18可以由形成每个多晶硅电极35的多晶硅膜形成。绝缘膜17包括接触件21。发射极电极18掩埋在每个接触件21中。具体地，发射极电极18通过形成在绝缘膜17中的每个接触件21连接到沟道层15。如图1中所示的XY平面中一样，每个接触件21被线性地形成，其中Y方向对应于其纵向方向。
此外，在两个栅极沟槽14之间形成FET(场效应晶体管)的源极扩散层19。源极扩散层19各自形成在半导体衬底11的每个沟道层15的表面上。源极扩散层19各自与栅极沟槽14接触。各源极扩散层19是N+型发射极扩散层，并且通过各接触件21连接到发射极电位。
以这种方式，两个栅极沟槽14设置在两个发射极沟槽13之间。IGBT 1具有在两个相邻的FLP层12之间在X方向上按顺序设置发射极沟槽13、栅极沟槽14、栅极沟槽14和发射极沟槽13的结构(在下文中称为EGGE结构)。在EGGE结构中，两个发射极沟槽13设置在两个FLP层12之间，并且至少两个栅极沟槽14设置在两个发射极沟槽13之间。
通过EGGE结构，可以增加栅极沟槽14的占用率，同时维持EGE结构的优点。相应地，输入电容Cies可以增加。这导致噪声容限和ESD容限的改善。这在例如芯片尺寸小的低电流应用中更有效。特别地，IGBT 1适用于小电流应用的逆变器。
设置在两个发射极沟槽13之间的栅极沟槽14的数量不限于两个，而是三个或更多个栅极沟槽14可以设置在两个发射极沟槽13之间。在EGGE结构中，设置多个栅极沟槽14，这提供了电容值和电流密度的可控制性。通过浮置结构，可以减小集电极-发射极电压Vce(sat)。各发射极沟槽13防止FLP层12与栅极沟槽14接触。换句话说，各发射极沟槽13插入在栅极沟槽14和FLP层12之间。因此，可以获得设计的灵活性，同时维持减小反馈电容Cres的效果。
第一变形例
将参照图3描述根据第一实施例的第一变形例的沟槽栅极IGBT1a(以下简称为IGBT 1a)。图3是示意性示出IGBT 1a的构造的XZ截面图。IGBT 1a的基本构造与图1及图2中所示的IGBT 1的基本构造相同，因此适当省略其描述。图3示出了各自设置在发射极沟槽13和栅极沟槽14之间作为沟道层15a和15b的沟道层15。
IGBT 1a还包括各自设置在发射极沟槽13和栅极沟槽14之间的源极扩散层19。在IGBT 1a中，源极扩散层19不仅设置在两个栅极沟槽14之间的区域中，也设置在栅极沟槽14和发射极沟槽13之间的区域中。具体地，在沟道层15a和15中的每一个的表面上形成源极扩散层19。在X方向上，在一个栅极沟槽14的两侧上均设置源极扩散层19。利用这种构造，可以增加源极密度并且可以使更大的电流流动。除了设置在栅极沟槽14和发射极沟槽13之间的源极扩散层19之外的组件与第一实施例中的组件类似，因此省略对其的描述。
在根据第一实施例的图2中所示的构造中，源极扩散层19未设置在栅极沟槽14与发射极沟槽13之间的区域中。换句话说，源极扩散层19仅设置在两个栅极沟槽14之间的区域。在这种情况下，可以减小栅极沟槽14与发射极沟槽13之间的无效区域的宽度。相应地，可以缩小无效区域并减小其面积。
可以取决于要流动的电流来调整各源极扩散层19的尺寸。例如，可以通过增加各源极扩散层19的面积来增加电流，并且可以通过减小各源极扩散层19的面积来减小电流。可以通过减小各源极扩散层19的尺寸来减小当负载短路时流动的短路电流。可以取决于各源极扩散层19的尺寸来调整短路容限。
第二实施例
将参照图4描述根据第二实施例的沟槽栅极IGBT 2(在下文中简称为IGBT 2)。图4是示意性示出IGBT 2的构造的截面图。与图3一样，图4还示出了各自设置在发射极沟槽13和栅极沟槽14之间作为沟道层15a和15b的沟道层15。
在第二实施例中形成在绝缘膜17中的接触件21的布置与在第一实施例中的不同。除了接触件21的布置以外，根据第二实施例的IGBT2的基本构造与根据第一实施例的IGBT1的基本构造类似，因此省略其描述。
在第二实施例中，接触件21没有形成在沟道层15a和15b上。换句话说，沟道层15a和15b各自被绝缘膜17覆盖。因此，各自设置在发射极沟槽13和栅极沟槽14之间的沟道层15a和15b是浮置的。
沟道层15a和15b浮置的构造防止存储的载流子(空穴)在接触件中被吸收。因此，存储效果增强，并且集电极-发射极电压Vce(sat)减小。
第三实施例
将参照图5描述根据第三实施例的IGBT 3。图5是示意性示出IGBT 3的构造的截面图。第三实施例与第一实施例的不同之处在于设置在绝缘膜17中的接触件21的布置。除了接触件21的布置以外，根据第三实施例的IGBT 3的基本构造与根据第一实施例的IGBT的基本构造类似，因此省略其描述。
像图3和图4一样，图5还示出了各自设置在发射极沟槽13和栅极沟槽14之间作为沟道层15a和15b的沟道层15。图5还示出了形成在沟道层15a上作为接触件21a的接触件21以及形成在沟道层15b上作为接触件21b的接触件21。
接触件21a从发射极沟槽13的上部延伸到沟道层15a的上部。换句话说，接触件21a跨过发射极沟槽13和沟道层15a之间的边界。接触件21b从发射极沟槽13的上部延伸到沟道层15b的上部。换句话说，接触件21a跨过发射极沟槽13和沟道层15a之间的边界。
利用这种构造，可以减小从发射极沟槽13到栅极沟槽的无效区域的距离。相应地，可以缩小无效区域并可以减小其面积。
例如，在根据上述实施例的半导体器件中，可以颠倒半导体衬底、半导体层、扩散层(扩散区域)等的导电类型(p型或n型)。因此，当n型和p型导电类型之一被定义为第一导电类型且另一导电类型被定义为第二导电类型时，第一导电类型可以是p型且第二导电类型可以是n型。相反，第一导电类型可以是n型且第二导电类型可以是p型。
尽管以上参照实施例详细描述了由本发明人作出的发明，但是本发明不限于上述实施例，并且可以在不偏离本发明的范围的情况下以各种方式进行修改。
尽管已经根据若干实施例描述了本发明，但是本领域技术人员将认识到，可以在所附权利要求的精神和范围内以各种修改来实践本发明，并且本发明不限于上述示例。
此外，权利要求的范围不受上述实施例的限制。
此外，注意，申请人的意图是即使在稍后审查期间进行修改也包含所有权利要求要素的等同物。

Claims (2)

1.一种沟槽栅极绝缘栅双极晶体管，包括：
衬底；
设置在所述衬底上的第一导电类型的沟道层；
设置在所述沟道层两侧的两个第一导电类型的浮置层，所述第一导电类型的浮置层比所述沟道层深；
设置在两个浮置层之间的第一发射极沟槽和第二发射极沟槽，所述第一发射极沟槽和第二发射极沟槽分别与浮置层接触；
设置在所述第一发射极沟槽和第二发射极沟槽之间的第一栅极沟槽和第二栅极沟槽，所述第一栅极沟槽设置在所述第一发射极沟槽附近，并且所述第二栅极沟槽设置在所述第二发射极沟槽附近；
设置在所述第一栅极沟槽和第二栅极沟槽之间的第一源极扩散层和第二源极扩散层，所述第一源极扩散层与所述第一栅极沟槽接触，并且所述第二源极扩散层与所述第二栅极沟槽接触；
第一接触件，耦合到所述第一栅极沟槽和第二栅极沟槽之间的所述第一导电类型的沟道层；
第二接触件，耦合到所述第一发射极沟槽和所述第一栅极沟槽之间的所述第一导电类型的沟道层；以及
第三接触件，耦合到所述第二发射极沟槽和所述第二栅极沟槽之间的所述第一导电类型的沟槽层，
其中，所述源极扩散层不设置在所述第一发射极沟槽与所述第一栅极沟槽之间以及所述第二发射极沟槽与所述第二栅极沟槽之间。
2.根据权利要求1所述的沟槽栅极绝缘栅双极晶体管，其中所述两个第一导电类型的浮置层形成为比所述第一发射极沟槽和第二发射极沟槽深。
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