TWI751622B - 半導體記憶裝置 - Google Patents
半導體記憶裝置 Download PDFInfo
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- TWI751622B TWI751622B TW109124897A TW109124897A TWI751622B TW I751622 B TWI751622 B TW I751622B TW 109124897 A TW109124897 A TW 109124897A TW 109124897 A TW109124897 A TW 109124897A TW I751622 B TWI751622 B TW I751622B
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Abstract
實施型態,提供單位記憶容量的製造成本(位元成本)很少的半導體記憶裝置。
實施型態之半導體記憶裝置,具備電路晶片,及被層積於前述電路晶片的複數記憶體晶片;前述記憶體晶片分別具有包含複數記憶體胞的記憶體胞陣列,前述電路晶片具有資料閂鎖,前述資料閂鎖收容供往分別的前述記憶體胞陣列寫入或讀出資料之用的頁面資料。
Description
本發明之實施型態係關於半導體記憶裝置。
[相關申請案]
本案享受以日本專利申請案第2020-35101號(申請日:2020年3月2日)為基礎案之優先權。本案藉由參照此基礎案而包含基礎案之所有內容。
包含記憶體胞的陣列晶片,與包含控制記憶體胞的控制電路之電路晶片被貼合之半導體記憶裝置係屬已知。
實施型態,提供單位記憶容量的製造成本(位元成本)很少的半導體記憶裝置。
實施型態之半導體記憶裝置,具備電路晶片與複數記憶體晶片。複數記憶體晶片被層積於電路晶片。複數記憶體晶片分別含有記憶體胞陣列。記憶體胞陣列,包含複數之記憶體胞。電路晶片具有資料閂鎖。資料閂鎖,收容供往分別的記憶體胞陣列寫入或讀出資料之用的頁面資料。
以下,參照圖式說明實施型態之半導體記憶裝置。在以下的說明,具有相同或類似機能的構成賦予相同的符號。接著,亦有省略這些構成的重複說明的場合。圖式僅為模式或概念性表示者,各部分的厚度與寬幅的關係,各部分間的大小比率等,不一定與現實相同。
定義x方向、y方向、z方向。x方向及y方向係與後述的記憶體晶片的表面約略平行的方向(參照圖2)。x方向係xy面內的任意一方向,y方向係與x方向正交之方向。z方向係與x方向及y方向約略正交之方向。z方向亦有稱為層積方向的場合。但這些表達方式只是為了方便,並不規定重力方向。
(第1實施形態)
圖1係顯示記憶體系統1的電路構成之方塊圖。記憶體系統1,例如為一個儲存裝置,與主機裝置2連接。主機裝置2,例如為伺服機裝置、個人電腦或者攜帶型資訊處理裝置。記憶體系統1,作為主機裝置2的外部記憶裝置發揮機能。主機裝置2,發出對記憶體系統1的存取要求(讀取要求及寫入要求)。
記憶體系統1,具有記憶體控制器10及記憶體裝置20。記憶體控制器10與記憶體裝置20,以複數個通道連接。
記憶體控制器10,包含主機界面控制器(主機I/F控制器)11、RAM(隨機存取記憶體, Random Access Memory)12、ROM(唯讀記憶體, Read Only Memory)13、CPU(中央處理單元, Central Processing Unit)14、ECC(錯誤校正碼, Error Correcting Code)電路15、及NAND控制器16。這些機能部以匯流排相互連接。例如,記憶體控制器10,以這些構成總結於1個晶片之SoC(系統單晶片, System on a Chip)構成。其中,這些機能部的一部分亦可設於記憶體控制器10的外部。
主機I/F控制器11,在根據CPU14的控制下,執行主機裝置2與記憶體系統1之間的通訊界面的控制,以及主機裝置2與RAM12之間的資料傳送的控制。
RAM12例如為DRAM(Dynamic Random Access Memory)、SRAM(Static Random Access Memory)等。RAM12作為主機裝置2與記憶體裝置20之間的資料傳送之用的緩衝器發揮機能。此外,RAM12對CPU14提供工作區。於RAM12,在記憶體系統1動作時,載入被記憶於ROM13的韌體(程式)。
CPU14為硬體處理器之一例。CPU14例如藉著執行被載入至RAM12的韌體,控制記憶體控制器10之全體。例如,CPU14控制對記憶體裝置20的資料的關於寫入、讀出、以及消除的動作。
ECC電路15,對往記憶體裝置20之寫入對象的資料進行供錯誤訂正之用的編碼。ECC電路15,在由記憶體裝置20讀出的資料包含錯誤的場合,基於寫入動作時賦予的錯誤訂正符號,對讀出的資料執行錯誤訂正。
NAND控制器16,在根據CPU14的控制下,執行RAM12與記憶體裝置20之間的資料傳送的控制。NAND控制器16,為記憶體控制器10的物理層,包含送收訊電路。NAND控制器16,把從記憶體控制器10朝向記憶體裝置20送訊的數位訊號變換為電氣訊號,使變換的電氣訊號透過傳送線路送訊至記憶體裝置20。此外,NAND控制器16,通過傳送線路由記憶體裝置20接收電氣訊號,把接受的電氣訊號變換為數位訊號。
在本實施型態,NAND控制器16具有複數個通道。各通道,被連接於複數個記憶體裝置20。但是,通道亦可為1個。此外,於1個通道,亦可僅被連接於1個記憶體裝置20。
記憶體裝置20具有複數個積體電路晶片21。圖2係相關於第1實施型態的積體電路晶片21的立體圖。積體電路晶片21具備電路晶片30與複數個記憶體晶片40。複數個記憶體晶片40係於電路晶片30上被層積在z方向。圖2係顯示記憶體晶片40為4層之例,但記憶體晶片40之數並不限定於此。而且電路晶片30與記憶體晶片40之層積順序不拘。
電路晶片30及記憶體晶片40分別具備第1墊片P1與第2墊片P2。而且電路晶片30具有第3墊片P3,第3墊片係連接到印刷電路基板上的第4墊片P4。第1墊片P1,係用以對電路晶片30或記憶體晶片40供給電源之墊片。第2墊片P2,係用以對電路晶片30或記憶體晶片40傳送訊號之墊片。第3墊片P3及第4墊片P4,係用以對電路晶片30供給電源之墊片。圖2中,第1墊片P1之間及第2墊片P2之間,係以導線w接合。導線w係有線的訊號線或電源線之一例。
圖3係顯示相關於第1實施型態的積體電路晶片21的電路構成之方塊圖。積體電路晶片21係由電路晶片30與複數個記憶體晶片40所構成。電路晶片30與分別的記憶體晶片40之間係以訊號線連接,且進行訊號的交換。
電路晶片30,例如,具有I/O訊號處理電路31,35、控制訊號處理電路32、序列電路33、資料閂鎖34、電壓產生電路36、晶片控制電路37。
I/O訊號處理電路31,係供在記憶體控制器10與積體電路晶片21之間傳送接收I/O訊號之用的緩衝電路。I/O訊號處理電路31,係由記憶體控制器10或外部電源接收訊號,且將積體電路晶片21內的資料往記憶體控制器10輸出。I/O訊號處理電路31,係連接到傳送資料、位址、及各種指示之I/O訊號線。記憶體控制器10與積體電路晶片21之間的I/O訊號線,例如,數量為8條,以1GHz程度的高速傳送訊號。
控制訊號處理電路32,係連接到控制訊號線。控制訊號線,係包含WE(寫有效,write enable)訊號線、RE(讀有效,read enable)訊號線、CLE(命令鎖存,command latch enable)訊號線、ALE(位址鎖存,address Latch Enable)訊號線、WP(防寫,write protect)訊號線等。CE訊號線係傳送顯示記憶體晶片選擇中之訊號。RY/BY訊號線係顯示記憶體裝置20是否以訊號準位進行動作,例如,以High準位顯示非動作中對應之就緒狀態(RY),以Low準位顯示動作中對應之忙碌狀態(BY)。控制訊號處理電路32,接受控制訊號,且基於接受到的控制訊號,執行I/O訊號處理電路31接受到的I/O訊號之收容目的地分配。
序列電路33,係將記憶體胞陣列41的頁面的資料,變換成傳送用資料,且進行傳送之電路。序列電路33,例如,將1頁分的資料傳送到記憶體晶片40的分別的資料暫存器45。序列電路33,係以序列將來自I/O訊號處理電路31,35的I/O訊號高速地輸出。
資料閂鎖34,係收容來自I/O訊號處理電路31,35的I/O訊號。資料閂鎖34,係演算I/O訊號,且將其分配到分別的記憶體晶片40的記憶體胞陣列41的每一頁。頁面係記憶體胞陣列41的資料之讀入單位,由複數個位元所構成。
I/O訊號處理電路35,係供在電路晶片30與分別的記憶體晶片40之間傳送接收I/O訊號之用的緩衝電路。I/O訊號處理電路35,係連接到傳送資料、位址、及各種指示之I/O訊號線。電路晶片30與分別的記憶體晶片40之間的I/O訊號線,例如,數量為10條以上200條以下,以100MHz程度的速度傳送訊號。電路晶片30與記憶體晶片40之間的訊號傳送速度,係比記憶體控制器10與積體電路晶片21之間的訊號傳送速度要慢。
電壓產生電路36,係產生讀出資料、寫入資料、消除資料上所需要的電壓。電壓產生電路36,例如,由高電壓產生電路36A與低電壓產生電路36B所構成。電壓產生電路36,係生成對記憶體胞陣列41、列解碼器42、感測放大器44施加之電壓。低電壓產生電路36B係生成基準電壓。低電壓產生電路36B也進行降壓。高電壓產生電路36A係提高基準電壓,生成高電壓。
晶片控制電路37係控制電路晶片30內的各電路。晶片控制電路37,例如,控制控制訊號處理電路32、序列電路33、資料閂鎖34及I/O訊號處理電路35。
每個記憶體晶片40,例如,具備記憶體胞陣列41、列解碼器42、行解碼器43、感測放大器44、資料暫存器45、晶片控制電路46、I/O訊號處理電路47。
記憶體胞陣列41具有複數個記憶體胞MT,記憶資料。記憶體胞陣列41,例如,係複數個記憶體胞MT為立體狀配置之所謂的三維構造之NAND記憶體。以下列舉並說明記憶體胞陣列41為NAND記憶體之例,但記憶體胞陣列41並不限於NAND記憶體。例如,MRAM (Magnetoresistive Random Access Memory)、NOR型快閃記憶體、PCM(Phase Change Material)記憶體、可變電阻式記憶體(ReRAM)亦可。
圖4係相關於第1實施型態之記憶體胞陣列之電路圖。記憶體胞陣列41具有複數個區塊BLK(BLK0,BLK1,…)。例如,記憶體胞陣列41具有數百到數千個區塊BLK。
如圖4所示,m(m為自然數)條位元線BL(BL0~BLm-1)的每條,係與各區塊BLK中的複數個(例如4個)字串STR連接。各字串STR,係包含1個第1選擇閘極電晶體ST(ST0~ST3)、複數個記憶體胞MT(MT0~MT7)、及1個第2選擇閘極電晶體DT(DT0~DT3)。第1選擇閘極電晶體ST、複數個記憶體胞MT、及第2選擇閘極電晶體DT,係依此順序串聯連接於源極線CELSRC與1個位元線BL之間。分別與不同的複數位元線BL(BL0~BLm-1)連接之複數(m個)字串STR,係構成1個字串單元SU。各區塊BLK,係包含複數(例如4個)字串單元SU(SU0~SU3)。
第1選擇閘極電晶體ST的控制閘極電極,係連接到第1選擇閘極線(源極側選擇閘極線)SGSL。第1選擇閘極線SGSL,係控制第1選擇閘極電晶體ST的控制閘極電極之控制訊號線。第1選擇閘極電晶體ST,係基於通過第1選擇閘極線SGSL而被施加的電壓,將複數個記憶體胞MT與源極線CELSRC之間選擇性地連接。第1選擇閘極線SGSL,對每一字串單元SU(SU0~SU3)獨立連接亦可。
第2選擇閘極電晶體DT的控制閘極電極,係連接到第2選擇閘極線(汲極側選擇閘極線)SGDL(SGDL0~SGDL3)。第2選擇閘極線SGDL,係控制第2選擇閘極電晶體DT的控制閘極電極之控制訊號線。第2選擇閘極電晶體DT,係基於通過第2選擇閘極線SGDL而被施加的電壓,將複數個記憶體胞MT與位元線BL之間選擇性地連接。
各記憶體胞(記憶體胞電晶體)MT,係由具有層積閘極構造的MOSFET(Metal Oxide Semiconductor Field Effect Transistor)構成。記憶體胞MT,係包含控制閘極及電荷蓄積膜,非易失性地記憶資料。記憶體胞MT,係因應被施加於控制閘極之電壓,而於電荷蓄積膜蓄積電荷。
於各區塊BLK,各記憶體胞MT的控制閘極電極,係連接到分別對應的字元線WL。例如,於記憶體胞MT0~MT7的控制閘極電極,分別連接著字元線WL0~WL7。各字元線WL,係於記憶體胞陣列41中供選擇並排成1列(1個Row)的1群記憶體胞MT之用的控制訊號線,且共通地連接於該等並排成1列的1群記憶體胞MT。字元線WL0~WL7,係連接到列解碼器42。各記憶體胞MT,被設置於字元線WL與位元線BL(BL0~BLm-1)之交叉部。藉著向連接到進行讀出或寫入的記憶體胞MT之字元線WL,施加一定的電壓,而使記憶體胞MT的讀出或寫入可以進行。
於各區塊BLK,在不同的字串STR所包含的複數個記憶體胞MT,共通地連接著對應於相同位址的字元線WL。共有字元線WL的複數個記憶體胞MT之組稱為胞單元CU。1個胞單元CU所包含的複數個記憶體胞MT,係分批寫入資料,並分批讀出資料。1個胞單元CU的記憶空間係包含1個或複數個頁面。
列解碼器42,係基於由I/O訊號處理電路47接受的位址資訊,而選擇1個區塊BLK。列解碼器42,係對複數字元線的每一條施加所要的電壓,並對記憶體胞陣列41進行資料之寫入動作及讀出動作。
行解碼器43,係基於由I/O訊號處理電路47接受的位址資訊,而選擇並活性化指定的位元線。
感測放大器44,係於讀出動作中,感測記憶體胞陣列41所包含的記憶體胞MT(參照圖3)之狀態,且基於被感測的狀態而產生讀出資料。感測放大器44,係將產生的讀出資料收納於資料暫存器45。
資料暫存器45,係暫時地保存以感測放大器44被感測的讀出資料。資料暫存器45,係具有暫時地保存讀出資料之暫時的資料閂鎖(以下稱為TDL)。TDL,並不會變換成寫入及讀出的頁面資料,而是按原樣收納被感測的讀出資料。
晶片控制電路46,係控制列解碼器42及行解碼器43之邏輯電路。晶片控制電路46,係基於由I/O訊號處理電路47接受的位址資訊,而控制列解碼器42及行解碼器43。
I/O訊號處理電路47,係供在電路晶片30與分別的記憶體晶片40之間傳送接收I/O訊號之用的緩衝電路。被收納在TDL的讀出資料是按原樣被傳送到I/O訊號處理電路47。被傳送到I/O訊號處理電路47的讀出資料,會按原樣被傳送到電路晶片30的I/O訊號處理電路35。收納在TDL的讀出資料,由電路晶片30的資料閂鎖34演算,並被收納到每一頁面資料。
相關於第1實施型態之積體電路晶片21,控制記憶體胞陣列41之周邊電路的一部分,位於與記憶體晶片40不同的電路晶片30內。周邊電路的一部分,例如,為控制訊號處理電路32、資料閂鎖34、電壓產生電路36。將資料收納於每一頁面資料之資料閂鎖34、及供產出高電壓之用的高電壓產生電路36A,需要大面積,且在晶圓之佔有率高。藉著單獨設置由複數個記憶體晶片40共有控制訊號處理電路32、資料閂鎖34、電壓產生電路36之電路晶片30,而減少構成記憶體晶片40之要素。亦即,可以減小一個積體電路晶片21的尺寸。
此外,藉著將電路晶片30與記憶體晶片40之間的I/O訊號線數量、例如增加到大約100條,可以降低於電路晶片30與記憶體晶片40間傳送訊號時之動作頻率。傳送時的頻率低(例如,100MHz程度)之場合,即使傳送用電晶體的性能低也可以處理。高性能的電晶體係晶圓成本增加的原因之一,藉著降低電晶體的性能可以減低晶圓成本。
位元成本(bit cost)係每記憶容量之製造成本。位元成本係由晶圓成本與晶片尺寸之乘積決定。從而,相關於第1實施型態的積體電路晶片21可以減低位元成本。
(第1變形例)
相關於第1變形例之積體電路晶片中,記憶體晶片40與電路晶片30之間、以及記憶體晶片40彼此之間之訊號線及電源線為通孔(via)配線V及微凸塊MB之點,與圖2所示的積體電路晶片21不同。通孔配線V係貫通配線之一例。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
圖5係顯示相關於第1變形例的積體電路晶片的記憶體晶片40與電路晶片30之層積狀態之剖面圖。於電路晶片30上層積著複數記憶體晶片40。通孔配線V,係於層積方向上貫穿記憶體晶片40及電路晶片30的內部。通孔配線V,係由被充填於絕緣層形成的開口內之導電體所構成。通孔配線V,係使用作為有線的訊號線或電源線。
微凸塊MB,係將相鄰接的記憶體晶片40間及記憶體晶片40與電路晶片30之間連起來。微凸塊MB係有線的訊號線或電源線之一例。通孔配線V及微凸塊MB,係將電路晶片30與分別的記憶體晶片40導電地連起來,作為訊號線或電源線發揮機能。
藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。此外,通孔配線V的電容比電線小,所以使用通孔配線V可降低積體電路晶片的消耗電力。
(第2變形例)
相關於第2變形例之積體電路晶片中,記憶體晶片40與電路晶片30之間之訊號線及電源線為微凸塊MB之點,與圖2所示的積體電路晶片21不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
圖6係相關於第2變形的積體電路晶片之立體圖。圖7係擴大相關於第2變形例的積體電路晶片的記憶體晶片40與電路晶片30之界面之剖面圖。圖7係連接記憶體晶片40與電路晶片30之前之圖。例如,於電路晶片30的電極E被形成之微凸塊MB,係與記憶體晶片40的電極E接合。電路晶片30係於xy面內延伸。於電路晶片30上的分別的位置,中介著微凸塊MB而連接一個記憶體晶片40。記憶體晶片40係一個、或者複數個,在複數個的場合,係例如並排於電路晶片30上。微凸塊MB係使用作為有線的訊號線或電源線。使用微凸塊MB,則電路晶片30與記憶體晶片40之間的I/O訊號線的數量可增加到100條以上10000條以下。
藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。此外,電路晶片30與記憶體晶片40之間的I/O訊號線數量增加時,可以進而降低傳送時之頻率。傳送時之頻率降低時,則消除了使用高性能的電晶體於傳送之需要,從而更加減低位元成本。此外,藉著增加電路晶片30與記憶體晶片40之間的I/O訊號線數量,可以使電路晶片30與記憶體晶片40之間之訊號傳送量增加。為了增加來自記憶體晶片40的傳送量,而有在積體電路晶片內設置多個記憶體晶片40之場合。在這樣的積體電路晶片,每一個記憶體晶片40的傳送量增加,則可以減少積體電路晶片內的記憶體晶片40數量。結果,將削減積體電路晶片的位元成本。
(第3變形例)
相關於第3變形例之積體電路晶片中,微凸塊MB的設置位置與電路晶片30的電極E的位置不對齊之點,與相關於第2變形例的積體電路晶片(圖7)不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
圖8所示之電路晶片30,係於第1面30a露出絕緣層I1與電極E。於電路晶片30的第1面30a上有配線層50。配線層50係位於電路晶片30與記憶體晶片40之間。配線層50係由絕緣層51與配線52所構成。配線52係例如銅。
配線52,係於配線層50的第1面50a及第2面50b露出。第1面50a,係與電路晶片30的第1面30a對向之面。第2面50b,係與第1面50a相反之面。配線52的一部分係於xy面內延伸。配線52於第1面50a露出之第1點54、與於第2面50b露出之第2點55,從z方向俯視時為不同位置。於第2點55上,設置著電極E1與微凸塊MB。
藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。此外,藉著改變在第1面50a與第2面50b上的配線52的露出位置,即使電極E在電路晶片30與記憶體晶片40的設置位置不同之場合,也能將二個晶片導電地連接。在此,以於電路晶片30與記憶體晶片40之間設置配線層50之場合為例加以說明,但在相鄰接的記憶體晶片40之間設置配線層50亦可。
(第4變形例)
圖9係相關於第4變形例的積體電路晶片22之立體圖。相關於第4變形例之積體電路晶片22中,記憶體晶片40與電路晶片30之間、以及記憶體晶片40彼此之間之訊號線及電源線為無線之點,與圖2所示的積體電路晶片21不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
積體電路晶片22,訊號線及電源線為無線。藉著訊號線及電源線為無線,就不需要第1墊片P1及第2墊片P2。藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。
(第5變形例)
圖10係相關於第5變形例的積體電路晶片23之立體圖。相關於第5變形例之積體電路晶片23中,記憶體晶片40與電路晶片30之間、以及記憶體晶片40彼此之間之訊號線為無線、且電源線為有線之點,與圖2所示的積體電路晶片21不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
積體電路晶片23,訊號線為無線,電源線為有線。圖10中,例示電源線為導線之場合,但電源線為通孔配線、微凸塊亦可。藉著訊號線為無線,就不需要第2墊片P2。藉著電源線為有線,大電流晶片間的傳送變得容易。藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。
(第6變形例)
圖11係相關於第6變形例的積體電路晶片24之立體圖。圖12係相關於第6變形例的積體電路晶片24之電路圖。相關於第6變形例之積體電路晶片24中,電路晶片60具有記憶體層60B之點,與圖2、圖3所示的積體電路晶片21不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
積體電路晶片24係具有電路晶片60與複數個記憶體晶片40。電路晶片60具備電路層60A與記憶體層60B。記憶體層60B,例如,於電路層60A被層積著。電路層60A與記憶體層60B,例如,藉由貼合而被導電地連接。電路層60A之構成係與前述的電路晶片30相同。記憶體層60B,係具有記憶體胞陣列41、列解碼器42、行解碼器43、感測放大器44、資料暫存器45與晶片控制電路46。
記憶體層60B的記憶體胞陣列41的資料係由感測放大器44感測,被感測的讀出資料係於資料暫存器45暫時地被保存。保存於資料暫存器的暫時的資料,按原樣被傳送到序列電路33,以資料閂鎖34演算,並被收納到每一頁面資料。記憶體層60B各部分的動作,係由晶片控制電路46控制。
藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。
(第7變形例)
圖13係相關於第7變形例的積體電路晶片25之電路圖。相關於第7變形例之積體電路晶片25中,電路晶片70具有記憶體控制器71及演算電路72之點,與圖3所示的積體電路晶片21不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。記憶體控制器71係控制器之一例。
積體電路晶片25具備電路區域70A與記憶體控制器71與演算電路72。電路區域70A係與前述的電路晶片30相同。記憶體控制器71係與前述的記憶體控制器10相同。演算電路72,係演算記憶體控制器71之處理結果、並學習。在演算電路72學習到的重要資料被傳送到記憶體控制器71,且最適化記憶體控制器71的處理。
藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。此外,藉著電路晶片70承擔記憶體控制器10的機能的一部分,每個積體電路晶片25作為儲存裝置而發揮機能。此外,藉著電路晶片70具有演算電路72,則以電路晶片單體即可進行系統動作。
(第8變形例)
圖14係相關於第8變形例的積體電路晶片26之立體圖。圖15係相關於第8變形例的積體電路晶片26之電路圖。相關於第8變形例之積體電路晶片26中,電路晶片80不具有電壓產生電路36,具有電壓產生電路36之驅動晶片81為單獨的晶片之點,與圖3所示的積體電路晶片21不同。下列說明以外的構成,係與第1實施型態之積體電路晶片21相同。
積體電路晶片26係具有電路晶片80與驅動晶片81與複數個記憶體晶片40。驅動晶片81係於電路晶片80上被層積著。驅動晶片81與電路晶片80之間的電源線及訊號線可以為無線抑或有線。複數個記憶體晶片40係在與驅動晶片81不同的位置,於電路晶片80上被層積著。電路晶片80,除了不具有電壓產生電路36之點以外,與前述的電路晶片30相同。驅動晶片81係具有電壓產生電路36。驅動晶片81係與每個記憶體晶片40導電地連接著。驅動晶片81的電壓產生電路36,係於每個記憶體晶片40,產生讀出資料、寫入資料、消除資料上所需要的電壓。
藉由這樣的構成,也與第1實施型態同樣地,可以減低積體電路晶片的位元成本。
此外,圖16係相關於第8變形例的積體電路晶片之其他例之立體圖。圖16所示之積體電路晶片中,電路晶片80與記憶體晶片40之間之電源線及訊號線為微凸塊MB。電路晶片80係於xy面內延伸。驅動晶片81係於電路晶片80上被層積著。記憶體晶片40,係在與電路晶片30上的驅動晶片81不同的位置被層積著。記憶體晶片40係一個、或者複數個,例如複數個的場合,係散布於電路晶片30上。
(第9變形例)
圖17係相關於第9變形例的積體電路晶片27之立體圖。相關於第9變形例之積體電路晶片27中,於記憶體晶片40上層積著電路晶片30之點,與圖6所示的積體電路晶片不同。
積體電路晶片之電路晶片30與記憶體晶片40之層積順序不拘。此外,圖17中,採用電路晶片30與記憶體晶片40之連接為微凸塊MB之例,並圖示電路晶片30與記憶體晶片40之位置關係是與圖6中之位置關係相反之場合。然而,電路晶片30與記憶體晶片40之位置關係並不限於該場合,亦可適用於任一種實施型態及變形例。
說明了本發明的幾個實施形態,但這些實施形態只是提示作為例子之用,並未意圖限定發明的範圍。這些實施形態,能夠以其他種種形態來實施,在不逸脫發明要旨的範圍,可以進行種種的省略、置換、變更。這些實施形態或其變形,與包含於發明的範圍或是要旨相同,係包含於申請專利範圍所記載的發明以及其均等範圍者。
21,22,23,24,25,26:積體電路晶片
30,60,70,80:電路晶片
32:控制訊號處理電路
33:資料閂鎖
36:電壓產生電路
40:記憶體晶片
41:記憶體胞陣列
50:配線層
50a:第1面
50b:第2面
51:絕緣層
52:配線
54:第1點
55:第2點
60A:電路層
60B:記憶體層
70A:電路區域
71:NAND控制器
72:演算電路
81:驅動晶片
[圖1]係顯示相關於第1實施型態之半導體記憶裝置的電路構成之方塊圖。
[圖2]係相關於第1實施型態之積體電路晶片之立體圖。
[圖3]係顯示相關於第1實施型態之積體電路晶片的電路構成之方塊圖。
[圖4]係相關於第1實施形態之積體電路晶片之記憶體胞陣列之電路圖。
[圖5]係顯示相關於第1變形例之積體電路晶片之記憶體晶片與電路晶片的層積狀態之剖面圖。
[圖6]係相關於第2變形例之積體電路晶片之立體圖。
[圖7]係擴大相關於第2變形例之積體電路晶片之記憶體晶片與電路晶片的界面之剖面圖。
[圖8]係擴大相關於第3變形例之積體電路晶片之記憶體晶片與電路晶片的界面之剖面圖。
[圖9]係相關於第4變形例之積體電路晶片之立體圖。
[圖10]係相關於第5變形例之積體電路晶片之立體圖。
[圖11]係相關於第6變形例之積體電路晶片之立體圖。
[圖12]係顯示相關於第6變形例之積體電路晶片的電路構成之方塊圖。
[圖13]係顯示相關於第7變形例之積體電路晶片的電路構成之方塊圖。
[圖14]係相關於第8變形例之積體電路晶片之立體圖。
[圖15]係顯示相關於第8變形例之積體電路晶片的電路構成之方塊圖。
[圖16]係相關於第8變形例之積體電路晶片之其他例的立體圖。
[圖17]係相關於第9變形例之積體電路晶片之其他例的立體圖。
21:積體電路晶片
30:電路晶片
31,35:I/O訊號處理電路
32:控制訊號處理電路
33:資料閂鎖
34:資料閂鎖
36:電壓產生電路
36A:高電壓產生電路
36B:低電壓產生電路
37:晶片控制電路
40:記憶體晶片
41:記憶體胞陣列
42:列解碼器
43:行解碼器
44:感測放大器
45:資料暫存器
46:晶片控制電路
47:I/O訊號處理電路
Claims (13)
- 一種半導體記憶裝置,具備電路晶片,及被層積於前述電路晶片的複數記憶體晶片;前述複數記憶體晶片分別具有包含複數記憶體胞的記憶體胞陣列、資料暫存器及複數之第一I/O訊號處理電路,前述電路晶片具有收納資料於分別的頁面資料之資料閂鎖及第二I/O訊號處理電路,於讀出動作,由前述記憶體胞陣列讀出的讀出資料,經前述資料暫存器、前述第一I/O訊號處理電路、第二I/O訊號處理電路,以前述資料閂鎖演算而收納到每一頁面資料。
- 如請求項1之半導體記憶裝置,其中前述電路晶片,具備產生施加於分別的前述記憶體胞陣列的電壓之電壓產生電路。
- 如請求項1之半導體記憶裝置,其中進而具備具有產生施加於分別的前述記憶體胞陣列的電壓之電壓產生電路的驅動晶片。
- 如請求項1之半導體記憶裝置,其中前述電路晶片,具備前述記憶體胞陣列的控制訊號處理電路。
- 如請求項4之半導體記憶裝置,其中具有在前述電路晶片與分別的前述記憶體晶片之間進 行資料的交換之訊號線,與前述電路晶片及分別的記憶體晶片之電源線,前述訊號線為無線。
- 如請求項5之半導體記憶裝置,其中前述電源線為有線。
- 如請求項4之半導體記憶裝置,其中具有在前述電路晶片與分別的前述記憶體晶片之間進行資料的交換之訊號線,與前述電路晶片及分別的記憶體晶片之電源線,前述訊號線為有線。
- 如請求項1~7之任一之半導體記憶裝置,其中前述電路晶片與前述記憶體晶片之間,或者2個前述記憶體晶片之間,具有配線層,前述配線層,具有絕緣層與被形成於前述絕緣層內的配線,於前述配線層之第1面前述配線露出的第1點,與在前述配線層的第2面前述配線露出的第2點的位置不同。
- 如請求項1~7之任一之半導體記憶裝置,其中前述電路晶片,具備包含前述資料閂鎖的電路層,以及具有包含複數記憶體胞的記憶體胞陣列之記憶體層;前述電路層與前述記憶體層被層積。
- 如請求項1~7之任一之半導體記憶裝 置,其中前述電路晶片,進而具備包含前述資料閂鎖的電路區域,及控制前述電路區域的控制器。
- 如請求項10之半導體記憶裝置,其中前述電路晶片,進而具備演算前述控制器的動作結果之演算電路。
- 如請求項1之半導體記憶裝置,其中具有:在前述電路晶片與分別的前述記憶體晶片之間進行資料的交換之訊號線,與前述電路晶片及分別的記憶體晶片之電源線;前述訊號線及前述電源線,具有:於層積方向貫通前述電路晶片與前述記憶體晶片之中至少一方的貫通配線,以及與前述貫通配線導電連接,位在前述電路晶片與前述記憶體晶片之中至少一方表面的微凸塊。
- 如請求項1之半導體記憶裝置,其中具有:在前述電路晶片與分別的前述記憶體晶片之間進行資料的交換之訊號線,與前述電路晶片及分別的記憶體晶片之電源線;前述訊號線及前述電源線,為位在前述電路晶片與前述記憶體晶片之中至少一方表面的微凸塊。
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US20210272946A1 (en) | 2021-09-02 |
CN113345869A (zh) | 2021-09-03 |
CN113345869B (zh) | 2024-01-30 |
US20220320065A1 (en) | 2022-10-06 |
US11417642B2 (en) | 2022-08-16 |
JP2021140837A (ja) | 2021-09-16 |
TW202209316A (zh) | 2022-03-01 |
TW202135056A (zh) | 2021-09-16 |
US11756946B2 (en) | 2023-09-12 |
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