CN113345869A - 半导体存储装置 - Google Patents

半导体存储装置 Download PDF

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Publication number
CN113345869A
CN113345869A CN202010800953.1A CN202010800953A CN113345869A CN 113345869 A CN113345869 A CN 113345869A CN 202010800953 A CN202010800953 A CN 202010800953A CN 113345869 A CN113345869 A CN 113345869A
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chip
circuit
memory
circuit chip
memory device
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CN113345869B (zh
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佐贯朋也
藤泽俊雄
前岛洋
前田高志
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Kioxia Corp
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Kioxia Corp
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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Abstract

实施方式提供一种单位存储容量的制造成本即位成本少的半导体存储装置。实施方式的半导体存储装置具备：电路芯片；以及多个存储芯片，层叠于上述电路芯片；上述多个存储芯片分别具有包括多个存储单元的存储单元阵列；上述电路芯片具有数据锁存器；上述数据锁存器保存用来向各个上述存储单元阵列写入或读取数据的页数据。

Description

半导体存储装置
本申请基于日本专利申请第2020－35101号(申请日：2020年3月2日)主张优先权，这里通过引用而包含其全部内容。
技术领域
本发明涉及半导体存储装置。
背景技术
已知存在将包含存储单元的阵列芯片与包含控制存储单元的控制电路的电路芯片贴合成的半导体存储装置。
发明内容
本发明的目的是提供一种单位存储容量的制造成本(位成本)小的半导体存储装置。
技术方案的半导体存储装置具备电路芯片和多个存储芯片。多个存储芯片层叠于电路芯片。多个存储芯片分别具有存储单元阵列。存储单元阵列包括多个存储单元。电路芯片具有数据锁存器。数据锁存器保存用来向各个存储单元阵列写入或读取数据的页数据。
附图说明
图1是表示有关第1实施方式的半导体存储装置的电路结构的框图。
图2是有关第1实施方式的集成芯片的斜视图。
图3是表示有关第1实施方式的集成芯片的电路结构的框图。
图4是有关第1实施方式的集成芯片的存储单元阵列的电路图。
图5是表示有关第1变形例的集成芯片的存储芯片和电路芯片的层叠状态的剖面图。
图6是有关第2变形例的集成芯片的斜视图。
图7是将有关第2变形例的集成芯片的存储芯片与电路芯片的分界面放大的剖面图。
图8是将有关第3变形例的集成芯片的存储芯片与电路芯片的分界面放大的剖面图。
图9是有关第4变形例的集成芯片的斜视图。
图10是有关第5变形例的集成芯片的斜视图。
图11是有关第6变形例的集成芯片的斜视图。
图12是表示有关第6变形例的集成芯片的电路结构的框图。
图13是表示有关第7变形例的集成芯片的电路结构的框图。
图14是有关第8变形例的集成芯片的斜视图。
图15是表示有关第8变形例的集成芯片的电路结构的框图。
图16是有关第8变形例的集成芯片的另一例的斜视图。
图17是有关第9变形例的集成芯片的另一例的斜视图。
标号说明
21、22、23、24、25、26…集成芯片；30、60、70、80…电路芯片；32…控制信号处理电路；34…数据锁存器；36…电压产生电路；40…存储芯片；41…存储单元阵列；50…配线层；50a…第1面；50b…第2面；51…绝缘层；52…配线；54…第1点；55…第2点；60A…电路层；60B…存储层；70A…电路区域；71…NAND控制器；72…运算电路；81…驱动芯片。
具体实施方式
以下，参照附图说明实施方式的半导体存储装置。在以下的说明中，对具有相同或类似的功能的结构赋予相同的标号。并且，有时将这些结构的重复的说明省略。附图是示意性或概念性的图，各部分的厚度与宽度的关系、部分间的大小的比例等并不一定与现实相同。
对x方向、y方向、z方向进行定义。x方向及y方向是与后述的存储芯片的表面大致平行的方向(参照图2)。x方向是xy面内的任意的一个方向，y方向是与x方向正交的方向。z方向是与x方向及y方向大致正交的方向。z方向有时被称作层叠方向。但是，这些表现是为了方便，并不规定重力方向。
(第1实施方式)
图1是表示存储系统1的电路结构的框图。存储系统1例如是一个储存设备，与主机装置2连接。主机装置2例如是服务器装置、个人计算机或移动型的信息处理装置。存储系统1作为主机装置2的外部存储装置发挥功能。主机装置2发出对于存储系统1的访问请求(读请求及写请求)。
存储系统1具有存储控制器10和存储装置20。存储控制器10和存储装置20通过多个通道连接。
存储控制器10包括主机接口控制器(主机I/F控制器)11、RAM(Random AccessMemory，随机存取存储器)12、ROM(Read Only Memory，只读存储器)13、CPU(CentralProcessing Unit，中央处理器)14、ECC(Error Correcting Code，纠错码)电路15及NAND控制器16。这些功能部通过总线相互连接。例如，存储控制器10由将这些结构汇总于1个芯片的SoC(System on a Chip，片上系统)构成。但是，也可以将这些功能部的一部分设置在存储控制器10的外部。
主机I/F控制器11在通过CPU 14进行的控制下，执行主机装置2与存储系统1之间的通信接口的控制以及主机装置2与RAM 12之间的数据转送的控制。
RAM 12例如是DRAM(Dynamic Random Access Memory，动态随机存取存储器)、SRAM(Static Random Access Memory，静态随机存取存储器)等。RAM 12作为用于主机装置2与存储装置20之间的数据转送的缓存发挥功能。此外，RAM 12向CPU 14提供工作区。在存储系统1动作时，将存储于ROM 13中的固件(程序)装载到RAM 12中。
CPU 14是硬件处理器的一例。CPU 14例如通过执行装载到RAM 12中的固件，对存储控制器10的整体进行控制。例如，CPU 14控制与对于存储装置20的数据的写入、读取及删除有关的动作。
ECC电路15对作为向存储装置20的写入对象的数据进行用于错误校正的编码。ECC电路15在从存储装置20读取的数据中包含错误的情况下，基于在写入动作时赋予的错误校正码，对读取出的数据执行错误校正。
NAND控制器16在由CPU 14进行的控制下，执行RAM 12与存储装置20之间的数据转送的控制。NAND控制器16是存储控制器10的物理层，包括收发电路。NAND控制器16将从存储控制器10朝向存储装置20发送的数字信号转换为电信号，将转换出的电信号经由传送线路向存储装置20发送。此外，NAND控制器16经由传送线路从存储装置20接收电信号，将接收到的电信号转换为数字信号。
在本实施方式中，NAND控制器16具有多个通道。各通道与多个存储装置20连接。但是，通道也可以是1个。此外，也可以在1个通道仅连接1个存储装置20。
存储装置20具有多个集成芯片21。图2是有关第1实施方式的集成芯片21的斜视图。集成芯片21具备电路芯片30和多个存储芯片40。多个存储芯片40在z方向上层叠在电路芯片30上。在图2中，表示了存储芯片40是4层的例子，但存储芯片40的数量并不限定于此。此外，电路芯片30和存储芯片40的层叠顺序没有限制。
电路芯片30及存储芯片40分别具备第1焊盘P1和第2焊盘P2。此外，电路芯片30具有第3焊盘P3，第3焊盘与印刷基板上的第4焊盘P4连接。第1焊盘P1是用来向电路芯片30或存储芯片40供给电源的焊盘。第2焊盘P2是用来向电路芯片30或存储芯片40传送信号的焊盘。第3焊盘P3及第4焊盘P4是用来向电路芯片30供给电源的焊盘。在图2中，第1焊盘P1之间及第2焊盘P2之间通过导线w接合。导线w是有线的信号线或电源线的一例。
图3是表示有关第1实施方式的集成芯片21的电路结构的框图。集成芯片21由电路芯片30和多个存储芯片40构成。电路芯片30与各个存储芯片40之间通过信号线连接，进行信号的交换。
电路芯片30例如具有I/O信号处理电路31、35、控制信号处理电路32、串行电路33、数据锁存器34、电压产生电路36、芯片控制电路37。
I/O信号处理电路31是用来在存储控制器10与集成芯片21之间收发I/O信号的缓存电路。I/O信号处理电路31从存储控制器10或外部电源接收信号，将集成芯片21内的数据向存储控制器10输出。I/O信号处理电路31与传送数据、地址及各种指示的I/O信号线连接。存储控制器10与集成芯片21之间的I/O信号线例如是8条，以1GHz左右的高速传送信号。
控制信号处理电路32与控制信号线连接。控制信号线包括WE(写使能)信号线、RE(读使能)信号线、CLE(命令锁存器使能)信号线、ALE(地址锁存器使能)信号线、WP(写保护)信号线等。CE信号线传送表示存储芯片处于选择中的信号。RY/BY信号线用信号的电平表示存储装置20是否处于动作中，例如用High电平表示与非动作中对应的就绪状态(RY)，用Low水平表示与动作中对应的繁忙状态(BY)。控制信号处理电路32受理控制信号，基于受理的控制信号，执行I/O信号处理电路31受理的I/O信号的保存目的地的分配。
串行电路33是将存储单元阵列41的页的数据转换为转送用的数据并转送的电路。串行电路33例如将1页的量的数据向存储芯片40的各自的数据寄存器45传送。串行电路33将来自I/O信号处理电路31、35的I/O信号串行地高速输出。
数据锁存器34将来自I/O信号处理电路31、35的I/O信号保存。数据锁存器34对I/O信号进行运算，按照各个存储芯片40的存储单元阵列41的每个页分配。页是存储单元阵列41的数据的读入的单位，由多个位构成。
I/O信号处理电路35是用来在电路芯片30与各个存储芯片40之间收发I/O信号的缓存电路。I/O信号处理电路35与传送数据、地址及各种指示的I/O信号线连接。电路芯片30与各个存储芯片40之间的I/O信号线例如是10根以上200根以下，以100MHz左右的速度传送信号。电路芯片30与存储芯片40之间的信号的传送速度比存储控制器10与集成芯片21之间的信号的传送速度慢。
电压产生电路36产生数据的读取、数据的写入、数据的删除所需要的电压。电压产生电路36例如由高电压产生电路36A和低电压产生电路36B构成。电压产生电路36生成向存储单元阵列41、行解码器42、感测放大器44施加的电压。低电压产生电路36B生成基准电压。低电压产生电路36B也进行降压。高电压产生电路36A将基准电压升压，生成高电压。
芯片控制电路37对电路芯片30内的各电路进行控制。芯片控制电路37例如对控制信号处理电路32、串行电路33、数据锁存器34及I/O信号处理电路35进行控制。
各个存储芯片40例如具备存储单元阵列41、行解码器42、列解码器43、感测放大器44、数据寄存器45、芯片控制电路46、I/O信号处理电路47。
存储单元阵列41具有多个存储单元MT，对数据进行存储。存储单元阵列41例如是多个存储单元MT配置为立体状所得的所谓的三维构造的NAND存储器。以下，例举存储单元阵列41是NAND存储器的例子进行说明，但存储单元阵列41并不限于NAND存储器。例如，也可以是MRAM(Magnetoresistive Random Access Memory，磁阻式随机存取存储器)、NOR型闪存存储器、PCM(Phase Change Material，相变材料)存储器、电阻变化型存储器(ReRAM)。
图4是有关第1实施方式的存储单元阵列的电路图。存储单元阵列41具有多个块BLK(BLK0，BLK1，…)。例如，存储单元阵列41具有几百至几千个块BLK。
如图4所示，m(m是自然数)根位线BL(BL0～BLm－1)分别在各块BLK中与多个(例如4个)串(string)STR连接。各串STR包括1个第1选择栅极晶体管ST(ST0～ST3)、多个存储单元MT(MT0～MT7)及1个第2选择栅极晶体管DT(DT0～DT3)。第1选择栅极晶体管ST、多个存储单元MT及第2选择栅极晶体管DT以该顺序串联地连接在源极线CELSRC与1个位线BL之间。与不同的多个位线BL(BL0～BLm－1)分别连接的多个(m个)串STR构成1个串组件SU。各块BLK包括多个(例如4个)串组件SU(SU0～SU3)。
第1选择栅极晶体管ST的控制栅极电极与第1选择栅极线(源极侧选择栅极线)SGSL连接。第1选择栅极线SGSL是对第1选择栅极晶体管ST的控制栅极电极进行控制的控制信号线。第1选择栅极晶体管ST基于经由第1选择栅极线SGSL施加的电压，将多个存储单元MT与源极线CELSRC之间有选择地连接。第1选择栅极线SGSL也可以按照每个串组件SU(SU0～SU3)独立地连接。
第2选择栅极晶体管DT的控制栅极电极与第2选择栅极线(漏极侧选择栅极线)SGDL(SGDL0～SGDL3)连接。第2选择栅极线SGDL是对第2选择栅极晶体管DT的控制栅极电极进行控制的控制信号线。第2选择栅极晶体管DT基于经由第2选择栅极线SGDL施加的电压，将多个存储单元MT与位线BL之间有选择地连接。
各存储单元(存储单元晶体管)MT由具有层叠栅极构造的MOSFET(Metal OxideSemiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)构成。存储单元MT包括控制栅极及电荷积蓄膜，非易失性地存储数据。存储单元MT根据施加在控制栅极的电压而向电荷积蓄膜积蓄电荷。
在各块BLK，各存储单元MT的控制栅极电极分别与对应的字线WL连接。例如，在存储单元MT0～MT7的控制栅极电极分别连接着字线WL0～WL7。各字线WL是用来在存储单元阵列41中选择排列为1列(1个Row)的1群存储单元MT的控制信号线，与这些排列为1列的1群存储单元MT共同地连接。字线WL0～WL7与行解码器42连接。各存储单元MT设在字线WL与位线BL(BL0～BLm－1)的交叉部。通过对与进行读取或写入的存储单元MT连接的字线WL施加某一电压，从而能够进行存储单元MT的读取或写入。
在各块BLK，不同的串STR包含的多个存储单元MT共同地连接着与相同的地址对应的字线WL。共用字线WL的多个存储单元MT的组被称作单元组件CU。1个单元组件CU所包含的多个存储单元MT一起写入数据，此外一起读取数据。1个单元组件CU的存储空间包括1个或多个页。
行解码器42基于从I/O信号处理电路47接收到的地址信息，选择1个块BLK。行解码器42对多个字线分别施加希望的电压，进行对于存储单元阵列41的数据的写入动作及读取动作。
列解码器43基于从I/O信号处理电路47接收到的地址信息，选择规定的位线并激活。
感测放大器44在读取动作中，对存储单元阵列41所包含的存储单元MT(参照图3)的状态进行感测，基于感测到的状态生成读取数据。感测放大器44将生成的读取数据向数据寄存器45保存。
数据寄存器45将由感测放大器44感测到的读取数据暂时保存。数据寄存器45具有将读取数据暂时保存的临时性的数据锁存器(以下，称作TDL)。TDL将感测到的读取数据原样保存而不将其转换为写入及读取的页数据。
芯片控制电路46是对行解码器42及列解码器43进行控制的逻辑电路。芯片控制电路46基于从I/O信号处理电路47接收到的地址信息，对行解码器42及列解码器43进行控制。
I/O信号处理电路47是用来在电路芯片30与各个存储芯片40之间收发I/O信号的缓存电路。I/O信号处理电路47原样传送保存在TDL中的读取数据。传送给I/O信号处理电路47的读取数据向电路芯片30的I/O信号处理电路35原样传送。保存在TDL中的读取数据由电路芯片30的数据锁存器34进行运算，按照页数据进行保存。
有关第1实施方式的集成芯片21的对存储单元阵列41进行控制的周边电路的一部分处于与存储芯片40不同的电路芯片30内。周边电路的一部分例如是指控制信号处理电路32、数据锁存器34、电压产生电路36。将数据按照页数据进行保存的数据锁存器34及用来产生高电压的高电压产生电路36A需要较大的面积，晶片中的占有率较高。通过另外设置对多个存储芯片40将控制信号处理电路32、数据锁存器34、电压产生电路36共用化的电路芯片30，从而构成存储芯片40的要素变少。即，能够使一个集成芯片21的尺寸变小。
此外，通过将电路芯片30与存储芯片40之间的I/O信号线例如增加到大致100根，能够降低在电路芯片30与存储芯片40间传送信号时的动作频率。在传送时的频率低(例如100MHz左右)的情况下，即使传送用的晶体管的性能低也能够进行处理。高性能的晶体管是晶片成本的增大的原因之一，通过降低晶体管的性能，能够降低晶片成本。
位成本是单位存储容量的制造成本。位成本由晶片成本与芯片尺寸的乘积决定。因而，有关第1实施方式的集成芯片21能够降低位成本。
(第1变形例)
对于有关第1变形例的集成芯片，存储芯片40与电路芯片30之间以及存储芯片40彼此之间的信号线及电源线是导通孔配线V及微凸块MB这一点与图2所示的集成芯片21不同。导通孔配线V是贯通配线的一例。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。
图5是表示有关第1变形例的集成芯片的存储芯片40与电路芯片30的层叠状态的剖面图。在电路芯片30之上，层叠着多个存储芯片40。导通孔配线V将存储芯片40及电路芯片30的内部在层叠方向上贯穿。导通孔配线V由在形成于绝缘层的开口内填充的导电体构成。导通孔配线V作为有线的信号线或电源线使用。
微凸块MB将相邻的存储芯片40间及存储芯片40与电路芯片30之间相连。微凸块MB是有线的信号线或电源线的一例。导通孔配线V及微凸块MB将电路芯片30与各个存储芯片40电气地相连，作为信号线或电源线发挥功能。
通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。此外，由于导通孔配线V与导线相比电容较小，所以如果使用导通孔配线V，则集成芯片的耗电下降。
(第2变形例)
对于有关第2变形例的集成芯片，在存储芯片40与电路芯片30之间的信号线及电源线是微凸块MB这一点与图2所示的集成芯片21不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。
图6是有关第2变形例的集成芯片的斜视图。图7是将有关第2变形例的集成芯片的存储芯片40与电路芯片30的分界面放大的剖面图。图7是将存储芯片40与电路芯片30连接之前的图。例如，形成在电路芯片30的电极E的微凸块MB与存储芯片40的电极E接合。电路芯片30在xy面内展开。在电路芯片30上的各个位置，经由微凸块MB连接着一个存储芯片40。存储芯片40是一个或多个，在多个的情况下，例如在电路芯片30上排列。微凸块MB作为有线的信号线或电源线使用。如果使用微凸块MB，则使电路芯片30与存储芯片40之间的I/O信号线增加到100根以上10000根以下。
通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。此外，如果将电路芯片30与存储芯片40之间的I/O信号线增加，则能够进一步降低传送时的频率。如果传送时的频率下降，则不需要为了传送用而使用高性能的晶体管，带来位成本的进一步的降低。此外，通过增加电路芯片30与存储芯片40之间的I/O信号线，能够增加电路芯片30与存储芯片40之间的信号的传送量。为了增加来自存储芯片40的传送量，有时在集成芯片内设置大量的存储芯片40。对于这样的集成芯片，如果每一个存储芯片40的传送量增加，则能够减少集成芯片内的存储芯片40的数量。结果，削减了集成芯片的位成本。
(第3变形例)
有关第3变形例的集成芯片在微凸块MB的设置位置与电路芯片30的电极E的位置错开这一点上与有关第2变形例的集成芯片(图7)不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。
图8所示的电路芯片30在第1面30a露出绝缘层I1和电极E。在电路芯片30的第1面30a上存在配线层50。配线层50处于电路芯片30与存储芯片40之间。配线层50由绝缘层51和配线52构成。配线52例如是Cu。
配线52在配线层50的第1面50a及第2面50b露出。第1面50a是与电路芯片30的第1面30a对置的面。第2面50b是第1面50a反对侧的面。配线52的一部分在xy面内展开。配线52在第1面50a中露出的第1点54和在第2面50b中露出的第2点55从z方向俯视时位置不同。在第2点55上，设置有电极E1和微凸块MB。
通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。此外，通过在第1面50a和第2面50b中改变配线52的露出位置，即使是在电极E在电路芯片30和存储芯片40间的设置位置不同的情况下，也能够将两个芯片电气地连接。这里，以在电路芯片30与存储芯片40之间设置配线层50的情况为例进行了说明，但也可以在相邻的存储芯片40之间设置配线层50。
(第4变形例)
图9是有关第4变形例的集成芯片22的斜视图。对于有关第4变形例的集成芯片22，在存储芯片40与电路芯片30之间及存储芯片40彼此之间的信号线及电源线是无线的这一点上与图2所示的集成芯片21不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。
集成芯片22的信号线及电源线是无线的。通过将信号线及电源线设为无线，不再需要第1焊盘P1及第2焊盘P2。通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。
(第5变形例)
图10是有关第5变形例的集成芯片23的斜视图。对于有关第5变形例的集成芯片23，在存储芯片40与电路芯片30之间及存储芯片40彼此之间的信号线是无线的而电源线是有线的这一点上与图2所示的集成芯片21不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是同样的。
集成芯片23的信号线是无线的，电源线是有线的。在图10中，例示了电源线是导线的情况，但电源线也可以是导通孔配线、微凸块。通过将信号线设为无线，不再需要第2焊盘P2。通过将电源线设为有线，大电流的芯片间的电力输送变得容易。通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。
(第6变形例)
图11是有关第6变形例的集成芯片24的斜视图。图12是有关第6变形例的集成芯片24的电路图。有关第6变形例的集成芯片24在电路芯片60具有存储层60B这一点上与图2、图3所示的集成芯片21不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。
集成芯片24具有电路芯片60和多个存储芯片40。电路芯片60具备电路层60A和存储层60B。存储层60B例如层叠在电路层60A。电路层60A和存储层60B例如通过贴合而电气地连接。电路层60A是与上述的电路芯片30同样的结构。存储层60B具有存储单元阵列41、行解码器42、列解码器43、感测放大器44、数据寄存器45和芯片控制电路46。
存储层60B的存储单元阵列41的数据通过感测放大器44进行感测，感测到的读取数据暂时地保存到数据寄存器45。将保存在数据寄存器中的暂时性的数据原样向串行电路33传送，在数据锁存器34中进行运算，按照页数据保存。存储层60B的各部分的动作由芯片控制电路46控制。
通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。
(第7变形例)
图13是有关第7变形例的集成芯片25的电路图。对于有关第7变形例的集成芯片25，在电路芯片70具有存储控制器71及运算电路72这一点上与图3所示的集成芯片21不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。存储控制器71是控制器的一例。
集成芯片25具备电路区域70A、存储控制器71和运算电路72。电路区域70A与上述的电路芯片30是相同的。存储控制器71与上述的存储控制器10是相同的。运算电路72对存储控制器71的处理结果进行运算、学习。将由运算电路72学习出的权重的数据传送给存储控制器71，优化存储控制器71的处理。
通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。此外，通过电路芯片70承担存储控制器10的功能的一部分，各集成芯片25作为储存设备发挥功能。此外，由于电路芯片70具有运算电路72，从而能够以电路芯片单体进行系统动作。
(第8变形例)
图14是有关第8变形例的集成芯片26的斜视图。图15是有关第8变形例的集成芯片26的电路图。对于有关第8变形例的集成芯片26，在电路芯片80不具有电压产生电路36，具有电压产生电路36的驱动芯片81为其他芯片这一点上与图3所示的集成芯片21不同。以下说明的结构以外的结构与第1实施方式的集成芯片21是相同的。
集成芯片26具有电路芯片80、驱动芯片81和多个存储芯片40。驱动芯片81层叠在电路芯片80上。驱动芯片81与电路芯片80之间的电源线及信号线既可以是无线的也可以是有线的。多个存储芯片40在与驱动芯片81不同的位置层叠在电路芯片80上。电路芯片80除了不具有电压产生电路36这一点以外，与上述的电路芯片30是相同的。驱动芯片81具有电压产生电路36。驱动芯片81与各个存储芯片40电连接。驱动芯片81的电压产生电路36产生在各个存储芯片40中数据的读取、数据的写入、数据的删除所需要的电压。
通过这样的结构，也与第1实施方式同样地，能够降低集成芯片的位成本。
此外，图16是有关第8变形例的集成芯片的另一例的斜视图。对于图16所示的集成芯片，电路芯片80与存储芯片40之间的电源线及信号线是微凸块MB。电路芯片80在xy面内展开。驱动芯片81层叠在电路芯片80上。存储芯片40层叠在电路芯片30上的与驱动芯片81不同的位置。存储芯片40是一个或多个，在多个的情况下例如铺满在电路芯片30上。
(第9变形例)
图17是有关第9变形例的集成芯片27的斜视图。对于有关第9变形例的集成芯片27，电路芯片30层叠在存储芯片40上这一点与图6所示的集成芯片不同。
集成芯片的电路芯片30与存储芯片40的层叠顺序没有限制。此外，在图17中，使用电路芯片30与存储芯片40的连接手段为微凸块MB的例子，图示了电路芯片30与存储芯片40的位置关系与图6反转的情况。但是，电路芯片30与存储芯片40的位置关系并不限于该情况，能够应用于任一个实施方式及变形例中。
说明了本发明的几个实施方式，但这些实施方式是作为例子提示的，不是要限定发明的范围。这些实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围中能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围或主旨中，同样包含在权利要求书所记载的发明和其等价的范围中。

Claims (13)

1.一种半导体存储装置，其具备：
电路芯片；以及
多个存储芯片，层叠于所述电路芯片；
所述多个存储芯片分别具有包括多个存储单元的存储单元阵列；
所述电路芯片具有数据锁存器；
所述数据锁存器保存用来向各个所述存储单元阵列写入或读取数据的页数据。
2.如权利要求1所述的半导体存储装置，其中，
所述电路芯片具备生成向各个所述存储单元阵列施加的电压的电压产生电路。
3.如权利要求1所述的半导体存储装置，其中，
所述半导体存储装置还具备驱动芯片，所述驱动芯片具备生成向各个所述存储单元阵列施加的电压的电压产生电路。
4.如权利要求1所述的半导体存储装置，其中，
所述电路芯片具备所述存储单元阵列的控制信号处理电路。
5.如权利要求4所述的半导体存储装置，其中，
所述半导体存储装置具有在所述电路芯片与各个所述存储芯片之间进行数据的交换的信号线和所述电路芯片及各个存储芯片的电源线；
所述信号线是无线的。
6.如权利要求5所述的半导体存储装置，其中，
所述电源线是有线的。
7.如权利要求4所述的半导体存储装置，其中，
所述半导体存储装置具有在所述电路芯片与各个所述存储芯片之间进行数据的交换的信号线和所述电路芯片及各个存储芯片的电源线；
所述信号线是有线的。
8.如权利要求1～7中任一项所述的半导体存储装置，其中，
在所述电路芯片与所述存储芯片之间或两个所述存储芯片之间具有配线层；
所述配线层具有绝缘层和形成在所述绝缘层内的配线；
在所述配线层的第1面中露出所述配线的第1点和在所述配线层的第2面中露出所述配线的第2点的位置不同。
9.如权利要求1～7中任一项所述的半导体存储装置，其中，
所述电路芯片具备电路层和存储层，所述电路层包括所述数据锁存器，所述存储层具有包括多个存储单元的存储单元阵列；
所述电路层和所述存储层层叠。
10.如权利要求1～7中任一项所述的半导体存储装置，其中，
所述电路芯片还具备包括所述数据锁存器的电路区域和对所述电路区域进行控制的控制器。
11.如权利要求10所述的半导体存储装置，其中，
所述电路芯片还具备对所述控制器的动作结果进行运算的运算电路。
12.如权利要求1所述的半导体存储装置，其中，
所述半导体存储装置具有在所述电路芯片与各个所述存储芯片之间进行数据的交换的信号线和所述电路芯片及各个存储芯片的电源线；
所述信号线及所述电源线具有贯通配线和微凸块，所述贯通配线将所述电路芯片和所述存储芯片中的至少一个在层叠方向上贯通，所述微凸块与所述贯通配线电连接并处于所述电路芯片和所述存储芯片中的至少一个的表面。
13.如权利要求1所述的半导体存储装置，其中，
所述半导体存储装置具有在所述电路芯片与各个所述存储芯片之间进行数据的交换的信号线和所述电路芯片及各个存储芯片的电源线；
所述信号线及所述电源线是处于所述电路芯片和所述存储芯片中的至少一个的表面的微凸块。
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