TWI731849B - 使用無核心訊號分佈結構的半導體封裝 - Google Patents

使用無核心訊號分佈結構的半導體封裝 Download PDF

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TWI731849B
TWI731849B TW105104253A TW105104253A TWI731849B TW I731849 B TWI731849 B TW I731849B TW 105104253 A TW105104253 A TW 105104253A TW 105104253 A TW105104253 A TW 105104253A TW I731849 B TWI731849 B TW I731849B
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signal distribution
distribution structure
electronic device
semiconductor package
conductor
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TW105104253A
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TW201640643A (zh
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金杜渾
朴錦書
翰森其
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美商艾馬克科技公司
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Abstract

本發明揭示一種使用無核心訊號分佈結構(Coreless Signal Distribution Structure，CSDS)的半導體封裝，並且可以包含一種CSDS，其包括至少一介電層、至少一導體層、一第一表面、以及一和該第一表面反向的第二表面。該半導體封裝還可以包含：一第一半導體晶粒，其在一第一晶粒表面上有一第一接合觸墊，其中，該第一半導體晶粒透過該第一接合觸墊被接合至該CSDS的第一表面；以及一第二半導體晶粒，其在一第二晶粒表面上有一第二接合觸墊，其中，該第二半導體晶粒透過該第二接合觸墊被接合至該CSDS的第二表面。該半導體封裝可以進一步包含一金屬柱，其被電氣耦合至該CSDS的第一表面；以及一第一囊封劑材料，用以囊封側表面以及和該第一半導體晶粒的第一晶粒表面反向的表面、該金屬柱、以及該CSDS的第一表面的一部分。

Description

使用無核心訊號分佈結構的半導體封裝
本揭示內容的特定範例實施例和半導體晶片封裝有關。更明確的說，本揭示內容的特定範例實施例和使用無核心訊號分佈結構的半導體封裝有關。
相關申請案之交叉參考
本申請案參考2015年2月9日提申的韓國專利申請案第10-2015-0019458號並且主張該案的優先權與權利，本文以引用的方式將其內容完整併入。
目前的半導體封裝以及形成半導體封裝的方法(舉例來說，運用具有直通矽通孔之中介板技術的多維封裝與方法)已不適用，舉例來說，其會導致超額成本、低可靠度、或是過大的封裝尺寸。舉例來說，目前的中介板技術便不適用。熟習本技術的人士經由比較此些方式和參考圖式在本申請案的其餘部分中被提出的本揭示內容便會明白習知與傳統方式的進一步限制及缺點。
熟習本技術的人士經由比較此些系統和參考圖式在本申請 案的其餘部分中被提出的本揭示內容便會明白習知與傳統方式的進一步限制及缺點。
本揭示內容的各項觀點提供一種半導體封裝及其製造方法。舉例來說，但是沒有限制意義，本揭示內容的各項觀點提供一種使用無核心訊號分佈結構的三維半導體封裝及其製造方法，其實質上如該些圖式中的至少其中一者之中的顯示及/或配合該些圖式中的至少其中一者的說明，在申請專利範圍中會更完整被提出。
從下面的說明以及圖式之中將更完整瞭解本揭示內容的各項優點、觀點、與新穎特點以及支援實施例的各種被解釋範例的細節。
10:晶圓
20:載板
30:暫時性黏著劑
100:半導體裝置
110:訊號分佈結構
110a:訊號分佈結構的第一表面
110b:訊號分佈結構的第二表面
111:第一介電層
112:第一導體層
113:第二介電層
114:第二導體層
115:第三介電層
116:第一觸墊
117:第一柱
118:第二觸墊
120:第一半導體晶粒
121:接合觸墊
122:導體支柱
123:焊接帽
124:第一底部填充層
130:第一囊封劑
141:第一重新分佈結構
142:第一平台
143:第一凸塊觸墊
144:第一介電層
145:第二介電層
150:第二半導體晶粒
151:接合觸墊
152:導體支柱
153:焊接帽
154:第二底部填充層
160:第二囊封劑
170:導體凸塊
200:半導體裝置
250:第二半導體晶粒
300:半導體裝置
400:半導體裝置
419:第二柱
481:第二重新分佈結構
482:第二平台
483:第二凸塊觸墊
484:第一介電層
485:第二介電層
500:半導體裝置
圖1A至1K所示的係根據本揭示內容一實施例之製造半導體裝置的方法的剖視圖。
圖2所示的係根據本揭示內容另一實施例的半導體裝置的剖視圖。
圖3所示的係根據本揭示內容又一實施例的半導體裝置的剖視圖。
圖4所示的係根據本揭示內容又一實施例的半導體裝置的剖視圖。
圖5所示的係根據本揭示內容又一實施例的半導體裝置的剖視圖。
下面的討論藉由提供本揭示內容的範例而提出本揭示內容的各項觀點。此些範例並沒有限制性，且因此，本揭示內容之各項觀點的範疇不應受限於所提供範例的任何特殊特徵。在下面的討論中，「舉例來說」 以及「示範性」等用語皆沒有限制性並且大體上和「透過範例來說，但是沒有限制意義」、「舉例來說，但是沒有限制意義」、以及類似用語同義。
如本文中的用法，「及/或」的意義為藉由「及/或」來連接的列表之中的項目的任何一或更多者。舉例來說，「x及/或y」的意義為三要素集合{(x)、(y)、(x,y)}之中的任何要素。換言之，「x及/或y」的意義為「x與y之中的一或兩者」。於另一範例中，「x、y、及/或z」的意義為七要素集合{(x)、(y)、(z)、(x,y)、(x,z)、(y,z)、(x,y,z)}之中的任何要素。換言之，「x、y、及/或z」的意義為「x、y、以及z之中的一或更多者」。
本文中所使用的術語僅係為達成說明特殊範例的目的而沒有限制本揭示內容的意圖。如本文中的用法，除非文中額外清楚提及，否則單數的形式亦希望包含複數形式。進一步要瞭解的係，當本說明書中使用到「包括」、「包含」、「具有」、以及類似用詞時係表明所述特徵圖樣、數字、步驟、操作、元件、及/或器件的存在，但是並不排除有一或多個其它特徵圖樣、數字、步驟、操作、元件、器件、及/或其群組的存在，甚至並不排除加入一或多個其它特徵圖樣、數字、步驟、操作、元件、器件、及/或其群組。
應該瞭解的係，雖然本文中可以使用「第一」、「第二」、…等用詞來說明各種元件；不過，此些元件並不應該受限於此些用詞。此些用詞僅係用來區分其中一個元件以及另一個元件。因此，舉例來說，下文所討論的第一元件、第一器件、或是第一區段亦可被稱為第二元件、第二器件、或是第二區段，其並不會脫離本揭示內容的教示內容。同樣地，本文亦可能利用諸如「上方」、「下方」、「側邊」、以及類似用詞的各種空間術 語以相對的方式來區分其中一個元件和另一個元件。然而，應該瞭解的係，器件可以不同的方式來配向，舉例來說，一半導體裝置或封裝可以向側邊翻轉，俾使得其「頂端」表面面向水平方向並且使得其「側邊」表面面向垂直方向，其並不會脫離本揭示內容的教示內容。
還應該瞭解的係，除非額外清楚提及，否則，被耦合、被連接、被附接、以及類似詞包含直接與間接(舉例來說，利用一中間元件)耦合、連接、附接、…等。舉例來說，倘若元件A被耦合至元件B的話，元件A可以經由一中間訊號分佈結構間接被耦合至元件B、元件A可以直接被耦合至元件B(舉例來說，直接被黏接至元件B、直接被焊接至元件B、藉由直接金屬至金屬接合而被附接至元件B、…等)、…等。
在圖式中，為達清楚起見，結構、層、區域、…等的維度(舉例來說，絕對維度及/或相對維度)可能會被放大。此些維度雖然大體上表示一種範例施行方式；但是，它們並沒有限制性。舉例來說，倘若圖中所示的結構A大於區域B的話，這雖然大體上表示一種範例施行方式；但是，除非額外清楚提及，否則，結構A通常並不需要大於區域B。
本揭示內容的特定觀點可以在包括無核心訊號分佈結構的半導體封裝之中被發現。本揭示內容的範例觀點可以包括一無核心訊號分佈結構，其包括至少一介電層、至少一導體層、一第一表面、以及一和該第一表面反向的第二表面。該半導體封裝還可以包括：一第一半導體晶粒，其在一第一晶粒表面上有一第一接合觸墊，其中，該第一半導體晶粒透過該第一接合觸墊被接合至該無核心訊號分佈結構的第一表面；以及一第二半導體晶粒，其在一第二晶粒表面上有一第二接合觸墊，其中，該第二半 導體晶粒透過該第二接合觸墊被接合至該無核心訊號分佈結構的第二表面。該半導體封裝可以進一步包括：一金屬柱，其被電氣耦合至該無核心訊號分佈結構的第一表面；以及一第一囊封劑材料，用以囊封該第一半導體晶粒的側表面、該金屬柱、以及該無核心訊號分佈結構的第一表面的一部分，其中，該第一囊封劑材料的一表面為和該半導體晶粒的第一晶粒表面反向的第一半導體晶粒的表面共平面。該金屬柱可以包括銅並且延伸穿過該囊封劑材料。一第二囊封劑材料可以囊封該第二半導體晶粒。一第二金屬柱可以被耦合至該無核心訊號分佈結構並且延伸穿過該第二囊封劑材料。該第二囊封劑的一表面可以和該第二晶粒表面反向的第二半導體晶粒的表面為共平面。一導體支柱可以將該第一半導體晶粒的該第一接合觸墊電氣耦合至該無核心訊號分佈結構。一重新分佈結構可以在該第一囊封劑上並且被電氣耦合至該金屬柱，其中，該重新分佈結構可以包括至少一導體層以及至少一介電層。舉例來說，該重新分佈結構可以包括1μm至10μm的線寬度。
參考圖1A至1K，圖中所示的係根據本揭示內容一實施例之製造半導體裝置100的方法的剖視圖。
根據本揭示內容一實施例之製造半導體裝置100的方法包含：提供一晶圓(圖1A)；提供一訊號分佈結構，其具有一第一表面以及一第二表面(圖1B)；在該訊號分佈結構的第一表面上形成一第一觸墊以及一第一柱(圖1C)；將一第一半導體晶粒連接至該第一觸墊(圖1D)；利用一第一囊封劑來囊封該第一半導體晶粒與該第一柱(圖1E)；於該第一柱上形成一第一重新分佈結構及/或一第一觸墊(圖1F)；連接一載板(圖1G)；在移除 一晶圓之後於該訊號分佈結構的第二表面上形成一第二觸墊(圖1H)；將一第二半導體晶粒連接至該第二觸墊(圖1I)；利用一第二囊封劑來囊封該第二半導體晶粒並且移除該載板(圖1J)；以及形成導體互連結構(圖1 K)。
如圖1A中所示，一晶圓10可以被提供，其包括一矽基板、一玻璃基板、或是具有一實質上平面頂端表面的其它支撐結構，但是，本揭示內容的觀點並不受限於此。舉例來說，該晶圓10可以充當一基礎基板，於其上可以實施塗佈、光微影蝕刻、及/或電鍍，用以形成一訊號分佈結構110，本發明會參考圖1B進一步說明其範例。
圖1B所示的係一範例訊號分佈結構110，其具有一平面的第一表面110a(舉例來說，平面的第一表面)以及一和被形成在晶圓10的頂端表面的該第一表面110a反向的第二表面110b(舉例來說，平面的第二表面)。於一範例實施例中，該訊號分佈結構110可以藉由下面方式來形成：於該晶圓10的頂端表面提供一第一介電層111；於該第一介電層111上形成一第一導體層112；於該第一導體層112上與該第一介電層111上形成一第二介電層113；於該第二介電層113上形成一第二導體層114；以及於該第二導體層114上與該第一介電層111上形成一第三介電層115。此外，圖中雖然並未顯示；但是，該第一導體層112以及該第二導體層114可以藉由一(舉例來說，穿過該第二介電層113的)導體通孔(圖中並未顯示)相互電氣連接。進一步言之，該些第一導體層112與第二導體層114、第一介電層111、第二介電層113、第三介電層115、以及該導體通孔(圖中並未顯示)可以藉由如上面所述的通用塗佈、光微影蝕刻、及/或電鍍來形成。
於一範例實施例中，該訊號分佈結構110可以先利用一晶圓 製造製程及/或一凸塊製程來形成，但是接著會從該晶圓處被移除，也就是，沒有任何支撐基板或晶粒。據此，該訊號分佈結構110可以有落在1μm至10μm範圍之中的線寬度，並且該些導體層與介電層的厚度可以為1μm至10μm。相反地，因為一印刷電路板藉由一基板組裝製程來形成，所以，其具有實質上較大的線寬度。此外，和印刷電路板不同，根據本揭示內容的訊號分佈結構110並沒有一粗厚的堅硬層，也就是，該訊號分佈結構為「無核心」。所以，訊號分佈結構110的無核心觀點會達成較小的線寬度以及縮減的總封裝厚度。
於一範例實施例中雖然圖解兩個導體層以及三個介電層；但是，本揭示內容的觀點並不受限於此。舉例來說，該訊號分佈結構110可以被形成為具有任何數量的導體層及/或介電層。舉例來說，該等訊號分佈結構110亦可以包括單一導體層以及兩個介電層、三個導體層以及四個介電層、…等。
舉例來說，該些第一導體層112與第二導體層114以及該導體通孔可以包括銅、銅合金、鋁、鋁合金、以及雷同的材料；但是，本揭示內容的觀點並不受限於此。此外，舉例來說，第一介電層111、第二介電層113、第三介電層115則可以包括雙馬來醯亞胺-三氮雜苯(BT)、酚系樹脂、聚醯亞胺(PI)、環苯丁烯(BCB)、聚苯并噁唑纖維(PBO)、環氧樹脂、矽的氧化物、矽的氮化物、以及雷同的材料；但是，本揭示內容的觀點並不受限於此。
於第一介電層111、第二介電層113、及/或第三介電層115包括有機材料的範例情境中，它們可以藉由下面方式來形成：網印、旋塗、 或是其它雷同的製程；但是，本揭示內容的觀點並不受限於此。於第一介電層111、第二介電層113、以及第三介電層115包括無機材料的另一範例情境中，它們可以藉由下面方式來形成：化學氣相沉積(Chemical Vapor Deposition，CVD)、物理氣相沉積(Physical Vapor Deposition，PVD)、或是其它雷同的製程；但是，本揭示內容的觀點並不受限於此。該些第一導體層112與第二導體層114可以藉由下面方式來形成：金屬沉積、金屬蒸發、金屬濺鍍、以及雷同的製程；但是，本揭示內容的觀點並不受限於此。
如圖1C中所示，第一觸墊116以及第一柱117可以被形成在該訊號分佈結構110的第一表面110a上及/或被連接至該訊號分佈結構110的第一表面110a，舉例來說，被連接至第二導體層114。更明確的說，複數個第一觸墊116可以矩陣配置的方式被定位在該訊號分佈結構110的第一表面110a上。另外，複數個第一柱117可以被形成在複數個第一觸墊116上，它們可以被定位圍繞該訊號分佈結構110的該第一表面110a的周圍(舉例來說，被定位在該第一表面110a的一邊緣處或是附近)。
舉例來說，該第一柱117可以高於(舉例來說，縱向厚於)該第一觸墊116，並且可以被形成為具有大於或等於該第一半導體晶粒120之厚度的高度(舉例來說，縱向厚度)(舉例來說，參見圖1D)。
該第一觸墊116及/或該第一柱117可以藉由通用的電鍍以及光微影蝕刻來形成並且可以包括銅、銅合金、鋁、鋁合金、或是雷同的材料；但是，本揭示內容的觀點並不受限於此。
如圖1D中所示，一第一半導體晶粒120可以被電氣連接至該第一觸墊116，其可以被置中於該訊號分佈結構110之中。該第一半導體 晶粒120可以包括一接合觸墊121，其位於至少一主動裝置所在的晶粒的主動表面。一導體支柱122以及一焊接帽123可以被形成在該接合觸墊121上，用於電氣耦合至該晶粒120。該焊接帽123可以藉由回焊製程被電氣連接至該第一觸墊116。此外，一焊接凸塊可以被形成在該接合觸墊121上。該焊接凸塊可以藉由回焊製程被電氣連接至該第一觸墊116。於一範例實施例中，該導體支柱122以及該焊接帽123可以被形成為具有小於焊接凸塊的寬度。因此，在細微間距中，該導體支柱122以及該焊接帽123可以不同於焊接凸塊的方式被運用。然而，應該注意的係，本揭示內容的範疇並不受限於可被用來將該第一半導體晶粒120附接至該訊號分佈結構110的任何特殊類型互連結構。
此外，為在完成回焊製程之後牢牢地固定該第一半導體晶粒120，一第一底部填充層124可以被形成在該第一半導體晶粒120與該訊號分佈結構110之間。該第一底部填充層124可以覆蓋該導體支柱122以及該焊接帽123，從而提高該訊號分佈結構110以及該第一半導體晶粒120之間的電氣連接的可靠度。此第一底部填充層124可以任何各式各樣的方式來形成，舉例來說，可以藉由毛細管底部填充的方式來形成。應該注意的係，該底部填充層124亦可以在該第一半導體晶粒120被放置在及/或被附接至該訊號分佈結構110時被形成，舉例來說，運用一預塗敷底部填充層。同樣應該注意的係，該第一半導體晶粒120可以在一模製製程期間被底部填充，舉例來說，藉由模製底部填充方式來進行。
如圖1E中所示，該第一半導體晶粒120以及該第一柱117可以利用第一囊封劑130來囊封，其可以保護該第一半導體晶粒120以及該 第一柱117，避免受到外部環境破壞。於一範例情境中，該第一囊封劑130還可以囊封該第一底部填充層124。或者，如本文中的討論，該第一囊封劑130還可以提供該第一底部填充層124。該第一柱117的一頂端表面可以從該第一囊封劑130的一頂端表面處裸露至外面，從而可以讓該第一重新分佈結構141及/或該第一凸塊觸墊143稍後被連接至該第一柱117(舉例來說，參見圖1F)。該第一柱117的該頂端表面以及該第一囊封劑130的該頂端表面可以為共平面並且可以實質上為平面；不過，此共平面性並非必要。在囊封期間，該第一囊封劑130雖然可以囊封該第一柱117；然而，該第一柱117的該頂端表面卻可以藉由研磨及/或蝕刻而裸露及/或突出至該第一囊封劑130的外面。應該注意的係，該第一柱117的該頂端表面可以藉由形成一通孔貫穿該第一囊封劑(舉例來說，藉由機械研磨及/或雷射燒蝕、…等)而露出。
如圖1F中所示，一第一重新分佈結構141及/或第一凸塊觸墊143可以被電氣連接至該第一柱117，舉例來說，被電氣連接至該第一柱117的一頂端表面。於一範例實施例中，該第一重新分佈結構141可以包括一或更多個導體層以及介電層，用以橫向重新分佈電氣連接線(舉例來說，橫向分佈在該第一囊封劑130的該頂端表面的上方)。於圖1F中所示的範例中，該第一重新分佈結構可以被電氣連接至該第一半導體晶粒120左邊的該些第一柱117中的一或更多者，並且該第一凸塊觸墊143可以被電氣連接至在該第一半導體晶粒120右邊的該些第一柱117中的一或更多者。舉例來說，在該第一重新分佈結構141之中的導體層可以包括銅、銅合金、鋁、鋁合金、以及雷同的材料；但是，本揭示內容的觀點並不受限於此。
舉例來說，在該第一重新分佈結構141之中的導體層可以運用下面各式各樣製程中的一或更多者來形成或沉積：電極電鍍、無電極電鍍、化學氣相沉積(CVD)、濺鍍或物理氣相沉積(PVD)、離子氣相沉積、印刷、…等。此外，舉例來說，在該重新分佈結構141之中的介電層可以包括：雙馬來醯亞胺-三氮雜苯(BT)、酚系樹脂、聚醯亞胺(PI)、環苯丁烯(BCB)、聚苯并噁唑纖維(PBO)、環氧樹脂、矽的氧化物、矽的氮化物、以及雷同的材料；但是，本揭示內容的觀點並不受限於此。舉例來說，在該第一重新分佈結構141之中的介電層可以運用下面各式各樣介電質形成或沉積製程中的一或更多者來形成：印刷、旋塗、噴塗、燒結、熱氧化、物理氣相沉積(PVD)、化學氣相沉積(CVD)、離子氣相沉積、薄片層疊、…等。
一第一介電層144(在本文中其亦可以被稱為保護層)可以被形成在第一囊封劑130的一表面上，舉例來說，圍繞該第一柱117的周圍，並且該第一重新分佈結構141與該第一凸塊觸墊143的一第一導體層接著可以被形成。該第一導體層中不需要裸露至外面的一區域可以被第二介電層145(在本文中其亦可以被稱為保護層)覆蓋。該些第一介電層144與第二介電層145可以包括用以電氣隔離導體層的介電層，並且可以包括通用的雙馬來醯亞胺-三氮雜苯(BT)、酚系樹脂、聚醯亞胺(PI)、環苯丁烯(BCB)、聚苯并噁唑纖維(PBO)、環氧樹脂、矽的氧化物、矽的氮化物、或是雷同的材料；但是，本揭示內容的觀點並不受限於此。該些第一介電層144與第二介電層145可以藉由下面的方式來形成，但是，本揭示內容的觀點並不受限於此：化學氣相沉積(CVD)、物理氣相沉積(PVD)、或是其它雷同的沉積製程。
於一範例實施例中，該第一重新分佈結構141可以為從外面延伸至裡面的扇入型(fan-in type)(舉例來說，從該第一半導體晶粒120之覆蓋面積的外面將訊號分佈至該第一半導體晶粒120之覆蓋面積的裡面)。據此，裸露至外面的第一平台142便可以被定位在該第一半導體晶粒120上(或是上方)。依此方式，導體凸塊170(或是任何各式各樣類型的互連結構)便可以於稍後被電氣連接至該第一平台142以及該第一凸塊觸墊143。
舉例來說，該第一重新分佈結構141與該第一凸塊觸墊143的該(些)導體層可以包括銅、銅合金、鋁、鋁合金、或是雷同的材料；並且可以藉由通用的塗佈、光微影蝕刻、及/或電鍍來形成，但是，本揭示內容的觀點並不受限於此。
於圖1F中所示的範例施行方式中，該些第一介電層144與第二介電層145係被形成在圖中的左邊區域(舉例來說，第一半導體晶粒120的中央的左邊、第一半導體晶粒120的最右邊四分之一部分的左邊、第一半導體晶粒120的最右邊四分之三部分的左邊、…等)，而僅有該第一保護層144係被形成在圖中的實質上右邊的區域(舉例來說，第一半導體晶粒120的中央的右邊、第一半導體晶粒120的最左邊四分之一部分的右邊、第一半導體晶粒120的最左邊四分之三部分的右邊、…等)，從而施行一種不對稱的裝置。應該注意的係，此不對稱的介電層形成方式並非必要的方式。
如圖1G中所示，該結構會被翻轉並且一載板20接著會暫時被黏接至該經翻轉的裝置的一底部表面。據此，一暫時性黏著劑30可以被塗敷至該第一凸塊觸墊143與該第一重新分佈結構141(舉例來說，包含其已露出的導體層及/或介電層)，並且該載板20便可以被貼附。該暫時性黏 著劑30可以藉由網印、旋塗、或是雷同的製程來形成；但是，本揭示內容的觀點並不受限於此。此外，該暫時性黏著劑30一可以為一熱脫離膠帶；但是，本揭示內容的觀點並不受限於此。該載板20可以包括不鏽鋼、玻璃、假性半導體晶圓(舉例來說，沒有有功能的半導體裝置)、有孔陶瓷、或是雷同的材料；但是，本揭示內容的觀點並不受限於此。
如圖1H中所示，被用來形成該訊號分佈結構110的晶圓10可以被移除。第二觸墊118(或是複數個第二觸墊118)可以被形成在因移除晶圓10而裸露至外面的訊號分佈結構110的第二表面110b上。於此範例中，晶圓10可以經由研磨與蝕刻而從該訊號分佈結構110處被完全移除；不過，本揭示內容的範疇並不受限於此。該第二觸墊118接著可以藉由光微影蝕刻與電鍍被形成；不過，本揭示內容的範疇並不受限於此。舉例來說，該第二觸墊118可以被電氣連接至該訊號分佈結構110的第一導體層112。圖中雖然並未顯示；不過，必要時，該第二觸墊118的周圍區域可以被一額外的介電層(在本文中其亦可以被稱為保護層)覆蓋。
如圖1I中所示，第二半導體晶粒150可以被電氣連接至以上面所述方式所定位的第二觸墊118。舉例來說，該第二半導體晶粒150可以包括一接合觸墊151，並且一導體支柱152以及一焊接帽153可以被形成在該接合觸墊151上。該焊接帽153可以藉由回焊製程被電氣連接至該第二觸墊118。此外，一焊接凸塊亦可以被形成在該接合觸墊151上。該焊接凸塊可以藉由回焊製程被電氣連接至該第二觸墊118。應該注意的係，本揭示內容的範疇並不受限於可被用來將該第二半導體晶粒150附接至該訊號分佈結構110的任何特殊類型互連結構。
此外，為在完成該製程之後牢牢地固定該第二半導體晶粒150，一第二底部填充層154可以被形成在該第二半導體晶粒150與該訊號分佈結構110之間。於一範例情境中，該第二底部填充層154可以覆蓋該導體支柱152以及該焊接帽153的側表面。此第二底部填充層154可以任何各式各樣的方式來形成，舉例來說，可以藉由毛細管底部填充的方式來形成。應該注意的係，該底部填充層124亦可以在該第一半導體晶粒120被放置在及/或被附接至該訊號分佈結構110時被形成，舉例來說，運用一預塗敷底部填充層。同樣應該注意的係，該第一半導體晶粒120可以在一模製製程期間被底部填充，舉例來說，藉由模製底部填充方式來進行。
如圖1J中所示，該第二半導體晶粒150可以利用第二囊封劑160來囊封，從而保護該第二半導體晶粒150，避免受到外部環境破壞。於一範例情境中，該第二囊封劑160還可以囊封該第二底部填充層154。或者，如本文中的討論，該第二囊封劑160還可以提供該第二底部填充層154。此外，該第二半導體晶粒150的一頂端表面可以從該第二囊封劑160的一頂端表面處裸露至外面，從而改良將熱傳導至該晶粒外面的效果。該第二半導體晶粒150的該頂端表面以及該第二囊封劑160的該頂端表面可以為共平面並且可以實質上為平面。於另一範例情境中，該第二半導體晶粒150的該頂端表面可以被該第二囊封劑160完全囊封。
載板20接著可以運用任何或各式各樣的技術來移除。舉例來說，熱量或是UV光可以被供應用以消除該暫時性黏著劑30的黏著性，從而移除該載板20。或者，該載板20可以先藉由研磨及/或蝕刻來移除，而該暫時性黏著劑30則接著可以利用化學溶液來移除。
於利用化學溶液來移除該暫時性黏著劑30的一範例施行方式中，該載板20可以包括一有孔陶瓷，以便讓該化學溶液快速抵達該暫時性黏著劑30。該載板20與該暫時性黏著劑30接著便可以物理性的方式從該裝置處被脫離。
如圖1K中所示，在形成導體互連結構(舉例來說，導體凸塊、導體球、導體支柱、導體電線、…等)中，該些導體互連結構170可以被電氣連接至因移除該載板20與該暫時性黏著劑30而露出的第一重新分佈結構141的第一平台142以及第一凸塊觸墊143。於一範例實施例中，一揮發性助焊劑可以被形成在(舉例來說，點狀)該第一平台142以及該第一凸塊觸墊143上，並且該些導體互連結構170(舉例來說，導體凸塊或導體球)接著可以暫時被附接至該揮發性助焊劑。而後，該裝置便可以被運送至溫度維持在約160℃至約250℃的範圍之中的熔爐處。據此，該揮發性助焊劑可以被該揮發而接著被移除，並且該些導體互連結構170可以分別被電氣連接至該第一平台142以及該第一凸塊觸墊143。而後，該些導體互連結構170便可以藉由冷卻而被固化。
導體互連結構170可以包括共晶焊劑(舉例來說，Sn37Pb)、擁有高熔點的高鉛焊劑(舉例來說，Sn95Pb)、無鉛焊劑(舉例來說，SnAg、SnCu、SnZn、SnAu、SnZnBi、SnAgCu、以及SnAgBi)、以及雷同的材料；但是，本揭示內容的範疇並不受限於此。舉例來說，該些導體互連結構170亦可以包括導體支柱或導體柱，其可以包括銅、鎳、銀、鋁、…等，並且可以藉由電鍍、濺鍍、…等來形成。
此外，在形成該些導體互連結構170之前或之後可以實施一 雷射標記製程，舉例來說，用以在該第二半導體晶粒150的一表面上標記裝置的類型、製造商的名字、生產日期、…等。
上面所述的實施例雖然僅針對單一半導體裝置100來作說明；不過，實務上，可以同步形成複數個半導體裝置100。在形成該些導體互連結構170之後，可以實施一切割(或是其它單體裁切)製程，用以將所生成的產品分開成多個獨特的半導體裝置100。舉例來說，該切割製程可以藉由利用雷射或鑽石刀片依序切割至少第一囊封劑130、訊號分佈結構110、以及第二囊封劑160來實施。
如上面所述，根據本揭示內容的各項觀點，本發明提供一種半導體裝置及其製造方法，其利用一訊號分佈結構來相互電氣連接具有不同圖樣寬度的多個半導體晶粒。於一範例實施例中，該第一半導體晶粒120可以為一具有奈米級圖樣寬度的高科技半導體晶粒，而該第二半導體晶粒150可以為一具有光微影術米級圖樣寬度的低科技半導體晶粒。該第一半導體晶粒120以及該第二半導體晶粒150可以經由該訊號分佈結構110被相互電氣連接。
此外，根據本揭示內容，本發明提供一種具有低製造成本並且具有小厚度的半導體裝置及其製造方法，其係利用訊號分佈結構110而沒有直通矽通孔。於一範例實施例中，該訊號分佈結構110包括導體層以及導體通孔；但是並不包含可能既昂貴並且會降低產量的直通矽通孔。
進一步言之，根據本揭示內容，本發明提供一種沒有使用直通矽通孔及/或印刷電路板所製造的半導體裝置及其製造方法。舉例來說，該半導體裝置可以為扇入型及/或扇出型晶圓級半導體裝置。
此外，根據本揭示內容，本發明提供一種半導體裝置及其製造方法，其能夠藉由將半導體晶粒附接至一訊號分佈結構的頂端表面與底部表面來調整或維持翹曲平衡。
參考圖2，圖中所示的係根據本揭示內容另一實施例的半導體裝置200的剖視圖。舉例來說，該範例半導體裝置200可以和圖1A至1K中所示的範例半導體裝置100及/或其製造方法共用任何或全部特徵。
如圖2中所示，根據本揭示內容的半導體裝置200可以包含複數個第二半導體晶粒250。個別的半導體晶粒250可以經由導體支柱152以及焊接帽153或焊接凸塊被電氣連接至訊號分佈結構110的第二觸墊118。舉例來說，該訊號分佈結構110可以在該些第二半導體晶粒250中的任何一或更多個第二半導體晶粒以及該些第二半導體晶粒250中的一或更多個其它第二半導體晶粒之間提供訊號路徑。另外，舉例來說，該訊號分佈結構110亦可以在該些第二半導體晶粒250中的任何一或更多個第二半導體晶粒以及第一半導體晶粒120之間提供訊號路徑。除此之外，舉例來說，該訊號分佈結構還可以在該複數個第二半導體晶粒250中的一或更多個第二半導體晶粒以及該些導體互連結構170之間提供訊號路徑(並且因而連接至該半導體裝置200所耦合的另一裝置)。
此外，第二底部填充層154亦可以被形成在該些第二半導體晶粒250中的每一者以及該訊號分佈結構110之間。
依此方式，該複數個第二半導體晶粒250(每一個第二半導體晶粒250有相同或不相同的固有功能)可以被連接至單一個訊號分佈結構110，從而提供具有各種功能的半導體裝置200。
參考圖3，圖中所示的係根據本揭示內容又一實施例的半導體裝置300的剖視圖。舉例來說，該範例半導體裝置300可以和圖1A至1K以及圖2中所示的範例半導體裝置100與200及/或其製造方法共用任何或全部特徵。
如圖3中所示，該半導體裝置300被配置成使得一第一半導體晶粒120的一底部表面沒有完全被第一囊封劑130囊封，舉例來說，僅有第一半導體晶粒120的側表面被第一囊封劑130囊封，而第一半導體晶粒120的底部表面並沒有被第一囊封劑130囊封。於此範例中，第一半導體晶粒120的底部表面和第一囊封劑130的底部表面為共平面。
舉例來說，第一介電層144及/或第一保護層144與第二保護層145可以被形成在第一半導體晶粒120的底部表面上，而並非如圖1F中所示般地被形成在第一囊封劑130的底部表面上。第一重新分佈結構141的一第一導體層以及一第一平台142可以被形成在該第一介電層144以及該第二介電層145之間(舉例來說，經由該第二介電層145中的一孔洞而露出)，並且一導體互連結構170可以被連接至該第一平台142。
依此方式，本揭示內容藉由第一保護層144及/或第一保護層144與第二保護層145來覆蓋第一半導體晶粒120的底部表面(沒有被第一囊封劑130囊封)而提供具有小厚度及改良的熱輻射效能的半導體裝置300，第一保護層144及/或第一保護層144與第二保護層145可以包括多個薄層。
參考圖4，圖中所示的係根據本揭示內容又一實施例的半導體裝置400的剖視圖。舉例來說，該範例半導體裝置400可以和圖1A至1K、 圖2、以及圖3中所示的範例半導體裝置100、200、300及/或其製造方法共用任何或全部特徵。如圖4中所示，半導體裝置400包括：一第二柱419，其被形成在該訊號分佈結構110的第二表面110b上；以及一第二重新分佈結構481；及/或一被連接至該第二柱419的第二凸塊觸墊483。
該第二柱419可以被形成在一被連接至該訊號分佈結構110的第二表面110b(舉例來說，第一導體層112)的第二觸墊118上。更明確的說，複數個第二觸墊118可以矩陣配置的方式被排列在該訊號分佈結構110的第二表面110b上。另外，複數個該些第二柱419可以被形成在複數個該些第二觸墊118上，於此範例中，它們被定位圍繞該訊號分佈結構110的該第二表面110b的周圍(舉例來說，被定位在該第二表面110b的一邊緣處或是附近)。
該第二觸墊118及/或該第二柱419可以藉由通用的電鍍或是光微影蝕刻來形成並且可以包括銅、銅合金、鋁、鋁合金、或是雷同的材料；但是，本揭示內容的觀點並不受限於此。
此外，於一範例實施例中，該第二重新分佈結構481可以被電氣連接至可以被電氣連接至該第二半導體晶粒150左邊的該些第二柱419中的一或更多者，並且該第二凸塊觸墊483可以被電氣連接至在該第二半導體晶粒150右邊的該些第二柱419中的一或更多者。一第一介電層484可以先被形成在該第二囊封劑160的表面以及該第二半導體晶粒150的表面，其有一用於該第二柱419的開口。一第二凸塊觸墊483及/或該第二重新分佈結構481的一第一導體層接著可以被形成，並且該第二重新分佈結構481的該第一導體層中不需要裸露至外面的一區域可以被第二介電層485覆蓋。
於一範例實施例中，該第二重新分佈結構481為從外面延伸至裡面的扇入型(舉例來說，從該第二半導體晶粒150之覆蓋面積的外面將訊號分佈至該第二半導體晶粒150之覆蓋面積的裡面)。據此，裸露至外面的第二平台482便可以被定位在該第二半導體晶粒150上(或是上方)。依此方式，多個不同的半導體裝置(圖中並未顯示)便可以於稍後被鑲嵌在該第二重新分佈結構481的該第二平台482以及該第二凸塊觸墊483上。據此，圖4所示的係一種封裝上封裝(Package-On-Package，POP)型半導體裝置400。
第一介電層484與第二介電層485可以被形成在圖中的實質上左邊區域(舉例來說，第一半導體晶粒120的中央的左邊、第一半導體晶粒120的最右邊四分之一部分的左邊、第一半導體晶粒120的最右邊四分之三部分的左邊、…等)，而該第一介電層484可以被形成在圖中的實質上右邊的區域(舉例來說，第一半導體晶粒120的中央的右邊、第一半導體晶粒120的最左邊四分之一部分的右邊、第一半導體晶粒120的最左邊四分之三部分的右邊、…等)，從而施行一種不對稱的裝置。
參考圖5，圖中所示的係根據本揭示內容又一實施例的半導體裝置500的剖視圖。舉例來說，該範例半導體裝置500可以和圖1A至1K、圖2、圖3、以及圖4中所示的範例半導體裝置100、200、300、400及/或其製造方法共用任何或全部特徵。
如圖5中所示，半導體裝置500包括一裸露至外面的第二半導體晶粒150。依此方式，該第二半導體晶粒150的頂端表面與側表面不會被第二囊封劑160囊封，而是裸露至外面。一第二底部填充層154可以被填充在該第二半導體晶粒150與一訊號分佈結構110之間。
依此方式，本揭示內容藉由完全裸露該第二半導體晶粒150的頂端表面與側表面而提供具有改良的熱輻射效能的半導體裝置500。應該注意的係，該第二底部填充層154可以接觸該第二半導體晶粒150的該些側表面中的至少一部分。
本揭示內容提供一種使用無核心訊號分佈結構的半導體封裝。該無核心訊號分佈結構可以包括至少一介電層、至少一導體層、一第一表面、以及一和該第一表面反向的第二表面。該半導體封裝還可以包括：一第一半導體晶粒，其在一第一晶粒表面上有一第一接合觸墊，其中，該第一半導體晶粒透過該第一接合觸墊被接合至該無核心訊號分佈結構的第一表面；以及一第二半導體晶粒，其在一第二晶粒表面上有一第二接合觸墊，其中，該第二半導體晶粒透過該第二接合觸墊被接合至該無核心訊號分佈結構的第二表面。該半導體封裝可以進一步包括：一第一囊封劑材料，用以囊封該第一半導體晶粒的側表面以及該無核心訊號分佈結構的第一表面的一部分；以及一位於該第一囊封劑上的重新分佈結構，其中，該重新分佈結構包括至少一導體層以及至少一介電層。
一第一金屬柱可以位在該無核心訊號分佈結構上相鄰於該第一半導體晶粒的第一邊緣，其中，該第一金屬柱延伸穿過該囊封劑材料。一第二金屬柱可以位在該無核心訊號分佈結構上相鄰於該第一半導體晶粒的第二邊緣，其中，該第二金屬柱延伸穿過該囊封劑材料。該重新分佈結構可以被電氣耦合至該第一金屬柱以及一位於該第一囊封劑上的互連結構。
該重新分佈結構的一介電層可以接觸該第一金屬柱與該互 連結構；但是，沒有接觸該第二金屬柱。該互連結構可以包括一導體凸塊。一第二金屬柱可以被耦合至該無核心訊號分佈結構並且延伸穿過該第二囊封劑材料。一第二囊封劑可以囊封該第二半導體晶粒並且和該第二半導體晶粒中與該第二晶粒表面反向的表面共平面。
本揭示內容的實施例提供一種半導體裝置，該半導體裝置藉由利用一訊號分佈結構來相互電氣連接具有不同圖樣寬度的半導體晶粒而施行本揭示內容的製造方法。本揭示內容的實施例提供一種具有低製造成本並且具有小厚度的半導體裝置及其製造方法，其係利用訊號分佈結構而沒有使用TSV。
本揭示內容的實施例提供一種不需要利用TSV及/或印刷電路板便能夠製造的半導體裝置及其製造方法，並且能夠製造一種扇入型及/或扇出型晶圓級封裝及/或封裝上封裝(POP)。本揭示內容的實施例提供一種半導體裝置及其製造方法，其能夠藉由將半導體晶粒附接至一訊號分佈結構的頂端表面與底部表面來調整或維持翹曲平衡。
根據本揭示內容的一項觀點，本發明提供一種製造半導體裝置的方法，該製造方法包含：在一晶圓的一表面上形成一訊號分佈結構，其具有一第一表面與一第二表面；在該訊號分佈結構的第一表面上形成一第一觸墊與一第一柱；將該第一半導體晶粒電氣連接至該訊號分佈結構的該第一觸墊；利用一第一囊封劑來囊封該第一柱與該第一半導體晶粒；將一載板附接至該第一囊封劑並且移除該晶圓；在該訊號分佈結構的第二表面上形成一第二觸墊並且將一第二半導體晶粒電氣連接至該第二觸墊；以及在移除該載板之後於該第一柱上形成一導體互連結構。
根據本揭示內容的另一項觀點，本發明提供一種半導體裝置，其包含一訊號分佈結構，該訊號分佈結構具有一第一表面與一第二表面，其中，該第一表面包含被形成在其上的一第一觸墊以及一第一柱，而該第二表面包含被形成在其上的一第二觸墊。該半導體裝置還包含：一第一半導體晶粒，其被電氣連接至該訊號分佈結構的第一觸墊；一第一囊封劑，用以囊封該第一柱與該第一半導體晶粒；一第二半導體晶粒，其被電氣連接至該訊號分佈結構的第二觸墊；以及一導體互連結構，其被電氣連接至該第一柱。
如上面所述，在根據本揭示內容之實施例的半導體裝置及其製造方法中施行一種製程，其利用一訊號分佈結構來相互電氣連接具有不同圖樣寬度的半導體晶粒。於一範例實施例中，一具有奈米級圖樣的半導體晶粒會被電氣連接至該訊號分佈結構的一頂端表面，而具有微米級圖樣的另一半導體晶粒則被電氣連接至該訊號分佈結構的一底部表面。
此外，在根據本揭示內容之實施例的半導體裝置及其製造方法中，該半導體裝置能夠利用一訊號分佈結構而不必利用直通矽通孔以低成本來製造並且具有小厚度。於一範例實施例中，該訊號分佈結構包括導體層、介電層、以及導體通孔，但是並不包含TSV，從而可以低製造成本來提供該具有縮減厚度的半導體裝置。
進一步言之，在根據本揭示內容之實施例的半導體裝置及其製造方法中，該半導體裝置不需要利用TSV或印刷電路板便能夠被製造，並且能夠製造一種扇入型及/或扇出型晶圓級封裝及/或封裝上封裝(POP)。於一範例實施例中，本揭示內容提供一種藉由下面方式所製造的封裝上封裝 (POP)裝置：製備一具有被電氣連接至一導體柱之扇入型及/或扇出型重新分佈結構的晶圓級封裝；或是製備另一導體柱並且藉由被電氣連接至該導體柱的另一重新分佈結構在該導體柱上鑲嵌另一封裝。
此外，在根據本揭示內容之實施例的半導體裝置及其製造方法中，其能夠藉由將半導體晶粒附接至一訊號分佈結構的頂端表面與底部表面來調整或維持翹曲平衡。於一範例實施例中，本揭示內容提供一種半導體裝置，其藉由將具有實質上相同尺寸及/或厚度的半導體晶粒附接至該訊號分佈結構的頂端表面與底部表面而在該訊號分佈結構的頂端表面與底部表面的熱膨脹係數之間有小差異，從而防止翹曲。
本文雖然已經參考特定範例實施例說明過支援本揭示內容的各項觀點；不過，熟習本技術的人士便會瞭解，可以進行各種變更並且可以等效例來取代，其並不會脫離本揭示內容的範疇。此外，亦可以進行許多修飾，以便讓一特殊情況或材料適應於本揭示內容的教示內容，但卻不會脫離本揭示內容的範疇。所以，本揭示內容並不希望受限於已揭的特殊範例實施例；相反地，本揭示內容希望涵蓋落在隨附申請專利範圍的範疇裡面的所有實施例。
110‧‧‧訊號分佈結構
116‧‧‧第一觸墊
117‧‧‧第一柱
118‧‧‧第二觸墊
120‧‧‧第一半導體晶粒
121‧‧‧接合觸墊
122‧‧‧導體支柱
123‧‧‧焊接帽
124‧‧‧第一底部填充層
130‧‧‧第一囊封劑
141‧‧‧第一重新分佈結構
142‧‧‧第一平台
143‧‧‧第一凸塊觸墊
144‧‧‧第一介電層
145‧‧‧第二介電層
151‧‧‧接合觸墊
152‧‧‧導體支柱
153‧‧‧焊接帽
154‧‧‧第二底部填充層
160‧‧‧第二囊封劑
170‧‧‧導體凸塊
200‧‧‧半導體裝置
250‧‧‧第二半導體晶粒

Claims (23)

  1. 一種半導體封裝，其包括：一無核心訊號分佈結構，其包括至少一介電層、至少一導體層、一頂端表面、以及一底部表面；一第一電子器件，在該第一電子器件的一底部表面上具有一第一接合觸墊，其中該第一電子器件透過該第一接合觸墊以及在該第一接合觸墊和該無核心訊號分佈結構的該頂端表面之間的一導體結構，而被接合至該無核心訊號分佈結構的該頂端表面，其中該導體結構在該第一電子器件的該底部表面和該無核心訊號分佈結構的該頂端表面之間建立一空間；一第二電子器件，在該第二電子器件的一頂端表面上具有一第二接合觸墊，其中該第二電子器件透過該第二接合觸墊而被接合至該無核心訊號分佈結構的該底部表面；一電氣互連，其被電氣耦合至該無核心訊號分佈結構的該底部表面，其中該電氣互連的至少一部分在該半導體封裝的外部，並且經過配置以將該半導體封裝電氣耦合到該半導體封裝外部的一器件；以及一第一囊封劑材料，其用以囊封至少：該第一電子器件的側表面和一頂端表面；及該無核心訊號分佈結構的該頂端表面的一部分。
  2. 根據申請專利範圍第1項的半導體封裝，其中，該電氣互連被電氣連接到該第一電子器件和該第二電子器件中的一者或兩者。
  3. 根據申請專利範圍第1項的半導體封裝，其包括一第二囊封劑材料，用以囊封該電氣互連以及該第二電子器件的至少側表面，而不囊封該電氣 互連的在該半導體封裝外部的至少該部分。
  4. 根據申請專利範圍第1項的半導體封裝，其中：該第一囊封劑材料在該第一電子器件的該底部表面和該無核心訊號分佈結構的該頂端表面之間的該空間的至少一部分中形成一底部填充層；以及該底部填充層囊封該導體結構。
  5. 根據申請專利範圍第3項的半導體封裝，其中，用該第二囊封劑材料所形成的一第二囊封劑的一底部表面的至少一部分和該第二電子器件的一底部表面為共平面。
  6. 根據申請專利範圍第1項的半導體封裝，其包括在該第一電子器件的該底部表面和該無核心訊號分佈結構的該頂端表面之間的該空間中的一底部填充層，其中該底部填充層囊封該導體結構。
  7. 根據申請專利範圍第6項的半導體封裝，其中，該底部填充層覆蓋該第一電子器件的側表面的至少一部分。
  8. 根據申請專利範圍第3項的半導體封裝，其中：該電氣互連包括一柱和一球；該柱包括被耦合到該無核心訊號分佈結構的一第一末端；該球被耦合到該柱的與該第一末端反向的一第二末端；該電氣互連的在該半導體封裝外部的該部分包括該球的至少一部分；以及該柱所具有的一高度大於該第二電子器件的一高度。
  9. 根據申請專利範圍第1項的半導體封裝，其中該導體結構包括一導體 支柱。
  10. 根據申請專利範圍第9項的半導體封裝，其中：該第一囊封劑材料在該第一電子器件的該底部表面和該無核心訊號分佈結構的該頂端表面之間的該空間的至少一部分中形成一底部填充層；以及該底部填充層囊封該導體支柱的至少一側壁。
  11. 根據申請專利範圍第1項的半導體封裝，其中該導體結構包括一焊接凸塊。
  12. 根據申請專利範圍第3項的半導體封裝，其中：該第二電子器件透過該第二接合觸墊以及在該第二接合觸墊和該無核心訊號分佈結構的該底部表面之間的一第二導體結構，而被接合至該無核心訊號分佈結構的該底部表面；該第二導體結構經過配置以在該第二電子器件的該頂端表面和該無核心訊號分佈結構的該底部表面之間建立一空間；以及該第二囊封劑材料底部填充在該第二電子器件的該頂端表面和該無核心訊號分佈結構的該底部表面之間的該空間的至少一部分，並且囊封該第二導體結構的至少一側壁。
  13. 根據申請專利範圍第1項的半導體封裝，其中，該無核心訊號分佈結構為晶圓製造的一重新分佈結構。
  14. 根據申請專利範圍第1項的半導體封裝，其中，該至少一介電層包括一頂端介電層和一底部介電層，而在該頂端介電層和該底部介電層之間沒有較厚的一介電層。
  15. 一種製造半導體封裝的方法，該方法包括：透過在一第一電子裝置的一底部表面上所具有的一第一接合觸墊以及在該第一接合觸墊和一無核心訊號分佈結構的一頂端表面之間的一導體結構，將該第一電子裝置接合至該無核心訊號分佈結構的該頂端表面，其中該導體結構在該第一電子裝置的該底部表面和該無核心訊號分佈結構的該頂端表面之間建立一空間，其中該無核心訊號分佈結構包括至少一介電層、至少一導體層、該頂端表面、以及一底部表面；透過在一第二電子裝置的一頂端表面上所具有的一第二接合觸墊，將該第二電子裝置接合至該無核心訊號分佈結構的該底部表面；以一第一囊封劑材料囊封至少：該第一電子裝置的側表面和一頂端表面；及該無核心訊號分佈結構的該頂端表面的一部分；以及將一電氣互連電氣耦合至該無核心訊號分佈結構的該底部表面，使得該電氣互連的至少一部分在該半導體封裝的外部，並且經過配置以將該半導體封裝電氣耦合到該半導體封裝外部的一器件。
  16. 根據申請專利範圍第15項的方法，其包括將該電氣互連電氣連接到該第一電子裝置和該第二電子裝置中的一者或兩者。
  17. 根據申請專利範圍第15項的方法，其包括，以一第二囊封劑材料囊封該第二電子裝置的至少側表面，而不囊封該電氣互連的至少一部分。
  18. 根據申請專利範圍第17項的方法，其包括以該第二囊封劑材料在該第二電子裝置的該頂端表面和該無核心訊號分佈結構的該底部表面之間的該空間的至少一部分中形成一底部填充層。
  19. 根據申請專利範圍第17項的方法，其中，以該第二囊封劑材料所形成的一第二囊封劑的一底部表面的至少一部分和該第二電子裝置的一底部表面為共平面。
  20. 根據申請專利範圍第19項的方法，其包括在該無核心訊號分佈結構的該底部表面和該第二電子裝置的該頂端表面之間的該空間中形成一底部填充層。
  21. 根據申請專利範圍第20項的方法，其中，該底部填充層覆蓋該第二電子裝置的側表面的至少一部分。
  22. 根據申請專利範圍第15項的方法，其中，在該無核心訊號分佈結構中的一訊號路徑具有在實質上1μm和實質上10μm之間的一線寬度。
  23. 根據申請專利範圍第15項的方法，其進一步包含：藉由在一晶圓上形成該無核心訊號分佈結構的該至少一介電層和該至少一導體層，來晶圓製造該無核心訊號分佈結構；及在將該第一電子裝置接合至該無核心訊號分佈結構的該頂端表面之後，自該無核心訊號分佈結構移除該晶圓。
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