TWI723777B - 半導體元件之製造方法及電漿處理裝置 - Google Patents

半導體元件之製造方法及電漿處理裝置 Download PDF

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TWI723777B
TWI723777B TW109105111A TW109105111A TWI723777B TW I723777 B TWI723777 B TW I723777B TW 109105111 A TW109105111 A TW 109105111A TW 109105111 A TW109105111 A TW 109105111A TW I723777 B TWI723777 B TW I723777B
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aforementioned
sige
silicon
condition
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TW202038333A (zh
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三浦真
石井洋平
酒井哲
前田賢治
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日商日立全球先端科技股份有限公司
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Abstract

[課題] 於具有SiGe通道的半導體元件之製程，可在不對SiGe通道造成損傷之下，形成保護SiGe通道之Si偏析層。 [解決手段] 一種半導體元件之製造方法，具有：第1程序，其為對至少具有矽層與形成於矽層上的矽鍺層之半導體基板實施依第1條件之電漿處理而使矽鍺層曝露者；和第2程序，其為對半導體基板實施依第2條件之電漿處理，使矽偏析於曝露的矽鍺層的表面者；第1條件為可蝕刻矽鍺層或鄰接於矽鍺層之層的條件，第2條件為實施氫電漿處理的條件，第1程序及第2程序在相同的電漿處理裝置的處理室內連續進行。

Description

半導體元件之製造方法及電漿處理裝置
本發明涉及半導體元件之製造方法及電漿處理裝置。
要使積體電路晶片的功能及性能在無間隙下提升，不可欠缺電晶體的微細化。要實現電晶體的微細化，不僅縮小加工尺寸，正在進行與為了謀求微細化的電晶體的性能提升用的元件的構造、材料相關的各種的檢討。舉例如往金屬氧化膜半導體場效電晶體(MOSFET：Metal Oxide Semiconductor Field Effect Transistor)中的源極／汲極區域的應變的導入、高介電體閘極絕緣膜及金屬的導入、如從平面(Planar)型至鰭(Fin)型的新構造的導入等。
鰭型FET是將具有3維構造之鰭型通道的周圍以閘極覆蓋從而使閘極的控制性提升，可抑制因伴隨電晶體的微細化之閘極長的縮小所致的短通道效應(亦即，漏電流的增大)。再者，微細化進展時，預想成為一種閘極全環型FET(GAA：Gate All Around)，該閘極全環型FET是通道被作成線狀或薄片狀的層積體，其周圍被以閘極覆蓋。於如此的通道構造的變化亦會伴隨通道材料的變化。原因在於，伴隨電晶體的電源電壓(汲極電壓)的調節使得導通電流／關斷電流比減少，或伴隨由微細化帶來的接觸電阻等的寄生電阻的增大使得導通電流減少，故在低電場區域的導通電流的增大成為課題。例如，比矽(Si)載子移動度高的砷化銦鎵(InGaAs)等的III-V化合物、鍺(Ge)等的IV族半導體材料的導入被看好。尤其，矽鍺(SiGe)除電洞的移動度比Si高如此的特性以外，易於晶格匹配於Si，故可進行往SiGe通道內部的應變的導入，可期待進一步的移動度的提升。為此，鰭型FET或GAA型FET的p型通道的材料方面，期待導入SiGe。
然而，SiGe通道具有與閘極絕緣膜的界面的特性差如此的課題。SiGe表面的Ge原子的懸鍵(dangling bond)不易被由氫原子終結，故於SiGe表面存在多個懸鍵，成為載子的陷阱中心。陷阱成為漏電流的原因，同時誘發載子散射而成為載子移動度的降低主因。為此，已提出為了使SiGe通道與閘極絕緣膜的界面特性提升用的手法。
專利文獻1、非專利文獻1揭露：在SiGe通道上透過磊晶成長法形成Si保護膜(第1先前技術)。專利文獻2、非專利文獻2揭露：為了在SiGe通道上形成矽薄膜，在SiGe上形成矽氧化膜後，進行熱處理從而使在SiGe／矽氧化膜界面之Si組成增大，從而作成實質的矽薄膜(第2先前技術)。於非專利文獻3示出如下的實驗結果：對堆積於Si上之Ge表面照射原子狀氫從而予以形成Ge與H的結合，之後施加200℃～350℃程度的熱處理，使得於能量上在表面不穩定的Ge-H結合方面發生Si與Ge的置換，更穩定的Si-H結合的比例增大(第3先前技術)。 [先前技術文獻] [專利文獻]
[專利文獻1] 美國專利公開案第2016／0190286號說明書 [專利文獻2] 美國專利公開案第2018／0026100號說明書 [非專利文獻]
[非專利文獻1] G. Tsutsui et al., “Leakage aware Si/SiGe CMOS FinFET for low power applications”, Proceedings of VLSI Symposium 2018, 2018年, pp. 87～88 [非專利文獻2] P. Hashemi et al., “High Performance and Reliable StrainedSiGe PMOS FinFETs Enabled by Advanced Gate Stack Engineering”, Proceedings of IEDM 2017, 2017年, pp. 824～827 [非專利文獻3] E. Rudkevich et al., “Hydrogen Induced Si Surface Segregation on Ge-Covered Si(001)”, Physical Review Letters vol. 81, 1998年, pp. 3467～3470
[發明所欲解決之問題]
在第1先前技術，變成在磊晶成長法前需要將SiGe通道表面在氫環境中進行清潔。此程序在與進行磊晶成長之腔室相同的腔室進行，目的在於透過施加約750℃～850℃的熱處理，從而將結合於通道表面的懸鍵之雜質與氫一起除去。SiGe的熔點為約960℃，故於SiGe通道施加高的熱負載時，容易發生Ge的擴散、應變鬆弛，存在容易誘發SiGe通道的Ge組成降低、應變鬆弛所致的載子移動度的降低的課題。另外，磊晶成長的成長速度在結晶的面方位嚴重受到影響。FinFET構造的情況下，通道側壁成為成長速度慢(110)之面、通道上部成為成長速度快(100)之面，故均勻的膜厚的Si保護膜的形成困難。再者，由於產生於SiGe通道與Si保護膜之間的應變能，使得在Si保護膜成長的初始階段是原子層逐層的(layer by layer)成長困難，Si保護膜的成長應會島狀地開始。為此，要將SiGe通道表面完全以Si保護膜覆蓋則保護膜需要一定程度的膜厚。為此Si保護膜可能作動為通道，此情況下載子移動度大幅劣化。
在第2先前技術，首先將SiGe通道表面透過熱氧化或電漿氧化而氧化。於據此形成的氧化膜摻雜矽氧化膜(SiO2 )與氧化鍺膜(GeO2 )。對此氧化膜實施600℃～750℃的熱處理，使GeO2 揮發，從而可使氧化膜的組成大致上為SiO2 。於此熱處理的過程，以在SiGe通道與氧化膜的界面上Si原子與氧原子結合的狀態佔大半的方式發生Si原子與Ge原子的置換，使得於SiGe通道與氧化膜的界面形成薄的Si層。如此般，在第2先前技術，可進行比第1先前技術薄的Si保護膜形成，另外，該保護膜應依面方位之膜厚依存性亦少。然而，如同第1先前技術，留有由於熱處理因而容易誘發Ge組成降低、應變鬆弛所致的載子移動度的降低如此之課題。
發明人檢討有關以下的可能性：利用為第3先前技術之非專利文獻3的發現(Si偏析現象)，從而在不伴隨高溫的熱處理之下，在SiGe通道與閘極絕緣膜之間形成Si保護膜。此情況下，為了於蝕刻裝置將構成SiGe通道之Fin構造形成於晶圓後照射原子狀氫，需要將晶圓從蝕刻裝置取出而投入至進行氫處理的退火裝置或CVD(化學氣相沉積：Chemical Vapor Deposition)裝置。為此，在退火裝置或CVD裝置進行氫終結處理之前，需要實現雜質等未結合於通道表面的懸鍵的狀態，例如，需要透過氟化氫(HF)水溶液、氯化氫(HCl)水溶液等進行晶圓表面的濕式洗淨。然而SiGe表面的Ge原子具有的懸鍵不易進行透過濕式洗淨之氫終結，留有在洗淨後大氣中的雜質等結合於懸鍵的可能性。另外，Ge易於在大氣中被氧化，且氧化鍺膜為水溶性，故亦存在Ge-O結合的Ge原子熔化於濕式洗淨溶液之虞。發生Ge的熔化時，恐使SiGe通道寬的變動、通道的表面粗糙度增大。如此般第1～第3先前技術是為了在SiGe通道表面形成Si保護膜，皆伴隨高的熱負載或濕式洗淨所致的對於SiGe通道的損傷。
相對於此，發明人對SiGe空白樣品實施低溫氫電漿處理的結果，獲得誘發Si偏析現象而可將SiGe表面的組成改質為富Si的表面狀態如此的發現。從實驗結果發現： (1)Si偏析現象在樣品的表面附近發生； (2)離子能越大，樣品表面附近的Si／Ge比越降低； (3)離子能越大，多晶Si、SiGe的蝕刻率越降低。
本發明在於，於具有SiGe通道之鰭型FET、GAA型FET等的3維構造裝置的製程，確立可在不造成損傷之下形成保護SiGe層的Si偏析層的程序，此外提供使其為可能的電漿處理裝置。 [解決問題之技術手段]
為本發明的一態樣之半導體元件之製造方法具有：第1程序，其為對至少具有矽層與形成於矽層上的矽鍺層之半導體基板實施依第1條件之電漿處理而使矽鍺層曝露者；第2程序，其為對半導體基板實施依第2條件之電漿處理，使矽偏析於曝露的矽鍺層的表面者；第1條件為可蝕刻矽鍺層或鄰接於矽鍺層之層的條件，第2條件為實施氫電漿處理的條件，第1程序及第2程序在相同的電漿處理裝置的處理室內連續進行。
另外，為本發明的其他一態樣之電漿處理裝置為一種電漿處理裝置，其為進行對至少具有矽層與形成於矽層上之矽鍺層的半導體基板之電漿處理者，具有：處理室，其將半導體基板保持於真空環境；樣品台，其配置於處理室內，載置半導體基板；氣體供應機構，其對處理室供應電漿處理用的原料氣體；高頻電源，其用於生成為了電漿處理用的電漿；和控制部；控制部對半導體基板實施依第1條件之電漿處理而使矽鍺層曝露的第1程序、和對半導體基板實施依第2條件之電漿處理而連續進行使矽偏析於曝露的矽鍺層的表面的第2程序，氣體供應機構根據控制部的指示，於第1程序將在處理室蝕刻矽鍺層或鄰接於矽鍺層之層的原料氣體供應至處理室，於第2程序對處理室供應氫氣。 [對照先前技術之功效]
於具有SiGe通道的半導體元件之製程，可在不對SiGe通道造成損傷之下，形成保護SiGe通道之Si偏析層。
其他課題與新穎的特徵將由本說明書的記述及圖式而明朗化。
以下，根據圖式說明本發明的實施方式。另外，本發明不限於記述於以下的實施例，在該技術思想的範圍內可進行各種的變形。於用於說明實施例的全圖，對具有相同的功能之構材標注相同的符號，其重複的說明省略。另外，當然可對作為本實施例而揭露的內容進行改變材料、製程的組合等多種的變更。另外，圖式未必正確依照比例尺，而以邏輯為明確的方式強調重要的部分而示意性進行描繪。 [實施例1]
圖1中，示出實施例1的具有矽鍺(SiGe)通道之半導體元件的通道形成方法。於圖1(a)示出通道形成程序前的矽(Si)基板。於Si基板(單晶Si層)1的一部分形成溝，溝內中嵌入單晶SiGe層2。SiGe層2的膜厚期望30nm～100nm，SiGe層2內的鍺(Ge)的組成優選為20%～25%。為了實現高移動度，SiGe層2以晶格匹配的方式成膜於Si基板1，於SiGe內部含有因SiGe與Si的晶格常數的差異所致的應變能。據此，比起鬆弛的SiGe層實現高的移動度。SiGe層2例如可在透過圖案化形成溝的Si基板1上利用化學氣相沉積法(CVD：Chemical Vapor Deposition)等使SiGe膜成長後，以化學機械研磨(CMP：Chemical Mechanical Polishing)將表面平坦化而形成，亦可對用於溝形成的蝕刻時的絕緣膜遮罩使用CVD等進行選擇性磊晶成長，從而僅在溝內形成SiGe膜。
於Si基板1及SiGe層2之上部形成被圖案化的硬遮罩3。硬遮罩3具有週期性的圖案，圖案週期優選上為20nm～50nm間距。於硬遮罩3的形成，例如使用以氟化氬氣體(ArF)為光源的雷射的情況下，圖案週期為40nm以上且80nm以下時可採用自對準雙重圖案化(SADP：Self-Aligned Double Patterning)，圖案週期為20nm以上且40nm以下時可採用自對準4倍圖案化(SAQP：Self-Aligned Quadruple Patterning)。另外，進行波長13.5nm的極紫外線(EUV：Extreme Ultraviolet)曝光的情況下，至圖案週期40nm為止可採用單一曝光(Single Patterning)，圖案週期為20nm以上且40nm以下時可採用SADP。硬遮罩3為矽氧化膜(SiO2 )、矽氮化膜(Si3 N4 )、或基於其等之矽氧氮化膜(SiON)、碳氧化矽膜(SiCO)等的絕緣膜。或者，亦可為非晶質的碳化矽(SiC)等的寬帶隙材料、由其他複數個絕緣膜所成的層積膜。
將形成為圖1(a)的構造之基板導入至電漿處理裝置，以硬遮罩3為遮罩將SiGe層2與Si基板1的一部分進行蝕刻。蝕刻被依對基板表面保持垂直度的異向性蝕刻的條件而進行。據此，形成圖1(b)的fin構造。
接著，將基板保持於相同裝置的相同處理室(腔室)內，使用氫(H2 )氣體實施氫電漿處理，如示於圖1(c)般在SiGe通道表面形成極薄膜Si偏析層4。如後述般，即使透過蝕刻而除去的材料再附著於SiGe通道表面之狀態下仍可形成極薄膜Si偏析層4，故在圖1(b)的蝕刻程序與圖1(c)的Si偏析層形成程序之間不需要洗淨程序，可迴避洗淨程序所致的對於SiGe層的損傷。另外，圖1(b)～(c)的連續程序的處理溫度為大致上室溫，故可抑制Ge擴散所致的SiGe通道的組成變化、應變鬆弛所致的移動度降低。
將此連續程序中的電漿處理裝置的處理條件示於圖2。以硬遮罩3為遮罩之SiGe層2及Si基板1的蝕刻能以包含氯(Cl2 )、溴化氫(HBr)等的鹵素氣體之氣體為原料。使用如此的蝕刻氣體時，可在對SiO2 、Si3 N4 等的遮罩材料保持良好的選擇性的狀態下，進行SiGe層2及Si基板1的蝕刻。另外，為了對基板表面保持垂直度而蝕刻，對基板施加高頻偏壓。電漿內的離子被吸引至基板，從而保持垂直度而被蝕刻。另一方面，於為了形成Si偏析層4用的電漿處理，主要使用氫氣。此時，為了從fin側壁之上部至下部均勻照射電漿，設為對基板施加的高頻偏壓比起進行蝕刻之情況予以降低或不施加高頻偏壓的條件。此符合離子能越小則越可提高樣品表面附近的Si／Ge比如此的發現。然而，離子能減小同時亦伴隨Si層、SiGe層的蝕刻率提高的作用。為此，氫電漿處理設為不極力蝕刻形成於SiGe層2及Si基板1的fin的條件。例如，縮短氫電漿處理時間。如此般，以適合於蝕刻程序及偏析程序的個別的條件的方式，控制蝕刻室內的壓力、施加於基板的高頻偏壓、氣流量、處理時間如此的處理條件。
圖3中，示出就於SiGe fin形成極薄膜Si偏析層4的過程進行繪示的概念圖。為了示出對於SiGe fin之側壁的氫電漿處理效果，將相當於SiGe fin之側壁的(110)面作為SiGe層2的表面而表現。另外，於SiGe fin之側壁堆積蝕刻為fin形狀時產生的再附著物90。如示於圖3般，對SiGe層表面照射氫電漿時，氫電漿穿透再附著物層90而作用於SiGe層2，SiGe層表面的Si原子及Ge原子分別具有的懸鍵被透過氫原子終結。據此，SiGe層表面成為摻雜矽-氫(Si-H)結合與鍺-氫(Ge-H)結合的狀態。Si-H結合具有的能量是能量上比Ge-H結合穩定，故在SiGe結晶內部Si原子與Ge原子置換，Si原子偏析於SiGe層表面。相對於在非專利文獻3為了提供Si原子與Ge原子的置換所需的能量需要一定程度的熱處理，在本實施例由於為透過氫電漿處理之反應，故終結懸鍵之氫以具有高能量的分子種(自由基)的狀態與SiGe層表面反應。自由基具有的能量傳播至SiGe層表面，使得應會在SiGe表面附近發生Si原子與Ge原子的置換。尤其，透過此氫電漿處理之Si偏析層4的形成不限於表面乾淨的SiGe空白樣品，亦可對如存在再附著物層的加工中途的樣品進行，使得本實施例的連續程序成為可能。另外，使電漿處理裝置的腔室內溫度為室溫(27℃附近，最高100℃以下)，使得氫原子的解吸現象不會發生。
氫電漿反應為在SiGe層表面發生的反應，故Si偏析反應以不足1秒的極短時間完成，之後即使進行氫照射，反應仍不會朝SiGe層的深度方向繼續下去。形成的極薄膜Si偏析層的厚度亦不會依存於氫自由基的往SiGe層的侵入長而發生變動。反言之，氫電漿處理的過量的處理時間、往SiGe結晶內的氫自由基的過量的侵入長存在由於氫自由基而對SiGe通道造成損傷之虞，故需要以不會對SiGe通道造成過度的損傷的方式進行處理時間、基板偏壓等的電漿處理條件的調整。氫電漿處理時間之例方面，可調整為數秒～20秒以下的範圍。在迄今為止的檢討結果，獲悉因Si偏析現象而形成的Si偏析層的厚度不足1nm，引起Si偏析現象所需的氫的侵入長為數nm。
以上說明的Si偏析效果是以一定程度寬範圍的氫電漿條件而發現的現象，電漿處理裝置方面，使用感應耦合電漿(ICP：Inductively Coupled Plasma)的蝕刻裝置、使用電容耦合電漿(CCP：Capacitively Coupled Plasma)的蝕刻裝置、使用微波電子迴旋諧振(ECR：Electron Cyclotron Resonance)電漿的蝕刻裝置中任一者皆可使用。此處，說明使用微波ECR電漿的電漿處理裝置之例。於以下的實施例亦可使用此等電漿處理裝置而製造半導體裝置。
於圖4，示出使用微波ECR電漿之電漿處理裝置的構成。電漿處理裝置具有處理室(腔室)401，處理室401經由真空排氣口402連接於真空排氣裝置(未圖示)，於電漿處理中處理室401內被保持為0.1Pa～10Pa程度的真空。另外，於處理室401之上部，配置噴灑板403及窗部404。噴灑板403具有複數個孔，材質為例如石英。氣體供應機構具有氣源405、氣體供應裝置406、氣體導入口407，供應電漿處理用的原料氣體。氣源405至少具有fin構造的蝕刻所需的氣體種類(例如，以鹵素氣體為主之單一或複數個氣體種類)與引起Si偏析所需的氫氣。氣體供應裝置406具有控制氣體的供應／遮斷之控制閥與控制氣流量之質流控制器。另外，氣體導入口407設於噴灑板403與窗部404之間，將電漿蝕刻或氫電漿處理用的氣體通過噴灑板403的孔導入至處理室401內。窗部404扮演使從處理室上方的電磁波透過，同時將處理室上方氣密地密封之角色。窗部404的材質方面，採用介電體例如石英。
於處理室401之上部連接傳播電磁波之導波管409，於導波管409的端部連接作為高頻電源之電漿生成用高頻電源408。電漿生成用高頻電源408是為了產生電漿生成用的電磁波用的電源，例如電磁波方面使用頻率2.45GHz的微波。從電漿生成用高頻電源408產生的微波在導波管409傳播，入射至處理室401內。導波管409具有延伸於垂直方向的垂直導波管與兼具將微波的方向彎曲90度的角落之導波管變換器，使得微波垂直入射於處理室401。微波經由窗部404、噴灑板403而在處理室401內垂直傳播。配置於處理室401的外周之磁場產生線圈410在處理室401形成磁場。從電漿生成用高頻電源408發振的微波由於與透過磁場產生線圈410形成的磁場的相互作用，因而在處理室401內生成高密度電漿。
在處理室401的下方，與窗部404相向而配置樣品台412。樣品台412的材質方面，採用鋁、鈦。樣品台412於上表面載置並保持作為樣品之半導體基板411。於此，導波管409、處理室401、樣品台412及半導體基板411之中心軸一致。另外，於樣品台412內部設置為了將半導體基板411進行靜電吸附用的電極，施加直流電壓使得半導體基板411靜電吸附於樣品台412。再者，對樣品台412，從高頻偏壓電源413施加高頻電壓。施加的高頻偏壓的頻率可設為例如400kHz。
電漿處理裝置的各機構由控制部420控制(圖4中與各機構的連接省略)。控制部420依電漿處理裝置執行的處理條件，對各機構指示既定的動作的執行，從而控制各機構。例如，控制電漿生成用高頻電源408，控制為了電漿產生用的電磁波的ON-OFF。另外，控制氣體供應機構，調整導入至處理室401的氣體的種類、流量等。另外，控制高頻偏壓電源413，控制施加於樣品台412上的半導體基板411的高頻電壓的強度。
微波ECR電漿處理裝置具有電漿處理時的壓力比ICP電漿處理裝置、CCP電漿處理裝置低如此之特徵。進行在壓力低的區域的電漿處理，使得亦可獲得於一連串的電漿處理程序抑制往SiGe層表面的雜質的堆積、電漿處理所致的往SiGe層表面的損傷之功效。
以下，就製造具有圖1(c)的fin構造之MOSFET(鰭型FET)之程序進行說明。圖5A為就圖1(c)的fin構造形成於Si基板1上的狀態進行繪示的俯視圖。此處，示出具有p型MOSFET與n型MOSFET的互補型MOSFET(CMOS：Complementary MOSFET)之例。p型MOSFET以SiGe的fin構造為通道，n型MOSFET以Si的fin構造為通道。另外，此例中雖示出p型MOSFET及n型MOSFET皆為每一個電晶體具有2個fin之例，惟fin的個數不限定。另外，fin構造的最小間隔如前述般設為20nm～50nm的範圍，fin的寬在5nm～20nm的範圍內進行調整。作動為通道的fin區域的高度(相當於SiGe層2的膜厚)如前述般在30nm～100nm的範圍內界定，另一方面如示於圖5A，fin的高度為約100nm～200nm，在作動為通道之fin區域的下部形成為了抑制電晶體的漏電流用的井(WELL)區域。在n型MOSFET形成摻雜為p型的井區，在p型MOSFET形成摻雜為n型的井區。此等井區可例如透過離子植入而形成。
例如，在比形成圖1(a)的構造之前，首先對Si基板1，n型的摻雜時進行燐(P)或砷(As)的離子植入，p型的摻雜時進行硼(B)或氟化硼(BF2 )的離子植入。離子植入後進行為了雜質的活性化用的熱處理，透過磊晶成長以30nm～100nm的厚度形成不進行摻雜的通道部分。之後，如於圖1說明般形成嵌入之SiGe層2，形成fin構造。另外，井摻雜是亦可利用固相沉積、電漿摻雜進行，進行固相沉積的情況下，在fin構造形成後可進行井區的形成。
接著，為了形成元件分離區域，堆積STI (Shallow Trench Isolation)絕緣膜，進行STI絕緣膜的回蝕從而獲得圖5B的構造。STI絕緣膜5是使用CVD等而形成。STI絕緣膜5的材料可為SiO2 或基於其之SiON、SiCO等。最初堆積的STI絕緣膜5的厚度設為fin整體的高度與fin上部的硬遮罩3的合計高度以上。之後，實施以硬遮罩3之上部為阻擋層的CMP，在平坦化之後以乾式蝕刻進行回蝕而使作動為通道的fin區域曝露，從而獲得圖5B的構造。回蝕的深度雖調整為因應於MOSFET的通道的fin區域的30nm～100nm，惟可調整為回蝕後的STI絕緣膜5之上表面為與SiGe通道2的底面相同或稍低的位置。原因在於，在比STI絕緣膜5之上表面低的位置殘存電流容易流動的SiGe層時，成為使MOSFET的漏電流增大的原因。
STI絕緣膜5的材料方面使用SiO2 的情況下，於回蝕可使用四氟甲烷(CF4 )、三氟甲烷(CHF3 )作為蝕刻氣體。另外，以STI絕緣膜5的材料為SiO2 的情況下，需要對fin上部的硬遮罩3選擇性進行STI絕緣膜5的回蝕，故使硬遮罩3的材料為SiO2 以外的材料例如Si3 N4 等為優選。另外，如前述般在fin構造形成後形成井區的情況下，最初使STI絕緣膜5堆積之際，於形成井區的範圍堆積摻雜個別的雜質的絕緣膜，回蝕後實施熱處理從而使雜質擴散至作動為通道的fin區域的下部(固相沉積)而可進行井摻雜。
另外，亦可在STI絕緣膜5的回蝕後再度進行氫電漿處理，在SiGe層表面形成Si偏析層。此目的在於，於STI絕緣膜5的回蝕的程序恐極薄膜Si偏析層4受到損傷，因而使受到損傷的極薄膜Si偏析層4恢復。Si偏析反應為在SiGe層表面的反應，故即使重複進行仍可形成均勻的厚度的極薄膜Si偏析層4。
接著，透過CVD等堆積假閘極絕緣膜6、假閘極7、及硬遮罩8，對硬遮罩8進行圖案化而進行蝕刻加工後，以圖案化的硬遮罩8為遮罩而進行假閘極7的蝕刻，從而獲得圖5C的構造。假閘極絕緣膜6可為SiO2 或基於其之絕緣膜，膜厚優選上為1nm～3nm的範圍。另外，可使用熱氧化法、電漿氧化法將Si fin及SiGe fin氧化而形成假閘極絕緣膜6。假閘極7能以非晶(amorphous)Si或多晶(poly)Si形成。硬遮罩8採Si3 N4 或SiO2 或基於其之SiON等的絕緣膜。硬遮罩8的圖案化是依閘極之間距酌情使用SADP、單一曝光等的手法從而進行。例如，將閘極間矩設定為40nm～70nm，將假閘極7的寬設定為15nm～30nm的範圍，將硬遮罩8圖案化。硬遮罩8的蝕刻在例如硬遮罩8的材料方面採用Si3 N4 的情況下對CF4 與氧的混合氣體添加Cl2 等從而可保持高的與基底的假閘極7的選擇比。接續的假閘極7的蝕刻方面，使用Cl2 或HBr等的鹵素系的氣體使得可進行以基底的假閘極絕緣膜6為阻擋層之選擇性蝕刻。另外，在實施例1，在保留fin上部的硬遮罩3之下進行假閘極7的堆積及加工。於此構造，在假閘極7的蝕刻時硬遮罩3成為fin通道的保護膜，具有對於通道的蝕刻損傷被減輕如此之優點。
假閘極7的加工後，以CVD等堆積閘極側壁絕緣膜9，對閘極側壁絕緣膜9實施異向性蝕刻從而獲得示於圖5D的構造。閘極側壁絕緣膜9可採用為低比誘電率膜之SiON膜、於SiON含碳的SiOCN膜、或含碳氧化矽膜(SiCO)。於閘極側壁絕緣膜9使用SiCO膜的情況下，閘極側壁絕緣膜9的異向性蝕刻可例如以對CF4 與八氟環丁烷(C4 F8 )添加氮(N2 )氣體的混合氣體為蝕刻氣體。閘極側壁絕緣膜9的水平方向的膜厚在5nm～15nm的範圍進行調整。
接著，以覆蓋n型MOSFET區域的方式進行硬遮罩10的堆積與圖案化，以硬遮罩10為遮罩之蝕刻下，將在p型MOSFET的源極／汲極區域之假閘極絕緣膜6、fin上硬遮罩3及SiGe層2蝕刻除去，獲得圖5E的構造。於此，假閘極絕緣膜6、fin上硬遮罩3及SiGe層2的蝕刻採對基板表面保持垂直度的異向性蝕刻，以僅就作為蝕刻對象之材料進行蝕刻的選擇性蝕刻的條件進行。硬遮罩10的材料方面採用SiO2 或基於其之絕緣膜。
在p型MOSFET的源極／汲極區域的此等膜被除去，使得在閘極側壁絕緣膜9之側壁，SiGe層(通道)2之側壁曝露，於STI絕緣膜5表面上，形成fin構造之Si層或SiGe層長條狀地曝露。曝露於STI絕緣膜5表面上的fin表面為Si層或SiGe層是依存於蝕刻深度，此蝕刻深度可依電晶體性能進行調整。例如，可將以STI絕緣膜5表面為基準而曝露的fin表面的高度調整至±20nm程度。相對於fin之蝕刻深度深的情況下一方面電晶體的導通電流增大，另一方面短通道效應增大。相對於此之對於fin之蝕刻深度淺的情況下一方面短通道效應被抑制，另一方面導通電流降低。
接著，按fin，以覆蓋在STI絕緣膜5表面上曝露的fin表面與在閘極側壁絕緣膜9之側壁曝露的SiGe層2的方式，將p型SiGe源極／汲極11對周圍的絕緣膜選擇性予以磊晶成長而獲得示於圖5F的構造。磊晶成長能以CVD裝置進行，例如原料氣體方面採用氫稀釋的甲矽烷(SiH4 )、二矽烷(Si2 H6 )、鍺(GeH4 )，摻雜氣體方面採用氫稀釋的乙硼烷(B2 H6 )。另外，成長是在氫氣環境下進行，為了使選擇性提升，依所需而添加氯化氫氣體(HCl)。
接著亦對n型MOSFET區域進行在圖5E～F說明的在p型MOSFET區域的源極／汲極區域之層積體的蝕刻及透過磊晶成長之源極／汲極形成。此情況下，亦同樣地以硬遮罩覆蓋p型MOSFET區域，將在n型MOSFET的源極／汲極區域的硬遮罩3及Si fin蝕刻除去，將n型Si源極／汲極對於周圍的絕緣膜選擇性地予以磊晶成長。磊晶成長能以CVD裝置進行，例如原料氣體方面採用氫稀釋的SiH4 或Si2 H6 ，摻雜氣體方面採用氫稀釋的磷化氫(PH3 )或砷化氫(AsH3 )。另外，成長是在氫氣環境下進行，為了使選擇性提升，依所需而添加HCl。
接著，以填埋源極／汲極區域的方式堆積層間絕緣膜12，以CMP將表面平坦化後，將假閘極7上的硬遮罩8、假閘極7及假閘極絕緣膜6依序蝕刻除去而獲得圖5G的構造。於此，假閘極7上的硬遮罩8、假閘極7、假閘極絕緣膜6個別的蝕刻條件是以因應於迄今敘述的個別的材料的選擇性蝕刻條件進行。在假閘極7及假閘極絕緣膜6的蝕刻時fin上的硬遮罩3作動為fin通道的保護膜。
接著，在圖5G的構造上堆積閘極絕緣膜13、n型功函數調整用金屬(WFM：Work function metal)14或p型WFM15，進一步堆積閘極金屬16後，透過CMP將表面平坦化而獲得示於圖5H的構造。n型WFM14及p型WFM15分別形成為n型MOSFET區域及p型MOSFET區域。此WFM的分離例如可如以下般進行。首先形成n型WFM14後實施遮罩圖案化而將p型MOSFET區域的n型WFM14除去。之後，在整面形成p型WFM15後實施遮罩圖案，除去n型MOSFET區域的p型WFM15。於WFM的蝕刻時，形成於fin上的硬遮罩3亦作動為fin通道的保護膜。
閘極絕緣膜13在提高透過閘極之電晶體動作控制性之目的下，可為氧化鉿(HfO2 )、氧化鋁(Al2 O3 )等的高介電體材料、此等高介電體材料的層積膜。另外，對高介電體材料添加鋯(Zr)、鑭(La)、或釔(Y)等的金屬材料亦對於閘極絕緣膜的特性改善有效。再者，在閘極絕緣膜13的形成前可透過熱氧化或電漿氧化在fin通道的Si表面形成薄的氧化膜(SiO2 )。在高介電體材料與Si通道或具Si偏析層的SiGe通道的界面使極薄(約1nm以下)的SiO2 膜介於之間使得可達成界面特性的進一步的提升。
在圖5H的構造上形成金屬配線，與閘極及源極／汲極連接，使得可形成具有CMOS電晶體的邏輯積體電路。
將垂直於在圖5H的構造下的fin的剖面示於圖6。此處，單純化而僅就n型MOSFET與p型MOSFET的各者示出1個fin。SiGe通道2與閘極絕緣膜13由Si偏析層4隔開，抑制漏電流的產生及誘發載子陷阱的SiGe／閘極絕緣膜界面的形成。
將Si偏析層4對電晶體特性造成的功效示於圖7。圖7為示出在具有SiGe通道的finFET之通道與閘極的界面附近的層積膜、和對應於其之能帶構造及通道中的Si、Ge組成者。圖7中的能帶構造圖示出p型MOSFET為導通的狀態，亦即示出對p型WFM15施加負的電壓的狀態，隨此在閘極絕緣膜13附近的SiGe通道2及Si偏析層4產生能帶的彎曲。如圖示，此能帶的彎曲，使得為載子之電洞70累積於SiGe通道2與Si偏析層4的界面附近。於此，Si偏析層4是帶隙比SiGe通道2寬，於價帶在SiGe通道2之間具有20meV程度的能帶不連續(偏移)。此能帶偏移扮演將電洞70從SiGe通道2與閘極絕緣膜13的界面分離的角色。據此，可進一步抑制對於通道／閘極絕緣膜界面的電晶體特性的影響。另外，在本實施例可將Si偏析層4的厚度抑制至不足約1nm，故Si偏析層4由於該薄度而僅具有作為屏障膜的角色，迴避電洞進入至Si偏析層4中使得Si偏析層4本身作用為通道。此外，Si偏析現象由於在SiGe層之Si原子與Ge原子的置換而形成，故在SiGe通道2與Si偏析層4的界面附近，預想由於置換現象的影響致使Ge組成局部增大。於SiGe通道2的累積電洞70的區域，成為比通道內部的Ge組成高的Ge組成，因而可期待移動度的進一步的提升。
如此般，以在相同裝置之連續處理進行具有fin構造之通道的加工與往SiGe通道表面的極薄膜Si偏析層的形成，使得可在不對SiGe通道造成損傷之下，形成良好的通道／閘極絕緣膜界面。據此，可製作同時抑制因通道／閘極絕緣膜界面狀態而發生的關斷電流的增大、導通電流的劣化，且可同時實現高導通電流與低關斷電流的半導體元件。 [實施例2]
以下，雖就實施例2的具有矽鍺(SiGe)通道之半導體元件、其製造方法進行說明，惟以與實施例1的差異為中心進行說明，重複的說明方面省略。於圖8，示出實施例2的半導體元件的通道形成方法。與實施例1的程序是Si偏析層的形成時點不同。圖8(a)為在形成圖1(b)的fin構造後，在不對SiGe通道予以形成Si偏析層之下，堆積STI絕緣膜，之後以CMP進行平坦化而獲得的構造的剖面圖。於Si基板501的n型MOSFET區域形成Si fin，於p型MOSFET區域形成Si fin之上部區域從Si層置換為SiGe層502的fin(SiGe fin)。此fin構造與成為就fin構造進行蝕刻加工時的遮罩之硬遮罩503被由STI絕緣膜504覆蓋。以圖8(a)的構造為起點而蝕刻硬遮罩503，連續將STI絕緣膜504透過異向性蝕刻進行回蝕而形成元件分離區域，獲得圖8(b)的構造。此處，雖示出蝕刻後的STI絕緣膜504的表面比SiGe通道502的底面低數nm程度之例，惟亦可為相同的高度。連續於此蝕刻程序，在進行蝕刻的電漿裝置的相同腔室內進行氫電漿處理，予以誘發Si偏析現象，在SiGe通道502的表面形成極薄膜Si偏析層505而獲得圖8(c)的構造。
在實施例2，fin上部的硬遮罩503被除去，使得在電晶體完成時從fin型通道之側壁至上部為止被閘極覆蓋。據此，可達成比實施例1的構造強的閘極的控制性。
將此連續程序中的電漿處理裝置的處理條件示於圖9。硬遮罩503的蝕刻是依其材料選擇可對於STI絕緣膜504、Si fin表面及SiGe fin表面保持高的選擇性而蝕刻的氣體。例如，硬遮罩503的材料方面採用Si3 N4 的情況下對CF4 等的氟碳氣體系與氧的混合氣體添加Cl2 等使得可保持高的對於其他材料之蝕刻選擇比。於接著的STI絕緣膜504的蝕刻，例如STI絕緣膜504的材料方面使用SiO2 的情況下採用CF4 或CHF3 等的氟碳系氣體時，可進行對於Si fin及SiGe fin保持高的選擇比的蝕刻。硬遮罩503及STI絕緣膜504的蝕刻為基於異向性蝕刻之蝕刻，設為將一定程度的高頻偏壓對基板對施加的條件。另一方面，STI絕緣膜504的回蝕後的H2 電漿處理如同實施例1，設為對基板施加的高頻偏壓比起進行蝕刻之情況予以降低或不施加高頻偏壓的條件。
另外，於圖8雖示出對SiGe通道502在不予以形成極薄膜Si偏析層505之下堆積STI絕緣膜504之例，惟亦可如同實施例1般在對SiGe通道502予以形成極薄膜Si偏析層505而形成圖1(c)的構造後，予以堆積如示於圖8(a)的STI絕緣膜504。此情況下，將STI絕緣膜504透過異向性蝕刻而回蝕後，再度在SiGe通道形成極薄膜Si偏析層505。原因在於，在實施例2為了除去硬遮罩503將使得SiGe層502於SiGe fin之上部曝露。為此，需要至少2次的極薄膜Si偏析層形成程序。
將在實施例2的半導體元件之垂直於fin的剖面示於圖10。於fin構造之上，堆積閘極絕緣膜506、n型WFM507或p型WFM508、閘極金屬509。分別n型WFM507形成於n型MOSFET區域，p型WFM508形成於p型MOSFET區域。示於圖10的MOSFET是可對於示於圖8(c)的構造，實施作為實施例1而說明的示於圖5C～H的程序從而獲得。
於實施例2，在SiGe fin 502曝露後實施氫電漿處理，使得SiGe fin 502之側壁及上部皆被以均勻的厚度的極薄膜Si偏析層505覆蓋。在本實施例之Si偏析效果為僅在表面附近產生的現象，故Si偏析層505的厚度不依存於電漿處理時間，大致上為一定。相同的理由下，對於fin構造之STI絕緣膜504的堆積的前後2次予以形成Si偏析層的情況亦同樣地，SiGe fin 502之側壁及上部皆形成均勻的厚度的極薄膜Si偏析層505。
如上述般，示於圖10的MOSFET是fin型通道之側壁及上部皆被以閘極覆蓋，故可獲得閘極控制性比實施例1的MOSFET優異的MOSFET特性。 [實施例3]
以下，雖就實施例3的具有矽鍺(SiGe)通道之半導體元件、其製造方法進行說明，惟以與實施例1或實施例2的差異為中心進行說明，重複的說明方面省略。於圖11，示出實施例3的半導體元件的通道形成方法。與實施例1、2的程序是Si偏析層的形成時點不同。圖11(a)示出對實施例2的圖8(B)的構造(在Si基板601上形成Si fin與具有SiGe層602之SiGe fin)堆積使用實施例1的圖5C進行說明的假閘極絕緣膜604、假閘極605、硬遮罩606的狀態。
相當於實施例1的圖5C～F之程序後，執行相當於圖5G之程序。將圖11(a)的構造導入至電漿處理裝置，將硬遮罩606及假閘極605蝕刻除去，獲得圖11(b)的構造。連續而在相同裝置的相同腔室內將假閘極絕緣膜604蝕刻除去，獲得圖11(c)的構造。連續而在相同裝置的相同腔室內進行氫電漿處理，誘發Si偏析現象從而在SiGe通道602表面形成極薄膜Si偏析層607，獲得圖11(d)的構造。在實施例3，緊接著在MOSFET的閘極絕緣膜形成(實施例1的圖5H相當的程序)之前將Si偏析層607形成於SiGe通道602上，使得可將電晶體製程對於SiGe通道上的Si偏析層造成的損傷比實施例1、2減輕。其中，如上述般，於實施例1、2，皆重複氫電漿處理，使得可使Si偏析層恢復。
將在圖11的連續程序之電漿處理裝置的處理條件示於圖12。假閘極上硬遮罩606的蝕刻是依硬遮罩材料及周邊材料，選擇蝕刻氣體。亦即，硬遮罩606的材料方面採用Si3 N4 的情況下將CF4 等的氟碳系氣體與氧的混合氣體添加至Cl2 等使得可進行將對於其他材料之蝕刻選擇比保持為高的蝕刻。於假閘極605的蝕刻，採用Cl2 或HBr等的鹵素系的氣體使得可進行以基底的假閘極絕緣膜604為阻擋層之非晶質Si或多晶Si的選擇性蝕刻。於接著進行的假閘極絕緣膜604蝕刻，採用CF4 或CHF3 等的氟碳系氣體。硬遮罩606、假閘極605及假閘極絕緣膜604的連續蝕刻要求一定程度的垂直度，故將必要的高頻偏壓施加於基板。另一方面，氫電漿處理目的在於均勻地形成極薄膜Si偏析層607，故如同實施例1、2，設為對基板施加的高頻偏壓比起進行蝕刻之情況予以降低或不施加高頻偏壓的條件。
實施例3的MOSFET構造與實施例2大致上同等，垂直於在閘極部分之fin的剖面與圖10相同。 [實施例4]
實施例4的具有矽鍺(SiGe)通道之半導體元件具有通道的周圍全被以閘極覆蓋的閘極全環構造(GAA型FET)。於以下的說明，亦以與實施例1～3的差異為中心進行說明，重複的說明方面省略。於圖13A，示出將由Si基板701、形成於Si基板701上之單晶Si或應變鬆弛的單晶SiGe之磊晶成長層702及交互層積的複數個單晶Si層703與複數個單晶SiGe層704所成的層積膜加工為fin狀，形成STI絕緣膜705的構造。
於圖13A的構造，Si層或應變鬆弛SiGe層702、將Si層703與SiGe層704交互層積的層積膜是在Si基板701上連續而透過依CVD等之磊晶成長而形成。fin構造的加工程序及STI絕緣膜705的形成程序與其他實施例相同。使磊晶成長層702為Si層的情況下，Si層703未含有應變，僅SiGe層704含有壓縮性的應變。此情況下，SiGe層704的Ge組成以20%～25%的範圍進行調整為優選。另一方面，使磊晶成長層702為應變鬆弛SiGe層的情況下，於Si層703被施加拉伸應變。於SiGe層704被施加壓縮性的應變為優選，故SiGe層704優選上具有比應變鬆弛SiGe層702高的Ge組成。例如，可將應變鬆弛SiGe層702的Ge組成以20%～25%的範圍進行調整，將含有應變的SiGe層704的Ge組成以約30%～60%的範圍進行調整。施加有拉伸應變時，在n型MOSFET之電子的移動度提升，施加有壓縮應變時在p型MOSFET之電洞的移動度提升。因此，使磊晶成長層702為應變鬆弛SiGe層的情況下，比起為Si層的情況更可期待n型MOSFET的特性提升。
另外，使磊晶成長層702為應變鬆弛SiGe層的情況下，需要使磊晶成長之際的SiGe層的膜厚為應變會鬆弛的臨界膜厚以上，故需要抑制因應變鬆弛而發生的缺陷的影響。例如可在磊晶成長中使Ge組成逐漸增加，將緩衝層以低溫形成。另一方面，於應變SiGe層704的膜厚及磊晶成長層702採用應變鬆弛SiGe層的情況下的應變Si層703的膜厚為應變鬆弛的臨界膜厚以下。另外，Si層703與SiGe層704的膜厚是鑒於電晶體特性的設計亦為重要，例如閘極長為15nm～30nm的情況下，可將Si層703與SiGe層704的膜厚設計為5nm～20nm程度。
對示於圖13A的構造，實施相當於實施例1的圖5B～F的程序，獲得圖13B的構造。於圖14，示出從上方視看圖13B的構造時的平面圖。在形成為Si層703與SiGe層704的層積膜的fin構造上，形成假閘極絕緣膜706、假閘極707、硬遮罩708，於假閘極707側壁形成假閘極側壁絕緣膜709。另外，於n型MOSFET的源極／汲極區域形成磊晶成長的n型Si的源極／汲極713，於p型MOSFET的源極／汲極區域形成磊晶成長的p型SiGe的源極／汲極710。
之後，於整面堆積層間絕緣膜711後進行透過CMP之平坦化，透過圖案化的抗蝕層712將p型MOSFET區域覆蓋從而獲得示於圖13C的構造。就圖13C的構造，將連結圖14的a-a’的線上之垂直於n型MOSFET的閘極的剖面示於圖15A。於圖15A，垂直於閘極的剖面上的Si層703與SiGe層704的層積膜之側壁被由n型Si源極／汲極713覆蓋。
接著，實施以抗蝕層712為遮罩之蝕刻，將假閘極上硬遮罩708、假閘極707、及假閘極絕緣膜706依序蝕刻除去，獲得圖13D的構造。透過此蝕刻，於n型MOSFET的閘極形成區域，Si層703與SiGe層704的層積膜的fin構造曝露。就圖13D的構造，將連結圖14的a-a’的線上之垂直於n型MOSFET的閘極的剖面示於圖15B。
從示於圖13D及圖15B的在n型MOSFET區域的fin構造，將SiGe層704相對於Si層703及其他層選擇性進行蝕刻除去，獲得圖13E及圖15C的構造。SiGe層704的選擇性蝕刻可透過使用例如乙酸(CH3 COOH)與過氧化氫水(H2 O2 )及氫氟酸(HF)等酸性的混合液的濕式蝕刻而進行，亦可透過一氟化氯(ClF)、一溴化碘(IBr)、三氟化氯(ClF3 )、使用三氟化溴(BrF3 )等的鹵化物之乾式蝕刻而進行。透過此蝕刻，Si層703被加工為細線(nanowire)狀或薄片(nanosheet)狀的通道。
接著，將抗蝕層712除去後，以抗蝕層714覆蓋n型MOSFET區域，獲得圖13F的構造。於此，抗蝕層714可為由旋塗碳膜／旋塗玻璃膜／有機抗蝕層所成的三層抗蝕層。於此，旋塗碳膜為主要由所成的有機膜，旋塗玻璃膜為包含Si、氧的有機膜。一般而言，在採用三層抗蝕層的加工，使用抗蝕層而蝕刻旋塗玻璃膜，以旋塗玻璃膜為遮罩而蝕刻旋塗碳膜後，將抗蝕層及旋塗玻璃膜除去而將旋塗碳膜用作為遮罩的情況多，此情況下變成抗蝕層714主要由旋塗碳膜構成。就圖13F的構造，將連結圖14的b-b’的線上之垂直於p型MOSFET的閘極的剖面示於圖16A。於圖16A，垂直於閘極的剖面上的Si層703與SiGe層704的層積膜之側壁被由p型SiGe源極／汲極710覆蓋。
接著，實施以抗蝕層714為遮罩之蝕刻，將假閘極上硬遮罩708、假閘極707、及假閘極絕緣膜706依序蝕刻除去，獲得圖13G的構造。透過此蝕刻，於p型MOSFET的閘極形成區域，Si層703與SiGe層704的層積膜的fin構造曝露。就圖13G的構造，將連結圖14的b-b’的線上之垂直於p型MOSFET的閘極的剖面示於圖16B。
從示於圖13G及圖16B的在p型MOSFET區域的fin構造，將Si層703相對於SiGe層704及其他層選擇性進行蝕刻除去，獲得圖13H及圖16C的構造。此蝕刻連續於假閘極707等的蝕刻除去而於相同的腔室內進行。透過此蝕刻，SiGe層704被加工為細線(nanowire)狀或薄片(nanosheet)狀的通道。於此狀態，SiGe層704的表面及閘極側壁絕緣膜709內的p型SiGe源極／汲極710曝露。
Si層703的選擇性蝕刻後，在相同腔室內連續進行H2 電漿處理而誘發Si偏析現象，在曝露的SiGe層704及p型SiGe源極／汲極710的表面形成極薄膜Si偏析層715，獲得圖13I及圖16D的構造。
將從示於圖13G的假閘極除去程序至示於圖13I的透過氫電漿處理之Si偏析程序為止在相同腔室內以一貫處理而進行，使得成為可同時實現程序數的削減與通道-閘極間的界面特性的提升。將在此一貫處理的電漿處理裝置的處理條件示於圖18。
假閘極上硬遮罩708的蝕刻是依硬遮罩材料及周邊材料，選擇蝕刻氣體。亦即，硬遮罩708的材料方面採用Si3 N4 的情況下將CF4 等的氟碳系氣體與氧的混合氣體添加至Cl2 等使得可進行將對於其他材料之蝕刻選擇比保持為高的蝕刻。於假閘極707的蝕刻時採用Cl2 或HBr等的鹵素系的氣體，使得可進行以基底的假閘極絕緣膜706為阻擋層之非晶質Si或多晶Si的選擇性蝕刻。於接著進行的假閘極絕緣膜706蝕刻時，採用CF4 或CHF3 等的氟碳系氣體。硬遮罩708、假閘極707及假閘極絕緣膜706的連續蝕刻要求一定程度的垂直度，故將必要的高頻偏壓施加於基板。接著，在進行Si層703的選擇性蝕刻之際，要求各向等性的蝕刻，故設為對基板施加的高頻偏壓比起進行假閘極707等的蝕刻的情況予以降低或不施加高頻偏壓的條件。用於選擇性蝕刻的電漿的原料氣體除H2 以外，例如可採用六氟化硫(SF6 )或氟碳系氣體。接著誘發Si偏析的H2 電漿處理主要採用H2 氣體，如同Si層703選擇性蝕刻時，設為對基板施加的高頻偏壓比起進行假閘極707等的蝕刻的情況予以降低或不施加高頻偏壓的條件。
於圖13I及圖16D的構造堆積閘極絕緣膜716、n型WFM717或p型WFM718，進一步堆積閘極金屬719後，透過CMP將表面平坦化而獲得圖13J及圖16E的構造。n型WFM717及p型WFM718分別形成於n型MOSFET區域及p型MOSFET區域。閘極層積膜的形成方法與在實施例1示出的方法同等。
就實施例4的MOSFET構造，將連結圖14的c-c’的線上的剖面示於圖17。具有Si奈米線(或奈米片)通道703及SiGe奈米線(或奈米片)通道704的周圍被以閘極覆蓋的閘極全環構造，比起具有finFET構造的MOSFET，可進行閘極控制性更優異的電晶體的製作。另外，於閘極全環型MOSFET，SiGe通道704的表面被以極薄膜Si偏析層715保護，同時抑制因通道／閘極絕緣膜界面狀態而發生的電晶體關斷電流的增大、導通電流的劣化，可製作可同時實現高導通電流與低關斷電流的半導體元件。
1,501,601,701:矽基板(單晶矽層) 2,502,602:單晶應變矽鍺層 3,503:硬遮罩 4,505,607,715:矽偏析層 5,504,603,705:元件分離(STI)絕緣膜 6,604,706:假閘極絕緣膜 7,605,707:假閘極 8,606,708:硬遮罩 9,709:閘極側壁絕緣膜 10:硬遮罩 11,710:p型矽鍺源／汲極 12,711:層間絕緣膜 13,506,716:閘極絕緣膜 14,507,717:n型功函數調整用金屬 15,508,718:p型功函數調整用金屬 16,509,719:閘極金屬 70:電洞 90:再附著物層 702:應變鬆弛單晶矽鍺層或應變鬆弛單晶矽層 703:單晶應變矽或單晶矽層 704:單晶應變矽鍺層 712:抗蝕層 713:n型矽源／汲極 714:抗蝕層 401:處理室(腔室) 402:真空排氣口 403:噴灑板 404:窗部 405:氣源 406:氣體供應裝置 407:氣體導入口 408:電漿生成用高頻電源 409:導波管 410:磁場產生線圈 411:半導體基板 412:樣品台 413:高頻偏壓電源 420:控制部
[圖1]就實施例1的具有SiGe通道之半導體元件的通道形成方法進行繪示的圖。 [圖2]就實施例1中的電漿處理裝置的處理條件進行繪示的圖。 [圖3]就極薄膜Si偏析層的形成過程進行繪示的概念圖。 [圖4]使用微波ECR電漿之電漿處理裝置的構成圖。 [圖5A]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5B]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5C]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5D]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5E]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5F]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5G]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖5H]就實施例1的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖6]實施例1的具有SiGe通道之半導體元件的剖面圖。 [圖7]為了說明Si偏析層對電晶體特性帶來的功效用的圖。 [圖8]就實施例2的具有SiGe通道之半導體元件的通道形成方法進行繪示的圖。 [圖9]就實施例2中的電漿處理裝置的處理條件進行繪示的圖。 [圖10]實施例2的具有SiGe通道之半導體元件的剖面圖。 [圖11]就實施例3的具有SiGe通道之半導體元件的通道形成方法進行繪示的圖。 [圖12]就實施例3中的電漿處理裝置的處理條件進行繪示的圖。 [圖13A]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13B]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13C]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13D]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13E]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13F]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13G]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13H]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13I]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖13J]就實施例4的具有SiGe通道之半導體元件之製程進行繪示的俯視圖。 [圖14]從上方視看圖13B的構造時的平面圖。 [圖15A]就實施例4的n型MOSFET的製程進行繪示的剖面圖。 [圖15B]就實施例4的n型MOSFET的製程進行繪示的剖面圖。 [圖15C]就實施例4的n型MOSFET的製程進行繪示的剖面圖。 [圖16A]就實施例4的p型MOSFET的製程進行繪示的剖面圖。 [圖16B]就實施例4的p型MOSFET的製程進行繪示的剖面圖。 [圖16C]就實施例4的p型MOSFET的製程進行繪示的剖面圖。 [圖16D]就實施例4的p型MOSFET的製程進行繪示的剖面圖。 [圖16E]就實施例4的p型MOSFET的製程進行繪示的剖面圖。 [圖17]實施例4的具有SiGe通道之半導體元件的剖面圖。 [圖18]就實施例4中的電漿處理裝置的處理條件進行繪示的圖。

Claims (16)

  1. 一種半導體元件之製造方法，具有： 第1程序，其為對至少具有矽層與形成於前述矽層上的矽鍺層之半導體基板實施依第1條件之電漿處理而使前述矽鍺層曝露者；和 第2程序，其為對前述半導體基板實施依第2條件之電漿處理，使矽偏析於曝露的前述矽鍺層的表面者； 前述第1條件為可蝕刻前述矽鍺層或鄰接於前述矽鍺層之層的條件， 前述第2條件為實施氫電漿處理的條件， 前述第1程序及前述第2程序在相同的電漿處理裝置的處理室內連續進行。
  2. 如請求項1的半導體元件之製造方法，其中，前述第1程序及前述第2程序在室溫下進行。
  3. 如請求項1的半導體元件之製造方法，其中，前述第2條件為對前述半導體基板施加比於前述第1條件對前述半導體基板施加的高頻偏壓低的高頻偏壓、或不施加高頻偏壓的條件。
  4. 如請求項1的半導體元件之製造方法，其中，前述第2條件為使對前述半導體基板施加氫電漿處理的處理時間為20秒以內。
  5. 如請求項3的半導體元件之製造方法，其中，於前述第2程序形成的矽偏析層的厚度不足1nm。
  6. 如請求項1的半導體元件之製造方法，其中， 前述半導體元件為鰭型FET， 前述第1程序為形成前述鰭型FET的鰭構造的程序， 前述第1條件為將前述矽鍺層及前述矽層相對於前述半導體基板表面保持垂直度而進行異向性蝕刻的條件。
  7. 如請求項6的半導體元件之製造方法，其中，前述第2程序為在前述鰭構造上保留硬遮罩下對前述半導體基板實施前述氫電漿處理，前述硬遮罩用作為在前述第1程序為了形成前述鰭構造用的遮罩。
  8. 如請求項1的半導體元件之製造方法，其中， 前述半導體元件為鰭型FET， 前述第1程序為將以覆蓋前述鰭型FET的鰭構造的方式堆積的第1絕緣膜進行回蝕而形成元件分離區域的程序， 前述第1條件為將前述第1絕緣膜相對於前述矽鍺層及前述矽層而選擇性蝕刻的條件。
  9. 如請求項1的半導體元件之製造方法，其中， 前述半導體元件為鰭型FET， 前述第1程序為將形成於前述鰭型FET的鰭構造上的第2絕緣膜及形成於前述第2絕緣膜上的非晶矽層或多晶矽層進行蝕刻除去的程序， 前述第1條件為將前述第2絕緣膜及前述非晶矽層或前述多晶矽層，相對於前述矽鍺層及前述矽層而選擇性蝕刻的條件。
  10. 如請求項9的半導體元件之製造方法，其中， 前述第2絕緣膜為假閘極絕緣膜， 前述非晶矽層或前述多晶矽層為假閘極層。
  11. 如請求項1的半導體元件之製造方法，其中， 前述半導體元件為鰭型FET， 於前述鰭型FET的製程進行複數次前述第2程序。
  12. 如請求項1的半導體元件之製造方法，其中， 前述半導體元件為通道的全周被閘極覆蓋的閘極全環型FET， 在前述第1程序之前，於形成於前述半導體基板上的前述矽層與前述矽鍺層的層積膜形成鰭構造， 前述第1程序為從前述鰭構造將前述矽層進行蝕刻除去的程序， 前述第1條件為將前述鰭構造的前述矽層對於前述鰭構造的前述矽鍺層選擇性進行蝕刻的條件。
  13. 一種電漿處理裝置，其為對至少具有矽層與形成於前述矽層上之矽鍺層的半導體基板進行電漿處理者，具有： 處理室，其將前述半導體基板保持於真空環境； 樣品台，其配置於前述處理室內，載置前述半導體基板； 氣體供應機構，其對前述處理室供應電漿處理用的原料氣體； 高頻電源，其用於生成為了前述電漿處理用的電漿；和 控制部； 前述控制部連續進行對前述半導體基板實施依第1條件之電漿處理而使前述矽鍺層曝露的第1程序、和對前述半導體基板實施依第2條件之電漿處理而使矽偏析於曝露的前述矽鍺層的表面的第2程序， 前述氣體供應機構根據前述控制部的指示，於前述第1程序將在前述處理室蝕刻前述矽鍺層或鄰接於前述矽鍺層之層的原料氣體供應至前述處理室，於前述第2程序對前述處理室供應氫氣。
  14. 如請求項13的電漿處理裝置，其中，前述控制部使前述第1程序及前述第2程序在室溫下進行。
  15. 如請求項13的電漿處理裝置，其具有對前述半導體基板施加高頻偏壓的高頻偏壓電源， 前述高頻偏壓電源根據前述控制部的指示，於前述第1程序施加既定的高頻偏壓，於前述第2程序施加比前述既定的高頻偏壓低的高頻偏壓或不施加高頻偏壓。
  16. 如請求項13的電漿處理裝置，其中，前述控制部使於前述第2程序對前述半導體基板施加的氫電漿處理的處理時間為20秒以內。
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