TWI722966B - 半導體封裝裝置 - Google Patents

半導體封裝裝置 Download PDF

Info

Publication number
TWI722966B
TWI722966B TW109131583A TW109131583A TWI722966B TW I722966 B TWI722966 B TW I722966B TW 109131583 A TW109131583 A TW 109131583A TW 109131583 A TW109131583 A TW 109131583A TW I722966 B TWI722966 B TW I722966B
Authority
TW
Taiwan
Prior art keywords
decoupling
packaging device
semiconductor packaging
substrate
memory chip
Prior art date
Application number
TW109131583A
Other languages
English (en)
Other versions
TW202147556A (zh
Inventor
楊吳德
Original Assignee
南亞科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南亞科技股份有限公司 filed Critical 南亞科技股份有限公司
Application granted granted Critical
Publication of TWI722966B publication Critical patent/TWI722966B/zh
Publication of TW202147556A publication Critical patent/TW202147556A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

一種半導體封裝裝置包括基板、記憶體晶片、去耦陣列。基板具有上表面、電源端、接地端。記憶體晶片位於基板的上表面，且記憶體晶片具有電源焊墊，而電源焊墊經由節點電性連接至電源端以接收電力。去耦陣列設置於基板的上表面，而去耦陣列包括並聯的複數個去耦電容器。各個去耦電容器電性連接於節點和接地端之間。

Description

半導體封裝裝置
本發明涉及一種半導體封裝裝置。更具體的，是指能調節輸入電力的半導體封裝裝置。
半導體晶片有關的技術發展中，晶片尺寸的縮小是主要趨勢。隨著半導體晶片的需求快速增長，用於容納內部元件的空間也逐漸減小。
在半導體封裝領域，由於封裝體內部空間不足，電壓調節器不能應用在具有小型半導體晶片的半導體封裝裝置中。因此，耗能高的小尺寸半導體晶片會受到外部電力和自身雜訊所引起的負面影響。
從以上描述可知，有必要開發一種半導體封裝裝置，以實現體積縮小、同時調節外部電力並降低雜訊的負面影響。
本發明的其中一個實施方式是關於一種半導體封裝裝置包括基板、記憶體晶片、去耦陣列。基板具有上表面、電源端、接地端。記憶體晶片位於基板的上表面，且記憶體晶片具有電源焊墊，而電源焊墊經由節點電性連接至電源端以接收電力。去耦陣列設置於基板的上表面，而去耦陣列包括並聯的複數個去耦電容器。各個去耦電容器電性連接於節點和接地端之間。
在本發明的一個或多個實施方式中，記憶體晶片更包括接地焊墊，而接地焊墊電性連接基板的接地端。
在本發明的一個或多個實施方式中，去耦電容器的電容值大於或等於0.47 uF。
在本發明的一個或多個實施方式中，去耦陣列包括至少22個該些去耦電容器。
在本發明的一個或多個實施方式中，去耦陣列的電容值大於或等於10 uF。
在本發明的一個或多個實施方式中，去耦電容器中的任一者與記憶體晶片相隔的第一距離小於去耦電容器及基板的對應邊緣相隔的第二距離。
在本發明的一個或多個實施方式中，去耦陣列包括兩個去耦電容器群組，而記憶體晶片位於兩個去耦電容器群組之間。
在本發明的一個或多個實施方式中，兩個去耦電容器群組分別排列為兩條直行。
在本發明的一個或多個實施方式中，兩個去耦電容器群組分別排列為兩條平行的直行。
在本發明的一個或多個實施方式中，兩個去耦電容器群組的電容值皆大於或等於5 μF。
在本發明的一個或多個實施方式中，兩個去耦電容器群組皆包括至少11個去耦電容器。
在本發明的一個或多個實施方式中，記憶體晶片包括複數個金屬焊墊，金屬焊墊分別電性連接去耦電容器，且金屬焊墊設置於記憶體晶片的第一表面。
在本發明的一個或多個實施方式中，記憶體晶片的第一表面接觸基板的上表面，且基板具有開口露出金屬焊墊。
在本發明的一個或多個實施方式中，基板具有導線結構電性連接去耦電容器、電源端及接地端，讓去耦電容器電性連接於節點與接地端之間。
在本發明的一個或多個實施方式中，金屬焊墊經由奈米金屬線電性連接至導線結構。
在本發明的一個或多個實施方式中，半導體封裝裝置更包括壓模結構，其中壓模結構覆蓋記憶體晶片及去耦電容器。
綜上所述，本發明的半導體封裝裝置具有去耦陣列，而去偶陣列是由多個去耦電容器所組成，去耦電容器彼此電性連接以增加去耦陣列的電容值，以便於分流所輸入的電力，進而讓半導體封裝裝置的晶片在接收較高壓電力時仍維持正常功能。在另一方面，半導體封裝裝置包括面朝下的封裝結構，且去耦電容器排列為兩個平行的直行，晶片則位於去耦電容器所排成的兩個平行的直行之間。藉此，可以降低容納去耦電容器的所需要的空間，而有助於半導體封裝裝置朝微型化發展。
本發明可以以許多不同的形式實施。代表性實施例在附圖中示出，並且將在本文中詳細描述。本公開包含原理的示例或說明，並且本公開的態樣將不受限於所示的實施例。
請參考第1圖至第4圖。第1圖繪示為半導體封裝裝置100的立體示意圖。第2圖繪示為第1圖中，半導體封裝裝置100的上視示意圖。第3圖繪示為第2圖中，半導體封裝裝置100沿著截面線3-3繪製的截面圖。第4圖繪示為第1圖中，半導體封裝裝置100的電路圖。在本發明的一個實施方式中，半導體封裝裝置100包括基板110、記憶體晶片130、去耦陣列150。基板110具有上表面110a、電源端113、接地端115，其中電源端113可電性連接外部電源。記憶體晶片130位於基板110的上表面110a上，且記憶體晶片130具有電源焊墊131a，而電源焊墊131a經由節點117電性連接至電源端113以接收電力。去耦陣列150設置於基板110的上表面110a，去耦陣列150包括並聯的複數個去耦電容器150a，而去耦電容器150a電性連接於節點117和接地端115之間。此外，記憶體晶片130具有接地焊墊131b，且接地焊墊131b電性連接至基板110的接地端115。
去耦陣列150可以分流從電源端113傳輸至記憶體晶片130的電力，進而防止瞬態電流損壞記憶體晶片130。此外，複數個去耦電容器150a相互並聯，因此當去耦電容器150a的數量增加時，去耦陣列150的電容值也會上升。也就是說，去耦陣列150可以從電源端113分流更高壓的電力。
具體而言，基板110可以為銅箔基板(copper clad laminate , CCL)。記憶體晶片130可以為動態隨機存取記憶體晶片(dynamic random access memory, DRAM)。去耦陣列150的去耦電容器150a可以為陶瓷電容器(ceramic capacitor)，但本發明不以此為限。
基板110包括具有銅導線的導線結構119。導線結構119電性連接去耦電容器150a、電源端113以及接地端115，因此各去耦電容器150a電性連接於節點117與接地端115之間。電源端113及接地端115可以包括焊球(solder ball)以接收和傳輸電力和電訊號。焊球位於基板110的底面110c，且焊球更電性連接導線結構119。
半導體封裝裝置100更包括壓模結構170，其中壓模結構170以虛線繪示在第1圖，但省略於第2圖。壓模結構170位於基板110的上表面110a上，而壓模結構170覆蓋並包覆記憶體晶片130及去耦電容器150a。其中，壓模結構170包括環氧樹脂模製化合物(epoxy molding compound)以保護記憶體晶片130及去耦電容器150a。但本發明並不以此為限。
在本發明的一些實施方式中，記憶體晶片130更包括複數個金屬焊墊131，而金屬焊墊131分別電性連接去耦電容器150a。金屬焊墊131、電源焊墊131a及接地焊墊131b皆位於記憶體晶片130的第一表面130a。記憶體晶片130的第一表面130a接觸基板110的上表面110a，而基板110更具有開口111，開口111曝露金屬焊墊131、電源焊墊131a及接地焊墊131b。因此，半導體封裝裝置100為一個面朝下(face-down)的晶片封裝結構，以便於半導體封裝裝置100維持體積縮小。此外，金屬焊墊131是透過奈米金屬線電性連接導線結構119，例如是由打線接合(wire bonding)產生的奈米金屬線，但本發明並不以此為限。
在本發明的一些實施方式中，半導體封裝裝置100的去耦陣列150包括至少22個去耦電容器150a，而各個去耦電容器150a的電容值大於或等於0.47 uF。因此，去耦陣列150的電容值大於或等於10 uF，以便於對來自電源端113的電力進行分流。
具體而言，去耦陣列150包括兩個去耦電容器群組(去耦電容器150a所組成的群組)，而記憶體晶片130位於兩個去耦電容器群組之間)。其中，兩個去耦電容器群組的電容值皆大於或等於5 μF，故去耦陣列150的電容值大於或等於10 μF。
除此之外，兩個去耦電容器群組皆包括至少11個去耦電容器150a，且兩個去耦電容器群組分別排列為兩條平行的直行。藉由前述的配置關係，半導體封裝裝置100容置去耦電容器150a的所需空間較小，因此有助於實現微型化的目標。
在本發明的一些實施方式中，去耦電容器150a與記憶體晶片130相隔第一距離D1，去耦電容器150A與基板110的對應邊緣110b相隔第二距離D2，其中第一距離D1小於第二距離D2。詳細來說，對應邊緣110b指的是與所選擇的去耦電容器150最靠近的基板110的邊緣。此外，第一距離D1是指所選擇的去耦電容器150a到記憶體晶片130的最短距離。第二距離D2是指去耦電容器150a到基板110的對應邊緣110b的最短距離。
綜上所述，本發明的半導體封裝裝置具有去耦陣列，而去偶陣列是由多個去耦電容器所組成，去耦電容器彼此電性連接以增加去耦陣列的電容值，以便於分流所輸入的電力，進而讓半導體封裝裝置的晶片在接收較高壓電力時仍維持正常功能。在另一方面，半導體封裝裝置包括面朝下的封裝結構，且去耦電容器排列為兩個平行的直行，晶片則位於去耦電容器所排成的兩個平行的直行之間。藉此，可以降低容納去耦電容器的所需要的空間，而有助於半導體封裝裝置朝微型化發展。
100:半導體封裝裝置 110:基板 110a:上表面 110b:對應邊緣 111:開口 113:電源端 115:接地端 117:節點 119:導線結構 130:記憶體晶片 131:金屬焊墊 131a:電源焊墊 131b:接地焊墊 150:去耦陣列 150a:去耦電容器 170:壓模結構 D1:第一距離 D2:第二距離
為描述獲得本發明上述或其它的優點和特徵，將通過參考其具體實施方式對上述簡要描述的原理進行更具體的闡釋，而具體實施方式被展現在附圖中。這些附圖僅例示性地描述本發明，因此不被認為是對範圍的限制。通過附圖，本發明的原理會被清楚解釋，且附加的特徵和細節將被完整描述，其中： 第1圖係根據本發明一些實施方式所繪示半導體封裝裝置的立體示意圖； 第2圖繪示為第1圖中，半導體封裝裝置的上視示意圖； 第3圖繪示為第2圖中，半導體封裝裝置沿著截面線3-3繪製的截面圖；以及 第4圖繪示為第1圖中，半導體封裝裝置的電路圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:半導體封裝裝置
110:基板
110a:上表面
130:記憶體晶片
150:去耦陣列
150a:去耦電容器
170:壓模結構

Claims (16)

  1. 一種半導體封裝裝置，包括： 一基板，具有一上表面、一電源端及一接地端； 一記憶體晶片，設置於該基板的該上表面上並具有一電源焊墊，其中電源焊墊經由一節點連接至該電源端；及 一去耦陣列，設置於該基板的該上表面上，其中該去耦陣列包括並聯的複數個去耦電容器，且該些去耦電容器電性連接於該節點與該接地端之間。
  2. 如請求項1所述之半導體封裝裝置，其中該記憶體晶片更包括一接地焊墊，該接地焊墊電性連接該基板的該接地端。
  3. 如請求項1所述之半導體封裝裝置，其中該些去耦電容器的電容值大於或等於0.47 uF。
  4. 如請求項1所述之半導體封裝裝置，其中該去耦陣列包括至少22個該些去耦電容器。
  5. 如請求項1所述之半導體封裝裝置，其中該去耦陣列的電容值大於或等於10 uF。
  6. 如請求項1所述之半導體封裝裝置，其中該些去耦電容器中的任一者及該記憶體晶片相隔的一第一距離小於該些去耦電容器的該者及該基板的一對應邊緣相隔的一第二距離。
  7. 如請求項1所述之半導體封裝裝置，其中該去耦陣列包括兩個去耦電容器群組，而該記憶體晶片位於該兩個去耦電容器群組之間。
  8. 如請求項7所述之半導體封裝裝置，其中該兩個去耦電容器群組分別排列為兩條直行。
  9. 如請求項7所述之半導體封裝裝置，其中該兩個去耦電容器群組分別排列為兩條平行的直行。
  10. 如請求項7所述之半導體封裝裝置，其中該兩個去耦電容器群組的電容值皆大於或等於5 μF。
  11. 如請求項7所述之半導體封裝裝置，其中該兩個去耦電容器群組皆包括至少11個該些去耦電容器。
  12. 如請求項7所述之半導體封裝裝置，其中該記憶體晶片包括複數個金屬焊墊，該些金屬焊墊分別電性連接該些去耦電容器，且該些金屬焊墊設置於該記憶體晶片的一第一表面。
  13. 如請求項12所述之半導體封裝裝置，其中該記憶體晶片的該第一表面接觸該基板的該上表面，且該基板具有一開口露出該些金屬焊墊。
  14. 如請求項12所述之半導體封裝裝置，其中該基板具有一導線結構電性連接該些去耦電容器、該電源端及該接地端，讓該些去耦電容器電性連接於該節點與該接地端之間。
  15. 如請求項14所述之半導體封裝裝置，其中該些金屬焊墊經由奈米金屬線電性連接至該導線結構。
  16. 如請求項14所述之半導體封裝裝置，更包括壓模結構，其中該壓模結構覆蓋該記憶體晶片及該些去耦電容器。
TW109131583A 2020-06-11 2020-09-14 半導體封裝裝置 TWI722966B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/899,566 2020-06-11
US16/899,566 US20210391245A1 (en) 2020-06-11 2020-06-11 Semiconductor package device

Publications (2)

Publication Number Publication Date
TWI722966B true TWI722966B (zh) 2021-03-21
TW202147556A TW202147556A (zh) 2021-12-16

Family

ID=76035756

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109131583A TWI722966B (zh) 2020-06-11 2020-09-14 半導體封裝裝置

Country Status (3)

Country Link
US (1) US20210391245A1 (zh)
CN (1) CN113809052A (zh)
TW (1) TWI722966B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023128759A (ja) * 2022-03-04 2023-09-14 キオクシア株式会社 半導体装置、電子機器、及び半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140252573A1 (en) * 2013-03-08 2014-09-11 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
TWI517354B (zh) * 2014-02-25 2016-01-11 力成科技股份有限公司 內藏去耦合電容之半導體封裝構造
EP3493249A1 (en) * 2017-11-30 2019-06-05 INTEL Corporation Gate line plug structures for advanced integrated circuit structure fabrication

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739576A (en) * 1995-10-06 1998-04-14 Micron Technology, Inc. Integrated chip multilayer decoupling capacitors
US6822337B2 (en) * 2002-09-30 2004-11-23 Ultratera Corporation Window-type ball grid array semiconductor package
US7030481B2 (en) * 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
KR100688554B1 (ko) * 2005-06-23 2007-03-02 삼성전자주식회사 파워 디커플링 커패시터를 포함하는 반도체 메모리 소자
KR100834835B1 (ko) * 2006-09-15 2008-06-03 후지쯔 가부시끼가이샤 콘덴서를 내장한 반도체 장치 및 그 제조 방법
JP2009076815A (ja) * 2007-09-25 2009-04-09 Nec Electronics Corp 半導体装置
US8120162B2 (en) * 2007-09-28 2012-02-21 Integrated Device Technology, Inc. Package with improved connection of a decoupling capacitor
JP5658640B2 (ja) * 2011-09-12 2015-01-28 ルネサスエレクトロニクス株式会社 半導体装置
US9337138B1 (en) * 2012-03-09 2016-05-10 Xilinx, Inc. Capacitors within an interposer coupled to supply and ground planes of a substrate
KR102592640B1 (ko) * 2016-11-04 2023-10-23 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US10892021B2 (en) * 2018-06-05 2021-01-12 Sandisk Technologies Llc On-die capacitor for a memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140252573A1 (en) * 2013-03-08 2014-09-11 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
US20170263470A1 (en) * 2013-03-08 2017-09-14 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
TWI517354B (zh) * 2014-02-25 2016-01-11 力成科技股份有限公司 內藏去耦合電容之半導體封裝構造
EP3493249A1 (en) * 2017-11-30 2019-06-05 INTEL Corporation Gate line plug structures for advanced integrated circuit structure fabrication

Also Published As

Publication number Publication date
CN113809052A (zh) 2021-12-17
US20210391245A1 (en) 2021-12-16
TW202147556A (zh) 2021-12-16

Similar Documents

Publication Publication Date Title
US11018121B2 (en) Semiconductor packages
US5656856A (en) Reduced noise semiconductor package stack
US7119427B2 (en) Stacked BGA packages
KR101024241B1 (ko) 반도체 장치 및 그를 포함하는 반도체 패키지
US7405472B2 (en) Semiconductor device
US9627354B1 (en) Semiconductor memory device
US7355272B2 (en) Semiconductor device with stacked semiconductor chips of the same type
US12074103B2 (en) Circuit assembly
TW201705442A (zh) 半導體封裝組件
US20100102430A1 (en) Semiconductor multi-chip package
US20050141206A1 (en) Array capacitors with voids to enable a full-grid socket
US20240186293A1 (en) Semiconductor package having chip stack
WO2013098929A1 (ja) 半導体チップ及びそれを搭載した半導体モジュール
US7960823B2 (en) Semiconductor device with different sized ESD protection elements
TWI722966B (zh) 半導體封裝裝置
US20150228602A1 (en) Semicondcutor chip and semionducot module
KR101672967B1 (ko) 에지에 사이드 패드를 포함하는 반도체 스택 패키지, 및 이를 포함하는 고밀도 메모리 모듈, 전자 회로 기기
JP4754201B2 (ja) 半導体装置
CN112133679A (zh) 半导体装置
TWI781863B (zh) 平面式多晶片裝置
US20230260976A1 (en) Semiconductor device
TWI825771B (zh) 半導體元件
TWI473242B (zh) 晶片封裝結構
US20240055359A1 (en) Chip package with core embedded integrated devices
US20240290738A1 (en) Semiconductor device