TW201705442A - 半導體封裝組件 - Google Patents

半導體封裝組件 Download PDF

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Publication number
TW201705442A
TW201705442A TW105107875A TW105107875A TW201705442A TW 201705442 A TW201705442 A TW 201705442A TW 105107875 A TW105107875 A TW 105107875A TW 105107875 A TW105107875 A TW 105107875A TW 201705442 A TW201705442 A TW 201705442A
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Taiwan
Prior art keywords
semiconductor package
semiconductor
wire
semiconductor wafer
dielectric layer
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TW105107875A
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English (en)
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TWI615941B (zh
Inventor
林子閎
彭逸軒
蕭景文
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聯發科技股份有限公司
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Publication of TW201705442A publication Critical patent/TW201705442A/zh
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Publication of TWI615941B publication Critical patent/TWI615941B/zh

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Abstract

本發明提供半導體封裝組件，半導體封裝組件包含第一半導體封裝，其包含第一半導體晶片，以及重佈層結構與第一半導體晶片耦合，第一重佈層結構包含第一導線設置於第一層水平高度，第二導線設置於第二層水平高度，第一金屬層間介電層及位於第一金屬層間介電層旁的第二金屬層間介電層設置於第一導線與第二導線之間。

Description

半導體封裝組件
本發明係有關於半導體封裝組件，特別係有關於具有被動元件的半導體封裝組件。
為了確保電子產品與通訊裝置的微縮化與多功能性，需要小尺寸的半導體封裝，並且支撐多接腳連接、高速操作和具有高功能性。傳統的半導體封裝通常將被動元件設置於軟性電路板上。然而，軟性電路板需要提供額外讓被動元件安裝的區域，因此難以縮減封裝尺寸。
因此，需要創新的半導體封裝組件。
本揭露的一些實施例提供半導體封裝組件，其包含第一半導體封裝，包含第一半導體晶片；以及第一重佈層結構與第一半導體晶片耦合，其中第一重佈層結構包含：第一導線位於第一層水平高度；第二導線位於第二層水平高度；以及第一金屬層間介電層及位於第一金屬層間介電層旁的第二金屬層間介電層，其中第一金屬層間介電層和第二金屬層間介電層係設置於第一導線與第二導線之間。
本揭露的另一些實施例提供半導體封裝組件，其包含第一半導體封裝，包含第一半導體晶片；以及第一重佈層 結構與第一半導體晶片耦合，其中第一重佈層結構包含：第一導線位於第一層水平高度；第二導線位於第二層水平高度；第一金屬層間介電層和第二金屬層間介電層設置於第一導線與第二導線之間；以及電容結構由第一導線、第二導線及第二金屬層間介電層組成，其中第一金屬層間介電層的介電常數小於五分之一倍的第二金屬層間介電層的介電常數。
本揭露的另一些實施例提供半導體封裝組件，其包含第一半導體封裝，包含第一半導體晶片；以及第一重佈層結構與第一半導體晶片耦合，其中第一重佈層結構包含：第一導線位於第一層水平高度；第二導線位於第二層水平高度；第一金屬層間介電層和第二金屬層間介電層設置於第一導線與第二導線之間；以及電容結構由第一導線、第二導線及第二金屬層間介電層組成，其中第二金屬層間介電層的厚度小於或等於第一導線和第二導線的厚度。
以下實施例配合相關的圖式提供更詳細的說明。
200‧‧‧基座
202‧‧‧晶片附著表面
302、202a、202b、402、404‧‧‧半導體晶片
300a、300b、300c、300d‧‧‧半導體封裝
302a‧‧‧背面
302b‧‧‧正面
304、408、410、425‧‧‧接墊
306、320、428‧‧‧導電結構
308、328、418‧‧‧重佈層結構
310、312、324、352、354、420、422‧‧‧表面
314、336、340‧‧‧導線
316‧‧‧焊料遮罩層
318、334、424、456a、456b‧‧‧金屬層間介電層
322‧‧‧導孔
350、412‧‧‧模塑料
400‧‧‧第二半導體封裝
414、416‧‧‧接合線
426‧‧‧導線
427‧‧‧焊料遮罩層
450a、450b‧‧‧MIM電容結構
452a、452b‧‧‧第一導線
452a-1、452b-1‧‧‧第一電極
452b-1a、454b-1a‧‧‧凸面部分
452b-1b、454b-1b‧‧‧凹面部分
454a、454b‧‧‧第二導線
454a-1、454b-1‧‧‧第二導線
458a、458b、460a、460b‧‧‧界面
500a、500b、500c、500d‧‧‧半導體封裝組件
600a、600b‧‧‧部分
T1、T2、T3、T4‧‧‧厚度
本發明能藉由閱讀以下說明書的詳細說明並配合所附圖式說明之範例而完全理解，其中：
第1A圖係顯示根據本發明一些實施例，包含系統晶片(system-on-chip,SOC)封裝之半導體封裝組件的剖面示意圖。
第1B圖係顯示第1A圖的內嵌於重佈層結構的金屬-絕緣體-金屬(metal-insulator-metal,MIM)電容結構之部分的放大圖。
第2A圖係顯示根據本發明一些實施例，包含系統晶片封裝 之半導體封裝組件的剖面示意圖。
第2B圖係顯示第2A圖中內嵌於重佈層結構的金屬-絕緣體-金屬(MIM)電容結構之部分的放大圖。
第3圖係顯示根據本發明一些實施例，包含系統晶片封裝之半導體封裝組件的剖面示意圖。
第4圖係顯示根據本發明一些實施例，包含系統晶片(SOC)封裝及堆疊於其上的動態隨機存取記憶體(dynamic random access memory,DRAM)封裝之半導體封裝組件的剖面示意圖。
以下描述用以實施本揭露之最佳實施例。然而，此描述僅是用以說明本揭露之原理，且並非用以限制本揭露之範圍。本揭露之範圍係以申請專利範圍決定。
以下的揭露內容提供許多不同的實施例或範例以及圖式，然而，這些僅是用以說明本揭露之原理，且並非用以限制本揭露之範圍。本揭露之範圍係以申請專利範圍決定。本揭露之圖式僅為說明之用，且並非用以限定本揭露之範圍。在圖式中，為了清楚說明本揭露，部分元件之尺寸可能被放大且並未照實際比例繪製。此尺寸以及相對之尺寸並未對應實施本揭露時之實際尺寸。
第1A圖係根據本發明一些實施例，包含系統晶片(SOC)封裝之半導體封裝組件(semiconductor package assembly)500a的剖面示意圖。第1B圖係顯示第1A圖中內嵌於重佈層結構308的金屬-絕緣體-金屬(MIM)電容結構450a之部分600a的放大圖。在一些實施例，半導體封裝組件500a係晶圓 級(wafer-level)半導體封裝組件，例如為覆晶(flip-chip)半導體封裝組件。
如第1A圖所示，半導體封裝組件500a包含至少一安裝於基座(base)200的晶圓級半導體封裝(semiconductor package)。在此實施例，晶圓級半導體封裝300a包含系統晶片(SOC)封裝。
如第1A圖所示，基座200例如為印刷電路板(printed circuit board,PCB)，可由聚丙烯(polypropylene,PP)製成。應該注意的是，基座200可為單層或多層結構。複數個接墊(未繪示)及/或導線(未繪示)設置於基座200的晶片接合表面(die-attach surface)202上。在一實施例，導線可包含電源段(power segment)、信號線段(signal trace segment)或接地線段(ground trace segment)，其用來作為半導體封裝300a輸出/輸入(input/output,I/O)的連接。此外，半導體封裝300a係直接安裝於導線上。在其他一些實施例，接墊係設置於晶片接合表面202上，連接至導線之不同終端。接墊係用來直接安裝在半導體封裝300a在其上。
如第1A圖所示，半導體封裝300a係藉由接合製程(bonding process)安裝於基座200的晶片接合表面202上。半導體封裝300a係經由導電結構320安裝於基座200上。半導體封裝300a包含半導體晶片302及重佈層結構308。在一實施例，半導體晶片302可為系統晶片(SOC)型晶片。在其他實施例，半導體晶片302例如可為包含中央處理單元(central processing unit,CPU)、圖像處理單元(graphics processing unit,GPU)、動態隨 機存取記憶體(DRAM)控制器或上述任意組合的邏輯晶片(logic die)。
如第1A圖所示，半導體晶片302係由覆晶技術製成。半導體晶片302的接墊304係設置於正面302上，以電性連接至半導體晶片302的電路(未繪示)。在一些實施例，接墊304屬於半導體晶片302之內連線結構(interconnection structure)(未繪示)的最頂部金屬層。半導體晶片302的接墊304係與對應的導電結構306(例如導電凸塊)接觸。應該注意的是，整合於半導體封裝組件500a上的半導體晶片302的數目並未限定於實施例所揭露之數目。
如第1A圖所示，半導體封裝300a更包含覆蓋且圍繞半導體晶片302的模塑料(molding compound)350。模塑料350係與半導體晶片302接觸。模塑料350具有分別靠近於半導體晶片302的正面302b的表面352及靠近於背面302a且相對於表面352的表面354。模塑料350也可覆蓋半導體晶片302的背面302a。在一些實施例，模塑料350可由非導電性材料製成，例如環氧化物(epoxy)、樹脂(resin)、可塑形聚合物(moldable polymer)或類似的材料。可在大體上為液態時塗佈模塑料350，並經由化學反應固化模塑料350，例如成為環氧化物或樹脂。在其它一些實施例，模塑料350可為紫外光(UV)或熱固化聚合物的膠體或具延展性的固體，而能環繞地設置在半導體晶片302周圍，且可經由UV或熱固化製程來固化。模塑料350可使用模具(未繪示)固化。
如第1A圖所示，半導體封裝300a更包含設置於半 導體晶片302的正面302b上的重佈層結構308。重佈層結構308也設置於模塑料350的表面352上。半導體封裝300a的半導體晶片302經由導電結構306(例如為導電凸塊或錫膏(solder paste))連接至重佈層結構308的表面310。重佈層結構308可與模塑料350接觸。在一些實施例，重佈層結構308可具有設置於一或多層之金屬層間介電(inter-metal dielectric,IMD)層318內的一或多個導線314(包含第一導線452a及第二導線454a)。導線314的接墊部分係露出於焊料遮罩層316的開口。然而，應該注意的是，如第1A圖所示的導線314的數目及金屬層間介電層318的數目僅為一示例且並非用於限定本揭露。
如第1A和1B圖所示，半導體封裝300a的重佈層結構308更包含內嵌於重佈層結構308的金屬-絕緣體-金屬(MIM)電容結構450a。MIM電容結構450a與半導體晶片302耦合。在一些實施例，MIM電容結構450a包含第一電極452a-1、第二電極454a-1及位於上述兩者間的金屬層間介電層456a。在一些實施例，第一電極452a-1係重佈層結構308之靠近於半導體晶片302的第一導線452a的一段(segment)。此外，第二電極454a-1係重佈層結構308之靠近於導電結構320的第二導線454a的段。如第1A和1B圖所示，第一導線452a被設計為位於第一層水平高度(first layer-level)，且第二導線454a被設計為位於與第一層水平高度不同的第二層水平高度。此外，第一導線452a經由金屬層間介電層318和456a與第二導線454a隔開。
在一實施例，如第1B圖所示，第一電極452a-1大抵上平行於第二電極454a-1。在剖面圖中，MIM電容結構450a 的第一電極452a-1及第二電極454a-1為條狀(strip shape)。例如，如第1A和1B圖所示，在剖面圖中，每個第一電極452a-1和第二電極454a-1具有平坦表面。第一導線452a和第一電極452a-1被設計為具有均勻的厚度T1。相似地，第二導線454a和第二電極454a-1被設計為具有均勻的厚度T2。在一些實施例，厚度T1大抵上與厚度T2相等。例如，厚度T1和厚度T2被設計為小於或等於4μm。
如第1A和1B圖所示，MIM電容結構450a的金屬層間介電層456a設置在位於第一導線452a和第二導線454a之間的金屬層間介電層318旁。在剖面圖中，金屬層間介電層456a係條狀。此外，如第1A和1B圖所示，在剖面圖中，第一電極452a-1和金屬層間介電層456a間的界面458a或第二電極454a-1和金屬層間介電層456a間的界面460a大抵上為平坦表面。在一些實施例，金屬層間介電層456a係高介電常數(high-k，k係介電層的介電常數)介電層。金屬層間介電層456a的k值被設計為大於或等於20，其遠大於金屬層間介電層318的k值(金屬層間介電層318例如為二氧化矽(SiO2)層(k=3.9))。例如，金屬層間介電層318的介電常數係小於五分之一倍的金屬層間介電層456a的介電常數。在一些實施例，金屬層間介電層456a可由有機材料製成，其包含聚合物基材料；非有機材料，其包含氮化矽(SiNX)、氧化矽(SiOX)、石墨烯(graphene)或類似的材料。在其他一些實施例，金屬層間介電層456a可由光敏感材料製成，其包含乾膜光阻(dry film photoresist)或膠膜(taping film)。
如第1B圖所示，MIM電容結構450a的金屬層間介 電層456a的厚度T3被設計為小於金屬層間介電層318的厚度T4。此外，如第1B圖所示，在剖面圖中，金屬層間介電層456a的厚度T3被設計為小於或等於第一導線452a的厚度T1和第二導線454a的厚度T2。例如，MIM電容結構450a的金屬層間介電層456a的厚度T3被設計為小於或等於約4μm。
如第1A圖所示，半導體封裝300a更包含穿過模塑料350的導孔(via)322。導孔322與重佈層結構308的導線314(包含第一導線452a和第二導線454a)耦合。半導體晶片302被導孔322圍繞。每一個導孔322的兩個終端分別靠近於重佈層結構308的表面310和模塑料350的表面354。在一些實施例，導孔322可包含由銅形成的封裝穿孔(through package via,TPV)。
如第1A圖所示，半導體封裝300a更包含設置於重佈層結構308之遠離半導體晶片302的表面312上的導電結構320。導電結構320經由焊料遮罩層316之露出的開口與導線314耦合。此外，導電結構320經由重佈層結構308與模塑料350隔開。換句話說，導電結構320並未與模塑料350接觸。在一些實施例，導電結構320可包含導電凸塊結構，例如銅凸塊或焊料凸塊結構、導電柱結構、導線結構或導電膠(paste)結構。
在一些實施例，半導體封裝組件500a被設計為用來製造被動元件結構，例如內嵌於重佈層結構308的金屬-絕緣體-金屬(MIM)電容結構450a。MIM電容結構450a係由重佈層結構308的導線段(例如第一電極452a-1和第二電極454a-1)和位於重佈層結構308的金屬層間介電層(例如金屬層間介電層318)旁的高介電常數電容介電材料層(例如金屬層間介電層456a)所 組成。MIM電容結構450a被設計為用來增加金屬層間介電層456a的介電常數(k)或用來減少第一電極452a-1的厚度(例如厚度T1)、第二電極454a-1的厚度(例如厚度T2)和金屬層間介電層456a的厚度(例如厚度T3)，如此可獲得較大的電容值。內嵌式MIM電容結構450a可整合於重佈層結構308，並且使用相似於重佈層結構308的製程來形成。MIM電容結構450a可在半導體封裝組件內提供相當程度的製程相容性。此外，半導體封裝組件500a甚至可在半導體晶片302(例如系統晶片)被取代時，有助於增進表面安裝技術(surface-mount technology,SMT)的良率。此外，由於縮短了半導體晶片302(例如系統晶片)和MIM電容結構450a間的傳導路徑，因此增進內嵌式MIM電容結構450a的信號完整性/電源完整性(signal integrity/power integrity,SI/PI)的效能。內嵌式MIM電容結構450a可提供半導體封裝組件500a之系統整合的設計彈性。
第2A圖係根據本發明一些實施例，包含系統晶片封裝之半導體封裝組件500b的剖面示意圖。第2B圖係顯示第2A圖中內嵌於重佈層結構308的金屬-絕緣體-金屬(MIM)電容結構450b之部分600b的放大圖。在此實施例中與先前第1A和1B圖所敘述相同或相似的元件之描述為簡潔目的而省略。
如第2A和2B圖所示，半導體封裝組件500b與第1A-1B圖所示的半導體封裝組件500a之間其中一個不同處在於：半導體封裝組件500b包含內嵌於系統晶片(SOC)封裝300b的重佈層結構308內的MIM電容結構450b。在一些實施例，MIM電容結構450b包含第一電極452b-1、第二電極454b-1和位於上 述兩者之間的金屬層間介電層456b。在一些實施例，第一電極452b-1係靠近半導體晶片302的重佈層結構308的第一導線452b的一段(segment)。此外，第二電極454b-1係靠近導電結構320的重佈層結構308的第二導線454b的一段。如第2A和2B圖所示，第一導線452b被設計成位於第一層水平高度且第二導線454b被設計成位於與第一層水平高度不同的第二層水平高度。此外，第一導線452b經由金屬層間介電層318/456b與第二導線454b隔開。第一導線452b被設置成具有均勻的厚度T1。相似地，第二導線454b被設計成具有均勻的厚度T2。在一些實施例，厚度T1大抵上與厚度T2相等。例如，厚度T1與厚度T2被設置成小於或等於4μm。
在一實施例，如第2B圖所示，第一電極452b-1大抵上平行於第二電極454b-1。在剖面圖中，MIM電容結構450b的第一電極452b-1及第二電極454b-1為鋸齒形(zigzag shape)。例如，如第2B圖所示，在剖面圖中，第一電極452b-1具有包含凸面部分452b-1a和凹面部分452b-1b的不平坦表面。相似地，如第2B圖所示，在剖面圖中，第二電極454b-1具有包含凸面部分454b-1a和凹面部分454b-1b的不平坦表面。
如第2A和2B圖所示，MIM電容結構450b的金屬層間介電層456b設置在位於第一導線452b和第二導線454b之間的金屬層間介電層318旁。在剖面圖中，金屬層間介電層456a係鋸齒形。此外，如第2A和2B圖所示，在剖面圖中，MIM電容結構450b中與金屬層間介電層456b接觸的第一電極452b-1和第二電極454b-1係鋸齒形。在一些實施例，如第2A和2B圖所 示，在剖面圖中，第一電極452b-1和金屬層間介電層456a間的界面458b或第二電極454b-1和金屬層間介電層456b間的界面460b大抵上為不平坦且週期性變化的表面。例如，界面458b具有包含對應至凸面部分452b-1a的凸面部分和對應至凹面部分452b-1b的凹面部分的不平坦表面。相似地，界面460b具有包含對應至凸面部分454b-1a的凸面部分和對應至凹面部分454b-1b的凹面部分的不平坦表面。
如第2B圖所示，MIM電容結構450b的金屬層間介電層456b的厚度T3被設計為小於金屬層間介電層318的厚度T4。此外，如第2B圖所示，在剖面圖中，金屬層間介電層456b的厚度T3被設計為小於或等於第一導線452b的厚度T1和第二導線454b的厚度T2。例如，MIM電容結構450b的金屬層間介電層456b的厚度T3被設計為小於或等於4μm。
在一些實施例，半導體封裝組件500b被設計來製造被動元件結構，例如，內嵌於半導體封裝300b之重佈層結構308的金屬-絕緣體-金屬(MIM)電容結構450b。半導體封裝組件500b的優點與半導體封裝組件500a的優點相似。此外，電容結構450b被設計成具有鋸齒狀的電極(例如第一電極452b-1和第二電極454b-1)和鋸齒狀的電容介電層(例如金屬層間介電層456b)，以增加電容結構450b的面積，如此可獲得較大的電容值。此外，電容結構450b被設計成用來增加金屬層間介電層456b的介電常數(k)或減少第一電極452b-1的厚度(例如厚度T1)、第二電極454b-1的厚度(例如厚度T2)和金屬層間介電層456b的厚度(例如厚度T3)，如此可獲得較大的電容值。
第3圖係顯示根據本發明一些實施例，包含半導體封裝300c之半導體封裝組件500c的剖面示意圖。在此實施例中與先前第1A-1B和2A-2B圖所敘述相同或相似的元件之描述為簡潔目的而省略。
如第3圖所示，半導體封裝組件500c與第2A和2B圖所示的半導體封裝組件500b之間其中一個不同處在於：半導體封裝組件500c的半導體封裝300c包含兩個並列(side-by-side)排列的半導體晶片202a及202b。在一些實施例，半導體晶片202a和202b中至少一者為系統晶片(SOC)型晶片。例如，半導體晶片202a和202b係系統晶片(SOC)型晶片。或者，半導體晶片202a係系統晶片(SOC)型晶片，且半導體晶片202b係記憶體晶片，例如動態隨機存取記憶體(DRAM)晶片。在一些實施例，內嵌於重佈層結構308的MIM電容結構450b被設計成與系統晶片(SOC)型晶片(例如半導體晶片202a)耦合。因此，半導體封裝組件500c的半導體封裝300c包含純系統晶片封裝或混合式系統晶片封裝。然而，半導體晶片的數目和排列方式並不限定於在此揭露的實施例。
第4圖係顯示根據本發明一些實施例，包含第一半導體封裝300d和堆疊於其上的第二半導體封裝400(例如，動態隨機存取記憶體(DRAM)封裝)之半導體封裝組件500d的剖面示意圖。在此實施例中與先前第1A-1B、2A-2B和3A-3B圖所敘述相同或相似的元件之描述為簡潔目的而省略。
如第4圖所示，半導體封裝組件500d與第2A和2B圖所示的半導體封裝組件500b之間其中一個不同處在於：半導 體封裝組件500d的第一半導體封裝300d更包含設置在第一半導體晶片302上的重佈層結構328。此外，半導體封裝組件500d更包含藉由接合製程而堆疊在半導體封裝300d上的第二半導體封裝400。重佈層結構328設置於模塑料350上。重佈層結構328之靠近第一半導體晶片302的表面324與模塑料350的表面354接觸。換句話說，模塑料350之相對的表面352和表面354分別接觸重佈層結構308和重佈層結構328。
與重佈層結構308相同，重佈層結構328可具有一或多個導線336設置於一或多層的金屬層間介電層334內。導線336的接墊部分露出於金屬層間介電層334之遠離模塑料350的表面354的開口。然而，應該注意的是，第4圖所示的導線336的數目和金屬層間介電層334的數目僅為一示例，本發明並不限定於此。如第4圖所示，重佈層結構328藉由穿過位於重佈層結構308和重佈層結構328之間的模塑料350之導孔322與重佈層結構308耦合。
如第4圖所示，半導體封裝組件500d更包含堆疊在第一半導體封裝300d上的第二半導體封裝400。在此實施例，第二半導體封裝400包含記憶體封裝，例如為動態隨機存取記憶體(DRAM)封裝。第二半導體封裝400係經由導電結構428安裝於第一半導體封裝300上。第二半導體封裝400藉由第一半導體封裝300d的重佈層結構328和導孔322與重佈層結構308耦合。
如第4圖所示，第二半導體封裝400包含重佈層結構418，至少一半導體晶片(例如，兩個動態隨機存取記憶體 (DRAM)晶片402和404)及模塑料412。由於第二半導體封裝400係堆疊在第一半導體封裝300d上，因此重佈層結構328位於重佈層結構308和重佈層結構418間。重佈層結構418具有相對的表面420及表面422。表面420係提供來讓半導體晶片安裝於其上，且表面422係提供來讓導電凸塊428接合於其上。與重佈層結構308和重佈層結構328相似，重佈層結構418可具有一或多個導線426設置於一或多層的金屬層間介電層424內。導線426的接墊部分露出於焊料遮罩層427的開口。然而，應該注意的是，第4圖所示的導線426的數目和金屬層間介電層424的數目僅為一示例，本發明並不限定於此。
在此實施例，如第4圖所示，半導體晶片402和半導體晶片404為動態隨機存取記憶體(DRAM)晶片。半導體晶片402係用黏膠(paste)(未繪示)安裝於重佈層結構418的表面420上。此外，半導體晶片404係使用黏膠(未繪示)堆疊在半導體晶片402上。半導體晶片402具有位於其上的接墊408，且半導體晶片404具有位於其上的接墊410。
半導體晶片402和半導體晶片404的接墊408和接墊410可藉由接合線(例如分別為接合線414和接合線416)而耦合至重佈層結構418的接墊425。然而，半導體晶片堆疊的數目並不限定於在此揭露的實施例。此外，如第4圖所示的兩個半導體晶片402和半導體晶片404可並列(side-by-side)排列。因此，半導體晶片402和半導體晶片404藉由黏膠(未繪示)安裝於重佈層結構418的表面420上。
如第4圖所示，模塑料412圍繞半導體晶片402和半 導體晶片404。此外，模塑料412與重佈層結構412的表面420、半導體晶片402和半導體晶片404接觸，與模塑料350相似，模塑料412可由非導電性材料製成，例如環氧化物、樹脂、可塑形聚合物或類似的材料。
如第4圖所示，第二半導體封裝400更包含設置於重佈層結構418之遠離半導體晶片402和半導體晶片404的表面422上的導電結構428。導電結構428藉由焊料遮罩層427的開口而耦合至導線424。此外，導電結構428經由重佈層結構418與模塑料412隔開。第二半導體封裝400耦合至重佈層結構308及/或第一半導體封裝300d的MIM電容結構450b。更具體而言，第二半導體封裝400的導電結構428與穿過第一半導體封裝300d的重佈層結構328而形成的導孔340耦合。此外，導孔340與重佈層結構328的導線336耦合。與導電結構320相同，導電結構428可包含導電凸塊結構，例如為銅凸塊或焊料凸塊結構、導電柱結構、導線結構或導電膠結構。
本發明之實施例並不打算限定半導體晶片的種類。例如，在一些實施例，半導體晶片302可為基頻(baseband)晶片，其他的半導體晶片402和半導體晶片404可為射頻(radio-frequency,RF)晶片。在其他一些實施例，半導體晶片302可為類比處理器晶片(analog processor,AP)晶片，其他的半導體晶片402或半導體晶片404可為數位處理器(digital processor,DP)晶片。
實施例提供半導體封裝組件。在一些實施例，半導體封裝組件被設計成來製造被動元件結構，例如，金屬-絕 緣體-金屬(MIM)電容結構內嵌且整合於重佈層結構內。MIM電容結構由重佈層結構的導線(例如作為第一電極和第二電極)和位於重佈層結構的低介電常數(k4)之金屬層間介電層旁的高介電常數(k20)電容介電材料層的片段(segments)所組成。電容結構被設計來增加高介電常數電容介電材料層的介電常數(k)，或減低第一電極、第二電極和高介電常數電容介電材料層的厚度，如此以獲得較大的電容值。或者，電容結構被設計成具有鋸齒狀的電極和鋸齒狀的電容介電層，以增加電容結構的面積，藉此增加電容值。內嵌式MIM電容結構的製程可與重佈層結構的製程整合。因此，MIM電容結構可提供相當程度的製程相容性。此外，半導體封裝組件甚至可在半導體晶片(例如SOC晶片)被取代時，有助於改善表面安裝技術(SMT)的良率。此外，由於縮短了半導體晶片(系統晶片)和MIM電容結構間的傳導路徑，因此改善內嵌式MIM電容結構的信號完整性/電源完整性(SI/PI)的效能。內嵌式MIM電容結構可提供半導體封裝組件之系統整合的設計彈性。
雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得 大抵相同結果皆可根據本揭露使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。
200‧‧‧基座
202‧‧‧晶片附著表面
302‧‧‧半導體晶片
300a‧‧‧半導體封裝
302a‧‧‧背面
302b‧‧‧正面
304‧‧‧接墊
306、320‧‧‧導電結構
308‧‧‧重佈層結構
310、312、352、354‧‧‧表面
314‧‧‧導線
316‧‧‧焊料遮罩層
318、456a‧‧‧金屬層間介電層
322‧‧‧導孔
350‧‧‧模塑料
450a‧‧‧MIM電容結構
452a‧‧‧第一導線
452a-1‧‧‧第一電極
454a‧‧‧第二導線
454a-1‧‧‧第二導線
458a、460a‧‧‧界面
500a‧‧‧半導體封裝組件
600a‧‧‧部分

Claims (41)

  1. 一種半導體封裝組件，包括：一第一半導體封裝，包括：一第一半導體晶片；以及一第一重佈層結構，與該第一半導體晶片耦合，其中該第一重佈層結構包括：一第一導線，位於一第一層水平高度；一第二導線，位於一第二層水平高度；以及一第一金屬層間介電層及位於該第一金屬層間介電層旁的一第二金屬層間介電層，其中該第一金屬層間介電層和該第二金屬層間介電層係設置於該第一導線與該第二導線之間。
  2. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝包括：一第一模塑料，圍繞該第一半導體晶片；以及一第一導電結構，設置於該第一重佈層結構上，且與該第一重佈層結構耦合。
  3. 如申請專利範圍第2項所述之半導體封裝組件，其中該第一導線係設置於靠近該第一半導體晶片處，其中該第二導線係設置於靠近該第一導電結構處。
  4. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一導線與該第二導線隔開。
  5. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一金屬層間介電層的介電常數小於五分之一倍的該第二金屬 層間介電層的介電常數。
  6. 如申請專利範圍第5項所述之半導體封裝組件，其中該第二金屬層間介電層的介電常數大於或等於20。
  7. 如申請專利範圍第6項所述之半導體封裝組件，其中在剖面圖中，該第一金屬層間介電層的一第一厚度大於該第二金屬層間介電層的一第二厚度。
  8. 如申請專利範圍第7項所述之半導體封裝組件，其中該第二厚度小於或等於4μm。
  9. 如申請專利範圍第6項所述之半導體封裝組件，其中在剖面圖中，該第二金屬層間介電層為鋸齒形。
  10. 如申請專利範圍第9項所述之半導體封裝組件，其中在剖面圖中，與該第二金屬層間介電層接觸的該第一導線的一第一部分和該第二導線的一第二部分為鋸齒形。
  11. 如申請專利範圍第2項所述之半導體封裝組件，其中該第一半導體封裝包括：一第二重佈層結構，設置於該第一半導體晶片上，其中該第一模塑料具有兩個相對的表面，分別與該第一重佈層結構和該第二重佈層結構接觸；以及一第一導孔，穿過位於該第一重佈層結構與該第二重佈層結構間的該第一模塑料，其中該第一導孔圍繞該第一半導體晶片。
  12. 如申請專利範圍第1項所述之半導體封裝組件，其中該第一半導體封裝更包括：一第二半導體晶片，與該第一重佈層結構耦合，其中該第 一半導體晶片與該第二半導體晶片係並列排列。
  13. 如申請專利範圍第11項所述之半導體封裝組件，更包括：一第二半導體封裝，堆疊在該第一半導體封裝上，包括：一第三重佈層結構；一第二半導體晶片，與該第三重佈層結構耦合；以及一第二模塑料，圍繞該第二半導體晶片，並且與該第三重佈層結構和該第二半導體晶片接觸。
  14. 如申請專利範圍第13項所述之半導體封裝組件，其中該第二重佈層結構設置於該第一重佈層結構和該第三重佈層結構之間。
  15. 如申請專利範圍第13項所述之半導體封裝組件，其中該第二半導體封裝包括：一第二導電結構，設置於該第三重佈層結構的一遠離於該第二半導體晶片的表面上，其中該第二導電結構與該第三重佈層結構耦合。
  16. 如申請專利範圍第13項所述之半導體封裝組件，其中該第一半導體封裝係一系統晶片封裝，且該第二半導體封裝係一動態隨機存取記憶體封裝。
  17. 如申請專利範圍第13項所述之半導體封裝組件，其中該第二半導體封裝更包括：一第三半導體晶片，與該第三重佈層結構耦合，其中該第二半導體晶片與該第三半導體晶片係並列排列。
  18. 一種半導體封裝組件，包括：一第一半導體封裝，包括： 一第一半導體晶片；以及一第一重佈層結構，與該第一半導體晶片耦合，其中該第一重佈層結構包括：一第一導線，位於一第一層水平高度；一第二導線，位於一第二層水平高度；一第一金屬層間介電層和一第二金屬層間介電層，設置於該第一導線與該第二導線之間；以及一電容結構，由該第一導線、該第二導線及該第二金屬層間介電層組成，其中該第一金屬層間介電層的介電常數小於五分之一倍的該第二金屬層間介電層的介電常數。
  19. 如申請專利範圍第18項所述之半導體封裝組件，其中該第二金屬層間介電層位於該第一金屬層間介電層旁，其中該第二金屬層間介電層係設置於該第一導線與該第二導線之間。
  20. 如申請專利範圍第18項所述之半導體封裝組件，其中該第一半導體封裝包括：一第一模塑料，圍繞該第一半導體晶片；一第一導孔，穿過該第一模塑料，其中該第一導孔圍繞該第一半導體晶片；以及一第一導電結構，設置於該第一重佈層結構上且與該第一重佈層結構耦合。
  21. 如申請專利範圍第18項所述之半導體封裝組件，其中該第一導線與該第二導線隔開。
  22. 如申請專利範圍第18項所述之半導體封裝組件，其中該第 二金屬層間介電層的介電常數大於或等於20。
  23. 如申請專利範圍第18項所述之半導體封裝組件，其中在剖面圖中，該第一金屬層間介電層的一第一厚度大於該第二金屬層間介電層的一第二厚度。
  24. 如申請專利範圍第18項所述之半導體封裝組件，其中在剖面圖中，該第二金屬層間介電層為鋸齒形。
  25. 如申請專利範圍第24項所述之半導體封裝組件，其中在剖面圖中，與該第二金屬層間介電層接觸的該第一導線的一第一部分和該第二導線的一第二部分為鋸齒形。
  26. 如申請專利範圍第20項所述之半導體封裝組件，其中該第一半導體封裝包括：一第二重佈層結構，設置於該第一半導體晶片上，其中該第一模塑料具有兩個相對的表面，分別與該第一重佈層結構和該第二重佈層結構接觸。
  27. 如申請專利範圍第18項所述之半導體封裝組件，其中該第一半導體封裝更包括：一第二半導體晶片，與該第一重佈層結構耦合，其中該第一半導體晶片與該第二半導體晶片係並列排列。
  28. 如申請專利範圍第26項所述之半導體封裝組件，更包括：一第二半導體封裝，堆疊在該第一半導體封裝上，包括：一第三重佈層結構；一第二半導體晶片，與該第三重佈層結構耦合；一第二模塑料，圍繞該第二半導體晶片，並且與該第三重佈層結構和該第二半導體晶片接觸；以及 一第二導電結構，設置於該第三重佈層結構的一遠離於該第二半導體晶片的表面上，其中該第二導電結構與該第三重佈層結構耦合。
  29. 如申請專利範圍第28項所述之半導體封裝組件，其中該第二半導體封裝更包括：一第三半導體晶片，與該第三重佈層結構耦合，其中該第二半導體晶片與該第三半導體晶片係並列排列。
  30. 一種半導體封裝組件，包括：一第一半導體封裝，包括：一第一半導體晶片；以及一第一重佈層結構，與該第一半導體晶片耦合，其中該第一重佈層結構包括：一第一導線，位於一第一層水平高度；一第二導線，位於一第二層水平高度；一第一金屬層間介電層和一第二金屬層間介電層，設置於該第一導線與該第二導線之間；以及一電容結構，由該第一導線、該第二導線及該第二金屬層間介電層組成，其中該第二金屬層間介電層的厚度小於或等於該第一導線和該第二導線的厚度。
  31. 如申請專利範圍第30項所述之半導體封裝組件，其中該第二金屬層間介電層位於該第一金屬層間介電層旁，其中該第二金屬層間介電層設置於該第一導線與該第二導線之間。
  32. 如申請專利範圍第30項所述之半導體封裝組件，其中該第 一半導體封裝包括：一第一模塑料，圍繞該第一半導體晶片；一第一導孔，穿過該第一模塑料，其中該第一導孔圍繞該第一半導體晶片；以及一第一導電結構，設置於該第一重佈層結構上且與該第一重佈層結構耦合。
  33. 如申請專利範圍第30項所述之半導體封裝組件，其中該第一導線與該第二導線隔開。
  34. 如申請專利範圍第30項所述之半導體封裝組件，其中該第一金屬層間介電層的介電常數小於五分之一倍的該第二金屬層間介電層的介電常數。
  35. 如申請專利範圍第30項所述之半導體封裝組件，其中在剖面圖中，該第一金屬層間介電層的一第一厚度大於該第二金屬層間介電層的一第二厚度。
  36. 如申請專利範圍第30項所述之半導體封裝組件，其中在剖面圖中，該第二金屬層間介電層為鋸齒形。
  37. 如申請專利範圍第36項所述之半導體封裝組件，其中在剖面圖中，與該第二金屬層間介電層接觸的該第一導線的一第一部分和該第二導線的一第二部分為鋸齒形。
  38. 如申請專利範圍第32項所述之半導體封裝組件，其中該第一半導體封裝包括：一第二重佈層結構，設置於該第一半導體晶片上，其中該第一模塑料具有兩個相對的表面，分別與該第一重佈層結構接觸和該第二重佈層結構接觸。
  39. 如申請專利範圍第30項所述之半導體封裝組件，其中該第一半導體封裝更包括：一第二半導體晶片，與該第一重佈層結構耦合，其中該第一半導體晶片與該第二半導體晶片係並列排列。
  40. 如申請專利範圍第38項所述之半導體封裝組件，更包括：一第二半導體封裝，堆疊在該第一半導體封裝上，包括：一第三重佈層結構；一第二半導體晶片，與該第三重佈層結構耦合；一第二模塑料，圍繞該第二半導體晶片，並且與該第三重佈層結構和該第二半導體晶片接觸；以及一第二導電結構，設置於該第三重佈層結構的一遠離於該第二半導體晶片的表面上，其中該第二導電結構與該第三重佈層結構耦合。
  41. 如申請專利範圍第40項所述之半導體封裝組件，其中該第二半導體封裝更包括：一第三半導體晶片，與該第三重佈層結構耦合，其中該第二半導體晶片與該第三半導體晶片係並列排列。
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