CN113809052A - 半导体封装装置 - Google Patents

半导体封装装置 Download PDF

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CN113809052A
CN113809052A CN202011059895.8A CN202011059895A CN113809052A CN 113809052 A CN113809052 A CN 113809052A CN 202011059895 A CN202011059895 A CN 202011059895A CN 113809052 A CN113809052 A CN 113809052A
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decoupling
semiconductor package
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substrate
memory chip
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杨吴德
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体封装装置，包括基板、存储器芯片、去耦阵列。基板具有上表面、电源端、接地端。存储器芯片位于基板的上表面，且存储器芯片具有电源焊垫，而电源焊垫经由节点电性连接至电源端以接收电力。去耦阵列设置于基板的上表面，而去耦阵列包括并联的多个去耦电容器。各个去耦电容器电性连接于节点和接地端之间，以便于分流从电源端传输至存储器芯片的电力。

Description

半导体封装装置
技术领域
本发明涉及一种半导体封装装置。更具体的，是指能调节输入电力的半导体封装装置。
背景技术
半导体芯片有关的技术发展中，芯片尺寸的缩小是主要趋势。随着半导体芯片的需求快速增长，用于容纳内部元件的空间也逐渐减小。
在半导体封装领域，由于封装体内部空间不足，电压调节器不能应用在具有小型半导体芯片的半导体封装装置中。因此，耗能高的小尺寸半导体芯片会受到外部电力和自身杂讯所引起的负面影响。
从以上描述可知，有必要开发一种半导体封装装置，以实现体积缩小、同时调节外部电力并降低杂讯的负面影响。
发明内容
本发明的目的在于提供一种可以分流从电源端传输至存储器芯片电力的半导体封装装置。
本发明的其中一个实施方式是关于一种半导体封装装置包括基板、存储器芯片、去耦阵列。基板具有上表面、电源端、接地端。存储器芯片位于基板的上表面，且存储器芯片具有电源焊垫，而电源焊垫经由节点电性连接至电源端以接收电力。去耦阵列设置于基板的上表面，而去耦阵列包括并联的多个去耦电容器。各个去耦电容器电性连接于节点和接地端之间。
在本发明的一个或多个实施方式中，存储器芯片还包括接地焊垫，而接地焊垫电性连接基板的接地端。
在本发明的一个或多个实施方式中，去耦电容器的电容值大于或等于0.47uF。
在本发明的一个或多个实施方式中，去耦阵列包括至少22个这些去耦电容器。
在本发明的一个或多个实施方式中，去耦阵列的电容值大于或等于10uF。
在本发明的一个或多个实施方式中，去耦电容器中的任一个与存储器芯片相隔的第一距离小于去耦电容器与基板的对应边缘相隔的第二距离。
在本发明的一个或多个实施方式中，去耦阵列包括两个去耦电容器群组，而存储器芯片位于两个去耦电容器群组之间。
在本发明的一个或多个实施方式中，两个去耦电容器群组分别排列为两条直行。
在本发明的一个或多个实施方式中，两个去耦电容器群组分别排列为两条平行的直行。
在本发明的一个或多个实施方式中，两个去耦电容器群组的电容值皆大于或等于5μF。
在本发明的一个或多个实施方式中，两个去耦电容器群组皆包括至少11个去耦电容器。
在本发明的一个或多个实施方式中，存储器芯片包括多个金属焊垫，金属焊垫分别电性连接去耦电容器，且金属焊垫设置于存储器芯片的第一表面。
在本发明的一个或多个实施方式中，存储器芯片的第一表面接触基板的上表面，且基板具有开口露出金属焊垫。
在本发明的一个或多个实施方式中，基板具有导线结构电性连接去耦电容器、电源端及接地端，让去耦电容器电性连接于节点与接地端之间。
在本发明的一个或多个实施方式中，金属焊垫经由纳米金属线电性连接至导线结构。
在本发明的一个或多个实施方式中，半导体封装装置还包括压模结构，其中压模结构覆盖存储器芯片及去耦电容器。
综上所述，本发明的半导体封装装置具有去耦阵列，而去偶阵列是由多个去耦电容器所组成，去耦电容器彼此电性连接以增加去耦阵列的电容值，以便于分流所输入的电力，进而让半导体封装装置的芯片在接收较高压电力时仍维持正常功能。在另一方面，半导体封装装置包括面朝下的封装结构，且去耦电容器排列为两个平行的直行，芯片则位于去耦电容器所排成的两个平行的直行之间。借此，可以降低容纳去耦电容器的所需要的空间，而有助于半导体封装装置朝微型化发展。
附图说明
为描述获得本发明上述或其它的优点和特征，将通过参考其具体实施方式对上述简要描述的原理进行更具体的阐释，而具体实施方式被展现在附图中。这些附图仅例示性地描述本发明，因此不被认为是对范围的限制。通过附图，本发明的原理会被清楚解释，且附加的特征和细节将被完整描述，其中：
图1是根据本发明一些实施方式所绘示半导体封装装置的立体示意图；
图2绘示为图1中，半导体封装装置的上视示意图；
图3绘示为图2中，半导体封装装置沿着截面线3-3绘制的截面图；以及
图4绘示为图1中，半导体封装装置的电路图。
主要附图标记说明：
100-半导体封装装置，110-基板，110a-上表面，110b-对应边缘，111-开口，113-电源端，115-接地端，117-节点，119-导线结构，130-存储器芯片，131-金属焊垫，131a-电源焊垫，131b-接地焊垫，150-去耦阵列，150a-去耦电容器，170-压模结构，D1-第一距离，D2-第二距离。
具体实施方式
本发明可以以许多不同的形式实施。代表性实施例在附图中示出，并且将在本文中详细描述。本公开包含原理的示例或说明，并且本发明公开的实施例将不受限于所示的实施例。
请参考图1至图4。图1绘示为半导体封装装置100的立体示意图。图2绘示为图1中，半导体封装装置100的上视示意图。图3绘示为图2中，半导体封装装置100沿着截面线3-3绘制的截面图。图4绘示为图1中，半导体封装装置100的电路图。在本发明的一个实施方式中，半导体封装装置100包括基板110、存储器芯片130、去耦阵列150。基板110具有上表面110a、电源端113、接地端115，其中电源端113可电性连接外部电源。存储器芯片130位于基板110的上表面110a上，且存储器芯片130具有电源焊垫131a，而电源焊垫131a经由节点117电性连接至电源端113以接收电力。去耦阵列150设置于基板110的上表面110a，去耦阵列150包括并联的多个去耦电容器150a，而去耦电容器150a电性连接于节点117和接地端115之间。此外，存储器芯片130具有接地焊垫131b，且接地焊垫131b电性连接至基板110的接地端115。
去耦阵列150可以分流从电源端113传输至存储器芯片130的电力，进而防止瞬态电流损坏存储器芯片130。此外，多个去耦电容器150a相互并联，因此当去耦电容器150a的数量增加时，去耦阵列150的电容值也会上升。也就是说，去耦阵列150可以从电源端113分流更高压的电力。
具体而言，基板110可以为铜箔基板(copper clad laminate,CCL)。存储器芯片130可以为动态随机存取存储器芯片(dynamic random access memory,DRAM)。去耦阵列150的去耦电容器150a可以为陶瓷电容器(ceramic capacitor)，但本发明不以此为限。
基板110包括具有铜导线的导线结构119。导线结构119电性连接去耦电容器150a、电源端113以及接地端115，因此各去耦电容器150a电性连接于节点117与接地端115之间。电源端113及接地端115可以包括焊球(solder ball)以接收和传输电力和电信号。焊球位于基板110的底面110c，且焊球更电性连接导线结构119。
半导体封装装置100还包括压模结构170，其中压模结构170以虚线绘示在图1，但省略于图2。压模结构170位于基板110的上表面110a上，而压模结构170覆盖并包覆存储器芯片130及去耦电容器150a。其中，压模结构170包括环氧树脂模制化合物(epoxy moldingcompound)以保护存储器芯片130及去耦电容器150a。但本发明并不以此为限。
在本发明的一些实施方式中，存储器芯片130还包括多个金属焊垫131，而金属焊垫131分别电性连接去耦电容器150a。金属焊垫131、电源焊垫131a及接地焊垫131b皆位于存储器芯片130的第一表面130a。存储器芯片130的第一表面130a接触基板110的上表面110a，而基板110更具有开口111，开口111曝露金属焊垫131、电源焊垫131a及接地焊垫131b。因此，半导体封装装置100为一个面朝下(face-down)的芯片封装结构，以便于半导体封装装置100缩小体积。此外，金属焊垫131是透过纳米金属线电性连接导线结构119，例如是由打线接合(wire bonding)产生的纳米金属线，但本发明并不以此为限。
在本发明的一些实施方式中，半导体封装装置100的去耦阵列150包括至少22个去耦电容器150a，而各个去耦电容器150a的电容值大于或等于0.47uF。因此，去耦阵列150的电容值大于或等于10uF，以便于对来自电源端113的电力进行分流。
具体而言，去耦阵列150包括两个去耦电容器群组(去耦电容器150a所组成的群组)，而存储器芯片130位于两个去耦电容器群组之间)。其中，两个去耦电容器群组的电容值皆大于或等于5μF，故去耦阵列150的电容值大于或等于10μF。
除此之外，两个去耦电容器群组皆包括至少11个去耦电容器150a，且两个去耦电容器群组分别排列为两条平行的直行。藉由前述的配置关系，半导体封装装置100容置去耦电容器150a的所需空间较小，因此有助于实现微型化的目标。
在本发明的一些实施方式中，去耦电容器150a与存储器芯片130相隔第一距离D1，去耦电容器150A与基板110的对应边缘110b相隔第二距离D2，其中第一距离D1小于第二距离D2。详细来说，对应边缘110b指的是与所选择的去耦电容器150最靠近的基板110的边缘。此外，第一距离D1是指所选择的去耦电容器150a到存储器芯片130的最短距离。第二距离D2是指去耦电容器150a到基板110的对应边缘110b的最短距离。
综上所述，本发明的半导体封装装置具有去耦阵列，而去偶阵列是由多个去耦电容器所组成，去耦电容器彼此电性连接以增加去耦阵列的电容值，以便于分流所输入的电力，进而让半导体封装装置的芯片在接收较高压电力时仍维持正常功能。在另一方面，半导体封装装置包括面朝下的封装结构，且去耦电容器排列为两个平行的直行，芯片则位于去耦电容器所排成的两个平行的直行之间。借此，可以降低容纳去耦电容器的所需要的空间，而有助于半导体封装装置朝微型化发展。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (16)

1.一种半导体封装装置，其特征在于，包括：
基板，具有上表面、电源端及接地端；
存储器芯片，设置于所述基板的所述上表面上并具有电源焊垫，其中电源焊垫经由节点连接至所述电源端；及
去耦阵列，设置于所述基板的所述上表面上，其中所述去耦阵列包括并联的多个去耦电容器，且所述多个去耦电容器电性连接于所述节点与所述接地端之间。
2.如权利要求1所述的半导体封装装置，其特征在于，所述存储器芯片还包括接地焊垫，所述接地焊垫电性连接所述基板的所述接地端。
3.如权利要求1所述的半导体封装装置，其特征在于，所述多个去耦电容器的电容值大于或等于0.47uF。
4.如权利要求1所述的半导体封装装置，其特征在于，所述去耦阵列包括至少22个所述去耦电容器。
5.如权利要求1所述的半导体封装装置，其特征在于，所述去耦阵列的电容值大于或等于10uF。
6.如权利要求1所述的半导体封装装置，其特征在于，所述多个去耦电容器中的任一个与所述存储器芯片相隔的第一距离小于所述多个去耦电容器的所述任一个与所述基板的对应边缘相隔的第二距离。
7.如权利要求1所述的半导体封装装置，其特征在于，所述去耦阵列包括两个去耦电容器群组，而所述存储器芯片位于所述两个去耦电容器群组之间。
8.如权利要求7所述的半导体封装装置，其特征在于，所述两个去耦电容器群组分别排列为两条直行。
9.如权利要求7所述的半导体封装装置，其特征在于，所述两个去耦电容器群组分别排列为两条平行的直行。
10.如权利要求7所述的半导体封装装置，其特征在于，所述两个去耦电容器群组的电容值皆大于或等于5μF。
11.如权利要求7所述的半导体封装装置，其特征在于，所述两个去耦电容器群组皆包括至少11个所述去耦电容器。
12.如权利要求7所述的半导体封装装置，其特征在于，所述存储器芯片包括多个金属焊垫，所述多个金属焊垫分别电性连接所述多个去耦电容器，且所述多个金属焊垫设置于所述存储器芯片的第一表面。
13.如权利要求12所述的半导体封装装置，其特征在于，所述存储器芯片的所述第一表面接触所述基板的所述上表面，且所述基板具有开口露出所述多个金属焊垫。
14.如权利要求12所述的半导体封装装置，其特征在于，所述基板具有导线结构电性连接所述多个去耦电容器、所述电源端及所述接地端，让所述多个去耦电容器电性连接于所述节点与所述接地端之间。
15.如权利要求14所述的半导体封装装置，其特征在于，所述多个金属焊垫经由纳米金属线电性连接至所述导线结构。
16.如权利要求14所述的半导体封装装置，其特征在于，还包括压模结构，其中所述压模结构覆盖所述存储器芯片及所述多个去耦电容器。
CN202011059895.8A 2020-06-11 2020-09-30 半导体封装装置 Pending CN113809052A (zh)

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