TWI717032B - 製作半導體元件的方法及半導體元件 - Google Patents
製作半導體元件的方法及半導體元件 Download PDFInfo
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- TWI717032B TWI717032B TW108134723A TW108134723A TWI717032B TW I717032 B TWI717032 B TW I717032B TW 108134723 A TW108134723 A TW 108134723A TW 108134723 A TW108134723 A TW 108134723A TW I717032 B TWI717032 B TW I717032B
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- Prior art keywords
- gate stack
- etching
- side wall
- gate
- free radicals
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
一種方法,包括以下步驟:提供一種結構,此結構具有基板及從基板突出的鰭狀物;在鰭狀物上方形成虛設閘極堆疊;在虛設閘極堆疊的側壁上形成閘極間隔物;使用自由基蝕刻製程去除虛設閘極堆疊,產生閘極溝槽;以及在閘極溝槽中形成金屬閘極堆疊。
Description
本揭示係關於製作半導體元件的方法及半導體元件。
半導體積體電路(integrated circuit;IC)行業已經經歷了指數級增長。IC材料及設計的技術進步已經生產了數代IC,其中每一代都具有比上一代更小及更複雜的電路。在IC進化的過程中,幾何尺寸(即,使用製造製程可製造的最小元件(或線路))減小的同時,功能密度(即,單位晶片面積的互連元件的數目)大致增加。這種按比例縮小製程大體藉由提高生產效率及降低關聯成本而提供益處。此種按比例縮小亦增加處理及製造IC的複雜性。
在一些IC設計中,隨著技術節點縮小而實現的一個進步為用金屬閘極置換典型多晶矽閘極以提高特徵尺寸減小的元件效能。形成金屬閘極的一個製程稱為置換閘極製程或「閘極最後」製程,其中在已經去除多晶矽閘極之後
製造金屬閘極,其允許必須在形成閘極之後執行的後續製程數量減少,包括高溫處理。然而,實施此種IC製造製程,尤其在進階製程節點中具有按比例縮小的IC特徵情況下,具有挑戰。在一個實例中,在去除多晶矽閘極期間,可損壞閘極間隔物的側壁,產生非筆直側壁輪廓。因此,在此領域中需要改進。
本揭示內容的一態樣係提供一種製作半導體元件的方法,包括以下步驟:提供一結構,此結構具有基板及從基板突出的鰭狀物;在鰭狀物上方形成虛設閘極堆疊;在虛設閘極堆疊的側壁上形成閘極間隔物;使用自由基蝕刻製程去除虛設閘極堆疊,產生閘極溝槽;以及在閘極溝槽中形成金屬閘極堆疊。
本揭示內容的另一態樣係提供一種製作半導體元件的方法,包括以下步驟:在製程腔室的蝕刻處理區域中接收一結構,結構包括在基板上方的虛設閘極堆疊及在虛設閘極堆疊的側壁上的閘極間隔物;在製程腔室的電漿區域中用前驅物氣體生成電漿,電漿包括自由基及帶電離子;使該等自由基流進蝕刻處理區域中,而基本上排除該等帶電離子進入蝕刻處理區域;用該等自由基蝕刻虛設閘極堆疊,產生閘極溝槽;以及在閘極溝槽中形成金屬閘極堆疊。
本揭示內容的又一態樣係提供一種半導體元件,包括基板、鰭狀物、閘極堆疊及閘極間隔物。鰭狀物從
基板突出,鰭狀物在第一方向上縱向延伸。閘極堆疊接合鰭狀物,閘極堆疊在垂直於第一方向的第二方向中縱向延伸。閘極間隔物在閘極堆疊的側壁上,閘極間隔物包括與閘極堆疊的側壁直接連接的內側壁及與內側壁相對的外側壁,在橫截面視圖中沿第一方向內側壁具有第一高度以及弓形結構朝向閘極堆疊延伸第一橫向距離,第一橫向距離為沿第一方向自內側壁的中點測量的,其中在橫截面視圖中沿第一方向,外側壁具有低於內側壁的第一高度的第二高度。
100:方法
102、104、106、108、110、112、114、116:操作
112a、112b、112c、112d、112e:步驟
200:半導體元件
202:基板
204:鰭狀物
206:隔離結構
212:虛設(或暫態)閘極堆疊
260:閘極間隔物
262:源極/汲極特徵
264:接觸蝕刻停止層
266:層間介電層
270:側壁
272:閘極溝槽
278:覆蓋膜
280:高介電常數金屬閘極堆疊
282:高介電常數介電層
284:導電層
286:介電層
288:S/D觸點
300、300':製程腔室
310:真空腔室
310a:電漿區域
310b:蝕刻處理區域
320:真空源
322:通道
330:卡盤
332:偏壓電源
334:介電頂蓋
336:電極
338:射頻(RF)電源
340:隔離構件
342:氣體注射器
343:前驅物氣體
344:電漿
346:偏置電場
370:選擇性調變元件
372:氣體注射器
374:第二前驅物氣體
380p:正離子
380n:負離子
380r:自由基
450:第一前驅物氣體
當結合附圖閱讀時,根據以下詳細描述可更好地理解本揭示案。應強調,根據工業標準實踐,各種特徵未按比例繪製並且僅用作說明目的。事實上,為論述清楚,各特徵的尺寸可任意地增加或縮小。
第1圖及第2圖圖示根據本揭示案的態樣的用於形成半導體元件的方法的流程圖。
第3圖、第4圖、第5圖、第6圖、第7A圖、第7B圖、第8A圖、第8B圖、第10A圖、第10B圖、第12A圖、第12B圖、第13A圖、第13B圖、第14A圖、第14B圖、及第15圖圖示根據一些實施例的在根據第1圖及第2圖的方法的製造製程期間的半導體元件的橫截面視圖。
第9圖及第11圖圖示根據本揭示案的態樣的在根據第1圖及第2圖的方法的蝕刻製程中使用的示例製程腔室。
以下揭示內容提供許多不同實施例或實例,以便實現各個實施例的不同特徵。下文描述組件及排列的特定實例以簡化本揭示內容。當然,此等實例僅為實例且不意欲為限制性。舉例而言,在隨後描述中在第二特徵上方或在第二特徵上第一特徵的形成可包括第一及第二特徵形成為直接接觸的實施例,以及亦可包括額外特徵可形成在第一及第二特徵之間,使得第一及第二特徵可不直接接觸的實施例。另外,本揭示案在各實例中可重複元件符號及/或字母。此重複為出於簡單清楚的目的,且本身不指示所論述各實施例及/或配置之間的關係。
另外,空間相對用語,諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者,在此為便於描述可用於描述諸圖中所圖示一個元件或特徵與另一(些)元件或(多個)特徵的關係。除圖形中描繪的方向外,空間相對用語意圖是包含元件在使用或操作中的不同方向。設備可為不同朝向(旋轉90度或在其他的方向)及可因此同樣地解釋在此使用的空間相對的描述詞。更進一步,當用「約」、「近似」等描述數值或數值範圍時,術語旨在包含在包括在所述數字的+/-10%內的數值,除非另外說明。例如,術語「約5nm」包含自4.5nm變化至5.5nm的尺寸。
本揭示大體係關於半導體元件及製造方法,並且更特定言之係關於使用選擇性自由基蝕刻製程形成電晶體閘極。在置換閘極製程或「閘極最後(gate-last)」製程
中,虛設閘極去除製程之後的閘極間隔物的側壁輪廓定義後續形成的金屬閘極的側壁輪廓。非筆直閘極間隔物的側壁輪廓可包括弓形頂部、延伸的基部、及/或彎曲側壁,其將產生鄰接閘極間隔物的金屬閘極的類似側壁輪廓。這可不利地影響金屬閘極的效能的均勻性。一些實施例提供在虛設閘極去除製程期間具有大體上筆直側壁的閘極間隔物。雖然示例性方法特定應用於處理鰭式場效電晶體(fin field-effect transistor,FinFET)半導體元件,但其亦可用於其他應用中,諸如從其他工件(諸如平面電晶體及類似物)選擇性去除不同材料層。
第1圖及第2圖圖示根據本揭示的不同態樣的用於形成半導體元件的方法100的流程圖。方法100僅為示例,並且不意圖將本揭示限制於申請專利範圍中明確敘述的內容之外。可以在方法100之前、期間及之後提供附加的操作,並且可以替換、消除或移動所描述的一些操作以獲得此方法的附加實施例。方法100結合第3圖至第15圖在下文描述。第3圖至第8B圖、第10A圖、第10B圖、及第12A圖至第15圖圖示根據方法100的製造步驟期間的半導體元件200的不同橫截面視圖。第9圖及第11圖圖示適於在方法100的某些操作中使用的各種示例性蝕刻製程腔室。
在操作102處,方法100(第1圖)提供(或具備)具有基板202的半導體元件200,如在第3圖中所示。在圖示的實施例中基板202為矽基板。或者,基板202可包含另一元素半導體,諸如鍺;包括碳化矽、氮化鎵、砷化鎵、
磷化鎵、磷化銦、砷化銦、及銻化銦的化合物半導體;包括矽鍺、磷化鎵砷、磷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵、及磷化砷銦鎵的合金半導體;及/或類似物。在另一實施例中,基板202包括氧化銦錫(ITO)玻璃。在實施例中,基板202可為晶圓,諸如矽晶圓,並且可包括在其上部的一或多個磊晶生長的半導體層。
在操作104處,方法100(第1圖)形成從基板202向上突起的鰭狀物204,如第4圖所示。在圖示實施例中,鰭狀物204沿X方向縱向延伸並且在Y方向彼此間隔開。此外,鰭狀物204大體彼此平行。鰭狀物204可以藉由在基板202的整個區域上方磊晶生長一或多個半導體層形成並且隨後經圖案化以形成個別鰭狀物204。鰭狀物204可藉由任何適當方法圖案化。例如,鰭狀物204可以使用包括雙圖案化或多圖案化製程的一或多個光微影製程來圖案化。大體上,雙圖案化或多圖案化製程結合光微影及自對準製程,從而允許產生的圖案的間距小於例如使用單個、直接的光微影製程獲得的間距。例如,在一個實施例中,犧牲層形成於基板上方並且使用光微影製程圖案化。間隔物使用自對準製程沿所圖案化的犧牲層形成。接著去除犧牲層,並且剩餘的間隔物或心軸隨後可用以藉由蝕刻初始磊晶半導體層來圖案化鰭狀物204。蝕刻製程可以包括乾式蝕刻、濕式蝕刻、活性離子蝕刻(reactive ion etching,RIE)及/或其他適當製程。例如,乾式蝕刻製程可實施含氧氣體、含氟氣體(例如,CF4、SF6、CH2F2、CHF3、及/或C2F6)、含
氯氣體(例如,Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(例如,HBr及/或CHBR3)、含碘氣體,其他適宜氣體及/或電漿,及/或上述組合。例如,濕式蝕刻製程可包括在稀釋的氫氟酸(diluted hydrofluoric acid;DHF)中;氫氧化鉀(KOH)溶液;氨;包含氫氟酸(HF)、硝酸(HNO3)及/或乙酸(CH3COOH)的溶液中;或其他適當蝕刻劑中蝕刻。
在一些實施例中,鰭狀物204可包含一或多種半導體材料,諸如矽、鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、矽鍺、磷化鎵砷、磷化銦鋁、砷化鎵鋁、砷化銦鎵、磷化銦鎵及磷化砷銦鎵。在實施例中,鰭狀物204可以包括兩種不同半導體材料的交替堆疊層,諸如矽及矽鍺交替堆疊的層。鰭狀物204可以另外包括用於提高半導體元件200的效能的摻雜劑。例如,鰭狀物204可以包括n型摻雜劑,諸如磷或砷,或者p型摻雜劑,諸如硼或銦。
在操作106處,方法100(第1圖)圍繞鰭狀物204形成隔離結構206。操作106可包括各種製程,諸如沉積(例如,FCVD)、退火、化學機械平坦化(chemical mechanical planarization,CMP)、及回蝕(etching back)。隔離結構206的材料可以包括純的矽玻璃(undoped silicate glass,USG)、氟化物摻雜矽玻璃(fluoride-doped silicate glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(borophosphosilicate glass,BPSG),或其他適當的絕緣材料。例如,操作206可在基板
202上方沉積可流動介電材料及在鰭狀物204之間填充間隙,諸如第5圖所示。在一些實施例中,可流動介電材料的沉積步驟包括引入含矽化合物及含氧化合物(其反應以形成可流動介電材料),從而填充縫隙。隨後,操作106利用一些退火製程處理可流動材料以將可流動介電材料轉換成固態介電材料。退火製程可包括在約400℃至約550℃範圍中的溫度下的乾式退火或濕式退火。此後,操作106執行一或多個CMP製程及/或回蝕製程以凹進隔離結構206。例如,操作106可在不同實施例中使用一或多個濕式蝕刻、乾式蝕刻、活性離子蝕刻、或其他適當蝕刻方法,以凹進隔離結構206以暴露鰭狀物204的上部,如第6圖所示。
在操作108,方法100(第1圖)形成接合鰭狀物204的虛設(或暫態)閘極堆疊212,諸如第7A圖及第7B圖所示。第7A圖圖示Y-Z平面中的半導體元件200的橫截面視圖,而第7B圖圖示X-Z平面中的半導體元件200的橫截面視圖。在圖示的實施例中,虛設閘極堆疊212沿Y方向縱向延伸,Y方向垂直於鰭狀物204的縱向方向。虛設閘極堆疊212將隨後在閘極最後製程中由最終閘極堆疊(諸如高介電常數金屬閘極堆疊)替代。在一些實施例中,每個虛設閘極堆疊212包括虛設閘極介電層及虛設閘電極層(未圖示)。虛設閘極介電層形成於暴露的鰭狀物204上方。虛設閘極介電層可藉由熱氧化、CVD、濺射、或在用於形成虛設閘極介電層的領域中已知並使用的任何其他方法而形成。在一個實施例中,虛設閘極介電層由與隔離結構206相同的材料形
成。在其他實施例中,虛設閘極介電層可由一或多種適當介電材料組成,諸如氧化矽(例如,SiO2)、氮化矽(例如,Si3N4)、氮氧化矽(例如,SiON)、諸如碳摻雜氧化物的低介電常數介電質、諸如多孔碳摻雜二氧化矽的極低介電常數介電質、諸如聚醯亞胺的聚合物、類似物、或上述組合。在其他實施例中,虛設閘極介電層包括具有高介電常數(k值)(例如,大於3.9)的介電材料。材料可包括金屬氧化物,諸如HfO2、HfZrOx、HfSiOx、HfTiOx、HfAlOx、TiN、類似物、或上述組合。隨後,虛設閘電極層形成於虛設閘極介電層上方。在一些實施例中,虛設閘電極層為導電材料,並且可從包括以下的組群中選出:多晶矽(聚矽)、多晶矽鍺(聚SiGe)、氮化矽(例如,Si3N4)、金屬氮化物、金屬矽化物、及金屬氧化物。在實施例中,虛設閘電極層可藉由PVD、CVD、濺射沉積、或在用於沉積導電材料的領域中已知並使用的其他方法而沉積。虛設閘電極層的頂表面通常具有非平面頂表面,並且可在虛設閘電極層沉積之後用一或多個CMP製程來平坦化。虛設閘極介電層及虛設閘電極層可藉由光微影及蝕刻製程來圖案化以形成虛設閘極堆疊212。
在操作110,方法100(第1圖)在鰭狀物204中或上方形成各種特徵,包括閘極間隔物260、源極/汲極(source/drain,S/D)特徵262、接觸蝕刻停止層(contact etch stop layer,CESL)264、層間介電(interlayer dielectric,ILD)層266,諸如第8A圖及第8B圖所示。第8A
圖圖示Y-Z平面中的半導體元件200的橫截面視圖,而第8B圖圖示X-Z平面中的半導體元件200的橫截面視圖。操作110包括各種製程。
在一些實施例中,操作110在虛設閘極堆疊212的側壁上形成閘極間隔物260。在圖示的實施例中,在虛設閘極堆疊212的每個側面上形成閘極間隔物260。閘極間隔物260可用以偏置(offset)後續形成的S/D特徵262。閘極間隔物260可包含介電材料,諸如氧化矽、氮化矽、氮氧化矽、碳化矽、其他介電材料、或上述組合,並且可包含一或多個材料層。閘極間隔物260可藉由在隔離結構206、鰭狀物204及虛設閘極堆疊212上方沉積間隔物材料作為毯層而形成。接著藉由各向異性蝕刻製程來蝕刻間隔物材料。間隔物材料在虛設閘極堆疊212的側壁上的部分留下並變成閘極間隔物260。
然後,操作110在鰭狀物204上方形成S/D特徵262、在S/D特徵262上方形成CESL 264、在CESL 264上方形成ILD層266。例如,操作216可在與閘極間隔物260相鄰的鰭狀物204中蝕刻凹槽,並且在此凹槽中磊晶生長半導體材料。可將半導體材料提高至鰭狀物204頂表面上方。操作110可分別針對NFET及PFET元件形成S/D特徵262。例如,操作110可針對NFET元件形成具有n型摻雜矽的S/D特徵262,以及針對PFET元件形成具有p型摻雜矽鍺的S/D特徵262。在特定實施例中,S/D特徵262在磊晶製程期間藉由引入摻雜物質而原位摻雜,摻雜物質包括:p型摻雜
劑,諸如硼或BF2;n型摻雜劑,諸如磷或砷;及/或包括上述組合的其他適當摻雜劑。若S/D特徵262不為原位摻雜,則執行植入製程(即,接合植入製程)以摻雜S/D特徵262。例如,NFET元件中的S/D特徵262包括SiP,而PFET元件的S/D特徵262包括GeSnB(錫可用以調諧晶格常數)及/或SiGeSnB。可執行一或多個退火製程以活化S/D特徵262。適當退火製程包括快速熱退火(rapid thermal annealing,RTA)及/或雷射退火製程。
此後,操作110可在S/D特徵262上方沉積CESL 264及ILD層266。CESL 264可以包含氮化矽、氮氧化矽、具有氧(O)或碳(C)元素的氮化矽、及/或其他材料;並且可藉由CVD、PVD、ALD或其他適當方法形成。ILD層266可以包含正矽酸四乙酯(TEOS)氧化物、無摻雜矽玻璃、或摻雜氧化矽,諸如硼磷矽玻璃(borophosphosilicate glass,BPSG)、熔融石英玻璃(fused silica glass,F SG)、磷矽玻璃(phosphosilicate glass,PSG)、硼摻雜矽玻璃(boron doped silicon glass,BSG),及/或其他適當的介電材料。ILD層266可藉由電漿增強化學氣相沉積(plasma enhanced CVD,PECVD)、可流動CVD(flowable CVD,FCVD)或其他適當方法形成。在特定實施例中,閘極間隔物260富含氮化物,諸如主要包含氮化矽,而ILD層266富含氧化物,諸如主要包含氧化矽。隨後,操作110可執行一或多個CMP製程以平坦化半導體元件200的頂表面。
在操作112,方法100(第1圖)去除虛設閘極堆疊212以形成閘極溝槽。在不同實施例中,操作112使用乾式蝕刻製程。相對而言,實施乾式蝕刻製程的優點主要歸因於其控制氣態蝕刻劑的簡單性及其產生比其他製程(諸如濕式蝕刻方法)更具重複性結果的結果。在乾式蝕刻製程期間可變化或更改許多製程參數,諸如氣壓、化學物質、及源極/偏置功率以用於微調。
乾式蝕刻製程可使用各向異性蝕刻(例如,電漿蝕刻)或各向同性蝕刻(例如,自由基蝕刻,其中自由基藉由過濾電漿而生成)。在操作112的一個特定實施例中,各向異性蝕刻方法用以蝕刻虛設閘極堆疊212,諸如電漿蝕刻(或活性離子蝕刻(reactive-ion etching,RIE))。適於電漿蝕刻的示例性製程腔室300在第9圖中圖示。製程腔室300包括真空腔室310作為蝕刻處理區域。真空腔室310經由通道322與真空源320流體連通。真空源320可包括一或多個真空泵。真空源320在適當的低氣壓(例如,低於100mTorr)下可操作地維持真空腔室310的內部體積。製程腔室300亦包括用於固持半導體元件200的卡盤330。例如,卡盤330可為懸臂式的靜電卡盤(cantilevered electrostatic chuck),以及半導體元件200藉由靜電夾具、機械夾具、或其他夾緊機構而位於卡盤330上。卡盤330為導電的並電耦合至偏壓電源332。氣體注射器342提供前驅物氣體343以在真空腔室310內生成電漿。製程腔室300進一步包括具有安裝在其上的複數個電極336的介電頂蓋
334。介電頂蓋334及電極336可進一步藉由隔離構件340與真空腔室310的側面及底部隔離。電極336(諸如天線或平面線圈)由適當射頻(radio frequency,RF)電源338供電以將RF能量傳遞進真空腔室310中。RF能量可在真空腔室310中將前驅物氣體343激發成電漿344。耦合RF能量之偏壓源332為半導體元件200產生偏置電場346。藉由偏置電場346驅動,電漿344中的帶電離子類似濺射般地轟擊了半導體元件200的頂表面。轟擊加速了平行於離子軌道的蝕刻速率,從而產生各向異性蝕刻。在進一步實施例中,前驅物氣體343可包含CF4及Cl2的混合物(即,CF4/Cl2電漿)。或者,前驅物氣體343可包含HBr及O2的混合物(即,HBr/O2電漿)。蝕刻製程可以在約500sccm的CF4/Cl2(或HBr/O2)流速、約60mTorr的氣壓、小於約1000W的RF功率、及小於約200V的偏壓下應用。
本揭示的發明人已經觀察到,各向異性蝕刻製程期間的離子轟擊(ion bombardment)可對閘極間隔物260的側壁造成損壞,產生非筆直側壁,如第10A圖及第10B圖所示。第10A圖圖示Y-Z平面中的半導體元件200的橫截面視圖,而第10B圖圖示X-Z平面中的半導體元件200的橫截面視圖。如第10A圖及第10B圖圖示,閘極間隔物260的側壁270(面向閘極溝槽272)具有非筆直輪廓。非筆直輪廓可主要由轟擊期間從虛設閘極堆疊的頂表面反射的離子引起,反射後轟擊擊中側壁270。
如第10A圖圖示,將側壁270的中點M定義為至隔離結構206的頂表面具有一垂直距離的點,此垂直距離為閘極間隔物260的高度H1的一半(H1為從閘極間隔物260的最高部分至隔離結構206的頂表面垂直測量距離)。側壁270的中間部分具有圍繞中點M彎曲遠離閘極溝槽272的曲率形狀。側壁270的頂部具有朝向閘極溝槽272延伸第一橫向距離L1的弓形結構,第一橫向距離L1沿Y方向從中點M至弓形結構的尖端測量。側壁270的底部具有朝向閘極溝槽272延伸第二橫向距離L1'的基部結構,第二橫向距離L1'沿Y方向從中點M至基部結構的尖端測量。本揭示的發明者已經觀察到,各向異性蝕刻製程經常導致L1/H1及L1'/H1兩者都大於約8%。
類似地,如第10B圖圖示,將中點M'定義為側壁270上至鰭狀物204頂表面具有一垂直距離的點,此垂直距離為閘極間隔物260的高度H2的一半(H2為從閘極間隔物260的最高部分至鰭狀物204的頂表面垂直測量)。側壁270的中間部分具有圍繞中點M'彎曲遠離閘極溝槽272的曲率形狀。側壁270的頂部具有朝向閘極溝槽272延伸第二橫向距離L2的弓形結構,第二橫向距離L2沿X方向從中點M'至弓形結構的尖端測量。側壁270的底部具有朝向閘極溝槽272延伸第二橫向距離L2'的基部結構,第二橫向距離L2'沿X方向從中點M'至基部結構的尖端測量。本揭示案的發明者已經觀察到,各向異性蝕刻製程經常導致L2/H2及L2'/H2兩者都大於約8%。
在操作112的替代實施例中,如第2圖圖示,使用自由基的各向同性蝕刻方法用以蝕刻虛設閘極堆疊212,而不對半導體元件200施加偏置電場,以避免引起帶電離子轟擊。因此,此各向同性蝕刻方法亦稱為自由基蝕刻。如本文使用的術語「自由基」指示具有至少一個不成對價電子的原子或分子,並顯示為電中性。不成對電子使自由基具有高度化學反應性。如本文使用的術語「自由基蝕刻」指示一蝕刻製程,此蝕刻製程使用自由基作為蝕刻劑並且大體上排除帶電離子參與蝕刻。
適於自由基蝕刻的示例性製程腔室300'在第11圖中圖示。製程腔室300'具有重複元件符號的許多部件類似於第9圖中圖示的製程腔室300的對應者,並且下文為了簡明性不再重複。不同於製程腔室300,製程腔室300'並未將卡盤330偏置至電壓源。因而,位於卡盤330上的半導體元件200由偏置電場圍繞。此外,製程腔室300'的真空腔室310由選擇性調變元件370分成電漿區域310a及蝕刻處理區域310b。半導體元件200位於蝕刻處理區域310b中。製程腔室300'可進一步包括耦接至蝕刻處理區域310b的氣體注射器372以提供第二前驅物氣體374(非第一前驅物氣體343)進蝕刻處理區域310b中。
選擇性調變元件370可為充當阻障層的帶電光柵,其阻止來自電漿的帶電離子的運動,而允許不帶電電漿成分(例如,自由基)穿過選擇性調變元件370。在實施例中,選擇性調變元件370可藉由排斥帶電電漿離子或吸引帶
電電漿離子來防止帶電電漿離子(例如,帶正電離子或帶負電離子)穿過。然而,可使用將自由基與電漿分離的任何適當元件。
一起參照第2圖及第11圖,使用自由基蝕刻的操作112的一個實施例開始於步驟112a,其中半導體基板位於製程腔室300'的蝕刻處理區域310b中。在步驟112b中,在具有第一前驅物氣體343的電漿區域310a中生成電漿344。前驅物氣體343可包含一或多種第一氣態成分。在代表性實例中,第一前驅物氣體343可包含例如三氟化氮(NF3)作為氟自由基源;儘管可替代地、接合地、或順序地使用其他自由基源。例如,在另一代表性實例中,根據以下公式,第一前驅物氣體450可包含三氟化氮(NF3)作為氟自由基源及包含分子氫(H2)作為氫自由基源:NF3+H2→NF*+NF2*+F*+H*+HF+N*(*標記自由基成分)。第一前驅物氣體343經激發以形成電漿344,包括正離子380p、負離子380n及設置於在電漿區域310a中的自由基380r。例如,由RF電源338生成的RF(射頻)能量可用以形成電漿344。在一些實施例中,RF功率可在約10瓦特與約2500瓦特之間,諸如在約500瓦特與約1500瓦特之間。在特定實例中,RF功率為約1200瓦特。在一些實施例中,電漿344可在分隔區域(例如,在遠端電漿的情況下)生成,並隨後引入至電漿區域310a。在步驟112c,電漿344的自由基380r單獨地從電漿區域310a流至蝕刻處理區域310b。在圖示實施例中,選擇性調變元件370允許自由基
380r進入蝕刻處理區域310b中,而大體上將電漿344的正離子380p及負離子380n保持在電漿區域310a中。在步驟112d,將未激發氣體374作為第二前驅物引入至蝕刻處理區域310b中的自由基380r(並與自由基380r化學組合)。未激發氣體374可包含一或多種氣態成分。儘管第11圖代表性地圖示在引入未激發氣體374之前將自由基380r引入至蝕刻處理區域310b,但其他引入順序是可能的。例如,在一個實施例中,在自由基380r之前,可將未激發氣體374引入至蝕刻處理區域310b。在另一實施例中,可與引入自由基380r大體上同時地引入未激發氣體374。根據代表性實例,使用三氟化氮(NF3)及分子氫(H2)的混合物作為第一前驅物氣體343及使用分子氫(H2)作為未激發氣體(第二前驅物氣體)374、使用與分子氫(H2)組合的氟(F)及氫(H)自由基380r,以根據下式形成原子氫(H)及氟(F)自由基的複合物:F*+H2→HF+H*。提供未激發氣體374至蝕刻處理區域310b會微調蝕刻處理區域310b中的氟原子數目與氫原子數目的比率(F/H),其將在下文進一步論述。
在步驟112e,虛設閘極堆疊212用由自由基在表面吸附/解吸附製程中的化學反應形成的產物來蝕刻。氫(H)催化蝕刻製程。在一個實施例中,虛設閘極堆疊212包括多晶矽(Si),並且在表面吸附製程中,原子氫(H)及氟(F)自由基的複合物與多晶矽(Si)組合以形成四氟化矽(SiF4)及分子氫(H2)作為表面解吸附的氣態反應副產物。根據本文描述的一些實施例,包含多晶矽虛設閘極堆疊212蝕刻速率
對包含氮化矽閘極間隔物260蝕刻速率的選擇性可大於約25:1,諸如約50:1至約100:1(例如約60:1)。因此,操作112中的自由基蝕刻稱為大體上不含有離子轟擊的選擇性各向同性蝕刻。
第12A圖及第12B圖圖示虛設閘極堆疊212藉由操作112的自由基蝕刻去除之後的半導體元件200。第12A圖圖示Y-Z平面中的半導體元件200的橫截面視圖,而第12B圖圖示X-Z平面中的半導體元件200的橫截面視圖。相比於應用離子轟擊的第10A圖及第10B圖,閘極間隔物270大體上未遭受由於應用不含離子轟擊的自由基蝕刻而造成的側壁損害。側壁270的中間部分為大體上筆直的。側壁270的頂部中的弓形結構及側壁270的底部中的基部結構兩者的尺寸都顯著減小。在不同實施例中,具有自由基蝕刻的操作112經常導致L1/H1及L1'/H1(參照第12A圖)兩者小於約8%,諸如小於約3%(例如,在特定實例中約2%),及L2/H2及L2'/H2(參照第12B圖)兩者小於約8%,諸如小於約3%(例如,在特定實例中約2%)。本揭示的發明者已經注意到,當上述比率大於約8%時,閘極結構效能的均勻性退化,而當上述比率小於約8%時,閘極結構效能的均勻性提高。
在特定實施例中,閘極間隔物260富含氮化物,諸如主要包含氮化矽,而ILD層266富含氧化物,諸如主要包含氧化矽,並且操作112的自由基蝕刻使用氟(F)及氫(H)自由基作為蝕刻劑,此蝕刻劑對富含氧化物材料比富
含氮化物材料具有更高的蝕刻比率(etch rate)。因此,ILD層266在操作112期間在其頂表面上可能遭受比閘極間隔物260更高的蝕刻損失。因而,在兩個相鄰閘極溝槽272之間,閘極間隔物-ILD層-閘極間隔物的組合結構的頂表面展現具有最低點的凹槽276,此最低點在ILD層266的約中心,如第12B圖所示。閘極間隔物260面向閘極溝槽272的側壁270亦高於面向ILD層266的相對側壁。凹槽276的深度表示為D。凹槽276的深度與閘極間隔物260的高度的比率(D/H2)在一些實施例中可大於約3%。本揭示的發明者已經觀察到,大於約3%的D/H2為後續形成的S/D觸點提供更大著陸區域(landing area)的效能益處。
對於使用氟(F)及氫(H)自由基作為蝕刻劑的操作112的自由基蝕刻,蝕刻處理區域310b(第11圖)中氟原子數目與氫原子數目的比率(F/H)控制作為副產物生成的矽烷的量。豐富的氫(H)在製程腔室中接觸水蒸氣時會與基板上的矽(Si)鍵接,形成矽烷。藉由調整進入蝕刻處理區域310b中的含氫第二前驅物氣體374的量,可微調F/H比率。本揭示的發明者已經觀察到,F/H閾值(threshold)在約90:1000至約96:1000之間,諸如特定實例中約93:1000的閾值,使得當F/H比率大於F/H閾值時,將沒有充足的氫來生成矽烷。因此,第12A圖及第12B圖中的產生的元件不含矽烷。相反,當F/H比率小於閾值時,諸如在特定實例中小於約93:1000,由於豐富的氫,矽烷開始作為副產物出現。在蝕刻製程期間,矽烷大體被認為是污染源。然而,藉
由仔細控制蝕刻處理區域310b中的F/H比率略微低於F/H閾值,諸如約88:1000,適當控制量的矽烷將形成為覆蓋閘極溝槽272的側壁及底表面的薄覆蓋膜278,其可充當保護層以在後續操作之前保護半導體元件200,諸如第13A圖及第13B圖圖示。第13A圖圖示Y-Z平面中的半導體元件200的橫截面視圖,而第13B圖圖示X-Z平面中的半導體元件200的橫截面視圖。
在操作114,方法100(第1圖)在閘極溝槽272中沉積高介電常數金屬閘極堆疊280,諸如第14A圖及第14B圖所示。第14A圖圖示Y-Z平面中的半導體元件200的橫截面視圖,而第14B圖圖示X-Z平面中的半導體元件200的橫截面視圖。操作114可選擇性地預先執行濕式清洗製程以從閘極溝槽272的側壁及底表面去除矽烷覆蓋膜278(若覆蓋膜278在上述操作中形成)。高介電常數金屬閘極堆疊280包括高介電常數介電層282及導電層284。高介電常數金屬閘極堆疊280可進一步包括在高介電常數介電層282與鰭狀物204之間的介面層(例如,二氧化矽或氮氧化矽)(未圖示)。介面層可使用化學氧化、熱氧化、ALD、CVD、及/或其他適當方法形成。
高介電常數介電層282可以包括一或多種介電材料(或一或多個高介電常數介電材料層),諸如氧化矽鉿(HfSiO)、氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶
(SrTiO3)或上述組合。高介電常數介電層282可使用CVD、ALD及/或其他適當方法沉積。
導電層284包括一或多個金屬層,諸如功函數金屬層、導電阻障層及金屬填充層。根據元件的類型(PFET或NFET),功函數金屬層可為P型或N型功函數層。P型功函數層包含但不限於從由以下各者組成的群組中選出的具有足夠大有效功函數的金屬:氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)或上述組合。N型功函數層包含但不限於從由以下各者組成的群組中選出的具有足夠低有效功函數的金屬:鈦(Ti)、鋁(Al)、碳化鉭(TaC)、氮碳化鉭(TaCN)、氮化矽鉭(TaSiN)、氮化鋁鈦(TiAlN)、氮化矽鈦(TiSiN)或上述組合。金屬填充層可以包括鋁(Al)、鎢(W)、鈷(Co)及/或其他適宜材料。導電層284可使用諸如CVD、PVD、電鍍及/或其他適當製程的方法沉積。
在操作116處,方法100(第1圖)執行另外步驟以完成半導體元件200的製造。例如,方法100可形成連接不同電晶體的金屬互連件以形成完全的IC,金屬互連件諸如S/D觸點288,如第15圖所示,其為X-Z平面中半導體元件200的橫截面視圖。操作116可包括以下步驟:在半導體元件100上方沉積介電層286,蝕刻暴露S/D特徵262的接觸孔(未圖示),及將一或多種導電材料沉積進接觸孔中以形成S/D觸點288。ILD層266的凹進的頂表面可助於S/D觸點288的著陸。
儘管未旨在限制,但本揭示的一或多個實施例提供對半導體元件及其形成的許多益處。例如,本揭示的實施例提供一種閘極形成方法,其保持閘極間隔物的大體上筆直側壁輪廓,並因此保持閘極堆疊的大體上筆直側壁輪廓。閘極形成方法包括不含離子轟擊的自由基蝕刻。因此提高閘極結構效能的均勻性。此外,用於閘極形成的自由基蝕刻可易於整合入現有半導體製造製程中。
在一個示例性態樣中,本揭示關於一種方法。此方法包括以下步驟:提供一種結構,此結構具有基板及從基板突出的鰭狀物;在鰭狀物上方形成虛設閘極堆疊;在虛設閘極堆疊的側壁上形成閘極間隔物;使用自由基蝕刻製程去除虛設閘極堆疊,產生閘極溝槽;以及在閘極溝槽中形成金屬閘極堆疊。在一些實施例中,自由基蝕刻製程為各向同性的。在一些實施例中,自由基蝕刻製程包括以下步驟:將第一蝕刻前驅物激發成電漿;及在使自由基接觸虛設閘極堆疊之前將自由基與電漿分離。在一些實施例中,方法進一步包括在自由基與電漿分離之後,將自由基與第二蝕刻前驅物組合的步驟。在一些實施例中,第一蝕刻前驅物不含氧及氯。在一些實施例中,自由基蝕刻製程包括施加包含氯及氫的自由基的步驟。在一些實施例中,自由基蝕刻製程產生覆蓋閘極溝槽的覆蓋膜。在一些實施例中,覆蓋膜包括矽烷。在一些實施例中,自由基蝕刻製程包括施加具有一比率的蝕刻前驅物的步驟,此比率為氟原子數目與氫原子數目的比
率,其小於約93:1000。在一些實施例中,虛設閘極堆疊的去除步驟不含有對結構施加偏置電場的步驟。
在另一示例性態樣中,本揭示關於一種方法。方法包括一些步驟:在製程腔室的蝕刻處理區域中接收一結構,此結構包括基板上方的虛設閘極堆疊及虛設閘極堆疊的側壁上的閘極間隔物;在製程腔室的電漿區域中用前驅物氣體生成電漿,此電漿包括自由基及帶電離子;使自由基流進蝕刻處理區域中,而將帶電離子從蝕刻處理區域的入口大體上排除;用自由基蝕刻虛設閘極堆疊,產生閘極溝槽;以及在閘極溝槽中形成金屬閘極堆疊。在一些實施例中,方法進一步包括在蝕刻處理區域中接收未激發氣體以與自由基混合的步驟。在一些實施例中,自由基及未激發氣體兩者包括氫。在一些實施例中,在蝕刻虛設閘極堆疊期間,自由基及未激發氣體包括氟及氫。在一些實施例中,氟原子數目與氫原子數目的比率大於約93:1000。在一些實施例中,氟原子數目與氫原子數目的比率小於93:1000,使得虛設閘極堆疊的蝕刻在閘極溝槽的側壁上方產生覆蓋膜。在一些實施例中,方法進一步包括在形成金屬閘極堆疊之前,執行濕式清洗製程以去除覆蓋膜的步驟。
在又一示例性態樣中,本揭示關於一種半導體元件。半導體元件包括:基板;從基板突出的鰭狀物,鰭狀物在第一方向上縱向延伸;與鰭狀物接合的閘極堆疊,閘極堆疊在與第一方向垂直的第二方向中縱向延伸;閘極堆疊側壁上的閘極間隔物,閘極間隔物包括與閘極堆疊的側壁直接
連接的內側壁及與內側壁相對的外側壁,在橫截面視圖中沿第一方向此內側壁具有第一高度及朝向閘極堆疊延伸第一橫向距離的弓形結構,第一橫向距離沿第一方向從內側壁的中點測量,其中在橫截面視圖中沿第一方向此外側壁具有低於內側壁的第一高度的第二高度。在一些實施例中,第一橫向距離小於第一高度的約8%。在一些實施例中,在橫截面視圖中沿第一方向,內側壁具有朝向閘極堆疊橫向延伸第二橫向距離的基部結構,第二橫向距離沿第一方向從內側壁的中點測量,其中第二橫向距離小於第一高度的約8%。
以上概述了幾個實施例的特徵,以便本領域之普通技術人員可以更好地理解本揭示案之態樣。本領域的普通技術人員應該理解,他們可易於使用本揭示作為設計或更改此處介紹的實施例的相同目的及/或實現相同優勢的其他製程及結構的基礎。本領域的普通技術人員也應當認識到,此種同等結構不脫離本揭示的精神及範疇,並且他們可在不脫離本揭示的精神及範疇的情況下,進行各種改變、置換及改動。
100:方法
102、104、106、108、110、112、114、116:操作
Claims (10)
- 一種製作半導體元件的方法,包括以下步驟:提供一結構,該結構具有一基板及從該基板突出的一鰭狀物;在該鰭狀物上方形成一虛設閘極堆疊;在該虛設閘極堆疊的側壁上形成一閘極間隔物;使用一自由基蝕刻製程去除該虛設閘極堆疊,產生一閘極溝槽,該自由基蝕刻製程包括施加包含氟和氫的自由基的一步驟,且氟原子數目與氫原子數目的一比率大於一閥值,該閥值為約90:1000至約96:1000;以及在該閘極溝槽中形成一金屬閘極堆疊。
- 如請求項1所述的方法,其中該自由基蝕刻製程為各向同性的。
- 如請求項1所述的方法,其中該自由基蝕刻製程包括以下步驟:將一第一蝕刻前驅物激發成一電漿;以及在使自由基接觸該虛設閘極堆疊之前,將該等自由基與該電漿分離。
- 如請求項3所述的方法,進一步包括以下步驟: 在該等自由基與該電漿分離之後,將該等自由基與一第二蝕刻前驅物組合。
- 一種製作半導體元件的方法,包括以下步驟:在一製程腔室的一蝕刻處理區域中接收一結構,該結構包括在一基板上方的一虛設閘極堆疊及在該虛設閘極堆疊的側壁上的一閘極間隔物;在該製程腔室的一電漿區域中用一前驅物氣體生成電漿,該電漿包括自由基及帶電離子;使該等自由基流進該蝕刻處理區域中,而基本上排除該等帶電離子進入該蝕刻處理區域;用該等自由基蝕刻該虛設閘極堆疊,產生一閘極溝槽,該等自由基包括氟和氫,且氟原子數目與氫原子數目的一比率大於一閥值,該閥值為約90:1000至約96:1000;以及在該閘極溝槽中形成一金屬閘極堆疊。
- 如請求項5所述的方法,進一步包括以下步驟:在該蝕刻處理區域中接收一未激發氣體,以與該等自由基混合。
- 如請求項6所述的方法,其中該等自由基及該未激發氣體兩者包括氫。
- 一種半導體元件,包括:一基板;一鰭狀物,從該基板突出,該鰭狀物在一第一方向上縱向延伸;一閘極堆疊,接合該鰭狀物,該閘極堆疊在垂直於該第一方向的一第二方向中縱向延伸;以及一閘極間隔物,在該閘極堆疊的側壁上,該閘極間隔物包括與該閘極堆疊的該側壁直接連接的一內側壁及與該內側壁相對的一外側壁,在一橫截面視圖中沿該第一方向該內側壁具有一第一高度以及一弓形結構朝向該閘極堆疊延伸一第一橫向距離,該第一橫向距離為沿該第一方向自該內側壁的一中點測量的,其中在橫截面視圖中沿該第一方向,該外側壁具有低於該內側壁的該第一高度的一第二高度。
- 如請求項8所述的半導體元件,其中該第一橫向距離小於該第一高度的約8%。
- 如請求項8所述的半導體元件,其中在該橫截面視圖中沿該第一方向,該內側壁具有朝向該閘極堆疊橫向延伸一第二橫向距離的一基部結構,該第二橫向距離沿該第一方向從該內側壁的該中點測量,其中該第二橫向距離小於該第一高度的約8%。
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