TW201113935A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.

Description

201113935 UMCD-2009-0030 3195 ltwf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a void-free Semiconductor component and method of manufacturing the same. [Prior Art] As the size of semiconductor components is shrinking, the size of gates and structures is also reduced. Therefore, the thickness of the gate dielectric layer must also be reduced to avoid the effects of component performance. Generally, the material of the gate dielectric layer is usually yttrium oxide, but the gate dielectric layer made of yttrium oxide tends to have a leakage current when the thickness is reduced. In order to reduce the occurrence of leakage current, the S removal method uses a high dielectric constant (high-k) material instead of yttrium oxide as the gate dielectric layer. In the case of using a high dielectric constant material as the gate dielectric layer, a gate with polysilicon as a material reacts with a high dielectric germanium material to produce a Fermi level pinning, thereby causing a threshold voltage. ) increase and affect the efficiency of the component. One of the conventional techniques is to use a metal layer as a gate, that is, a well-known workfonction metal layer, to avoid an increase in the starting voltage and to lower the resistance of the element. In the case of a gate structure generally having a high-k dielectric layer and a metal gate, one conventional practice is to use a method in which a dummy pattern is formed first to form a gate structure. That is to say, the dummy pattern and the interlayer dielectric layer are formed on the substrate, and then the dummy pattern is removed, and then the opening towel formed after the dummy pattern is removed by moving the 201113935 ——-2009-0030 31951 twf.doc/n Metal gate structure. However, the virtual pattern that is typically formed by patterning the virtual pattern material layer to form a virtual pattern over the limit of the process is generally narrow: The trapezoidal shape is such that the top side of the interlayer dielectric layer and the surface of the interlayer dielectric layer are in a virtual shape, and the case is a trapezoid having a narrow width and a wide width. When the metal layer is filled in the opening with Du Er private, the effect of the metal filling groove (metalSaPfl11) is not affected by the earth's Gvefhang (4) problem, which causes the hole in the metal layer to have a hole of $41'. Component reliability and performance. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method for forming a semiconductor device, which is subjected to an ion implantation process to improve the reliability and performance of the device before forming a dummy pattern. The present invention provides a semiconductor device whose gate structure is disposed in a trench having a wide top opening and thus has a metal layer having no voids (v〇id_free). • The present invention proposes a method of manufacturing a semiconductor device. First, a polycrystalline germanium layer is formed on the substrate. The polycrystalline germanium layer is doped with an N-type dopant. Next, a portion of the polysilicon layer is removed to form a plurality of dummy patterns. Each of the dummy patterns has a top portion, a bottom portion, and a neck portion between the top portion and the bottom portion, wherein the width of the crotch portion is smaller than the width of the top portion. Thereafter, a dielectric layer is formed over the substrate, the dielectric layer covering the substrate between the dummy patterns and exposing the top of the dummy pattern. Accordingly, the dummy pattern is removed to form a plurality of trenches in the dielectric layer. Then, a plurality of gate structures are formed in the trench. 201113935 UMCD-2009-0030 31951 twf.doc/n In one embodiment of the invention, the polysilicon layer doped N-type dopant has the highest concentration at substantially the same level as the neck. In an embodiment of the invention, the polycrystalline N-type dopant concentration of the polycrystalline layer is greater than the N-type dopant concentration doped by the top of the polycrystalline layer.

In one embodiment of the invention, the concentration of the doped N-type dopant is increased from the top to the bottom of the polycrystalline layer. ''X In one embodiment of the invention, the method of fabricating a semiconductor device further includes rubbing another N-type dopant in the polycrystalline layer. In an embodiment of the invention, the N-type dopant is phosphorus (p), antimony (Sb) or arsenic (As). In one embodiment of the invention, when the N-type dopant is phosphorus, the energy used for doping is greater than 1 Kev but less than 20 KeV, and the dose is greater than 1E15 cm_2 but less than 8E15 cm 2 . In an embodiment of the invention, the distance between the top portion and the neck portion is a distance between the neck portion and the bottom portion. The ratio between the first height and the second height is substantially 2:1. In one embodiment of the invention, the angle between the top sidewall of the trench and the surface of the dielectric layer is greater than 90°. In one embodiment of the invention, the above method of removing a portion of the polysilicon layer includes the use of a halogen-containing reactant for credit engraving. In an embodiment of the invention, a high dielectric constant layer is further formed between the substrate and the dummy pattern before the dummy pattern is removed. In an embodiment of the present invention, the method for fabricating a semiconductor device further includes a source/defect formed in a substrate on both sides of the gate structure by 201113935 umcu-2〇〇9-〇〇3 0 31951 twf.doc/n. Polar zone. The method of forming the source/drain regions is, for example, an ion implantation process or a selective epitaxial growth process. In an embodiment of the invention, after the dummy pattern is formed and before the dielectric layer is formed, a spacer is further formed on the sidewall of the dummy pattern.

The present invention further provides a semiconductor device including a substrate, a gate structure, and a source/drain region. A dielectric layer is disposed on the substrate, and a trench is disposed in the dielectric layer. The gate structure is located in the trench, and the gate structure comprises a high dielectric constant layer, a work function metal layer and a metal layer which are sequentially arranged on the substrate. The source/drain regions are disposed in the substrate on either side of the gate structure. The trench has a top, a bottom and a neck between the top and the bottom, the width of the neck being less than the width of the top, and the width of the crotch being less than or equal to the width of the bottom. In one embodiment of the present invention, the distance between the top portion and the neck portion is the same as the second height between the bottom portion and the bottom portion, and the ratio between the first height and the second degree is substantially 2:1. In one embodiment of the invention, the angle between the top sidewall of the trench and the surface of the dielectric layer is greater than 90. . Inventive - In the embodiment, the abundance conductor element further comprises an insulating layer disposed between the substrate and the high dielectric constant layer. In an embodiment of the invention, the source/recording area is a tick zone. The conductor element further includes a spacer, and the method of fabricating the component, in one embodiment of the invention, is semi-disposed on the sidewall of the gate structure. Based on the above, the semiconductor 201113935 UMCD-2009-0030 31951twf.doc/n of the present invention is subjected to an ion implantation process after the polycrystalline layer, so that the doped polysilicon layer can be utilized differently when removing a portion of the polysilicon layer. The depth locations have different etch rates and form a dummy pattern having a neck width that is less than the top width. In this way, when the dummy pattern is removed and filled into the metal layer, not only the virtual pattern is quickly removed, but also the effect of the metal filling groove can be improved, and the hole is not easily formed, which can greatly improve the reliability of the component. And performance. The gate structure of the semiconductor device of the present invention is disposed in a trench having a wide upper opening, so that there is no hole in the metal layer of the gate structure, and good component performance can be obtained. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. 1A to 1E are schematic cross-sectional views showing a manufacturing process of a semiconductor body according to an embodiment of the present invention. It should be noted that the manufacturing method of the semiconductor device described below is described by taking a gate last process to form a complementary metal oxide semiconductor (CM 〇 s) device as an example, which is mainly To the extent that the skilled artisan is aware of the scope of the invention. The method of the present invention can also be used to form single-metal oxide semiconductor (M?s) devices. As for other components such as the metal gate structure, the doping region, the spacer, the stop layer, and the like, the arrangement position, the material and the order can be made according to the technique known to those skilled in the art, and are not limited to the following implementations. As stated in the example. 201113935 um^-2009-0030 31951twf.doc/n Referring to FIG. 1A, a substrate 100 is provided. The substrate 1 is, for example, a semiconductor substrate such as an N-type or P-type base, a tri-five semiconductor substrate, or the like. The substrate 100 has a first region 101a and a second region 101b, wherein the first region 101a and the second region 10b are separated by an isolation structure 1〇2. In an embodiment, when the first region 10a is a p-type metal oxide semiconductor region, the second region 101b is an N-type metal oxide semiconductor (NM〇s) region. The isolation structure 102 is, for example, a shallow trench isolation structure.

Then, a high dielectric constant (high k) material layer 1〇4 and a polycrystalline stone layer 1〇6 are sequentially formed on the substrate 100. The material of the high dielectric constant material layer 1〇4 is, for example, a dielectric material having a dielectric constant greater than 4, which may be Ti〇2, Zr02, A1203, La203, Y2〇3, Gd2〇3, Ta2〇5 or 2 combination. The method of forming the high dielectric constant material layer 104 is, for example, a vapor deposition (CVD) process. In an embodiment, the insulating material layer 1G3' may also be selectively applied on the surface of the substrate 1 to increase the layer of the high dielectric constant material 1 () 4 and the substrate (10) before forming the high dielectric material layer 104. Adhesion. The material of the insulating material layer 103 is, for example, oxygen. The method for forming the insulating material is, for example, a thermal oxidation method. The polycrystalline chopping layer should be, for example, a material layer formed by a pre-formed dummy pattern. The lamp ion implantation process 107 is then selected for the polycrystalline implant process 107, for example, by means of vertical implantation: mode i-day layer 106 is fully doped. N-type change (f), record, or Kun (As). The Handu distributed in the multi-layer 106 t will change with different depth positions of polycrystalline (tetra) 1G6t -, 201113935 UMCD-2009-0030 31951twf.doc/nn _ The highest concentration of mass concentration is located in the polycrystalline stone layer ^ The main bottom is increasing. In one embodiment, when the thickness of the polycrystal is about .u_A and the implanted (four) type uses a suitable energy between about 1 Kev and 20 KeV, the dose between Cong W and Mier-2 is used. The position from the schedule l〇7' is made such that the highest concentration of the N-type holding f falls on the surface of the multi-layer day 106 from about 300 to 4 people. A patterned hard mask is formed on the polycrystalline layer 106; the divided plurality of layers 1 〇 8 have, for example, openings </ RTI> to expose the 108 Å surface. In this step, the ® hard mask layer port configuration is set according to the position of the subsequent pre-formed gate structure, ie, the polycrystalline stone layer 106 covered by the patterned hard mask layer 108:: Subsequent pre-formation of the location of the gate structure. The patterned hard mask layer (10) can be selected from the polycrystalline stone layer 1〇6 with a different material selectivity = ‘/, for example, nitrite, oxidized stone or nitrous oxide. The method for forming the patterned hard mask I 08 is, for example, first forming a hard mask material layer (not shown in green) on the substrate 100 by chemical vapor deposition, and then using the photoresist material to enter the lithography process, silver. The engraving process removes a portion of the hard mask material layer. After the eve, the exposed hard mask layer 108 is used as a mask to remove the exposed sap layer 106 to form a plurality of dummy patterns 11 〇. Next, the high-encapsulation material layer 104 and the insulating material layer 1〇3 are patterned to form a high-intermediate layer-by-layer and insulating layer called a high dielectric constant layer 1G4a;; 201113935 um^-2009-0030 31951twf.doc /nf 1 2, for example, is a common pre-formed layer: the virtual pattern m has a top ma, a neck liGb, and the neck 邛 110b is located between the top 11 〇 a and the bottom _ 智 智 ■ 认 坻 丨 丨 c 110c The neck 110b has a smaller visibility than the width of the top portion 110a, and the width of the neck u, has a funnel-like cross section: the distance between the real two and the neck 11〇b is the height - Ηι, and the neck two When the distance between the second height H2 is reached, the ratio of the first height ♦ i 6 H2 is substantially 2:1. The method of removing a portion of the polycrystalline layer to form a virtual with 11G involves the use of a halogen-containing reactant. Generally, the use of dry etching to remove a portion of the polycrystalline stone layer contact source is, for example, a gas containing _, gas (C1) or containing (4) radicals. Specifically, due to the doping of the N type The doped polysilicon layer 1〇6, the engraving rate will be souther than the undoped polycrystalline stone material, and the etching rate will increase with the increase of the N-type dopant concentration, so the polycrystalline layer 1 The depth of the 〇6-doped N-type dopant is the highest and the neck u〇b is substantially at the same level as shown in Fig. 1B. In the above examples, the virtual pattern u〇 resembling a funnel-shaped cross section is illustrated, but is not intended to limit the scope of the invention. It is common to those skilled in the art that the virtual pattern can be formed into other shapes as long as the width of the neck is less than the width of the top. That is to say, the concentration distribution of the N-type dopant in the polycrystalline germanium layer 1〇6 can be adjusted by using parameters such as the implantation energy of the ion implantation process 107, so that the horizontal height position with the highest concentration of the N-type dopant can substantially correspond. The width of the virtual pattern formed in the following is 11 201113935 UMCD-2009-0030 31951twf.doc/n The position of the horizontal position in the narrow. 2 and 3 are schematic cross-sectional views showing a virtual pattern according to another embodiment of the present invention. In FIGS. 2 and 3, the same members as those in FIG. 1B are denoted by the same reference numerals and their description is omitted. In one embodiment, the doping dopant concentration at the bottom of the polysilicon layer 106 is greater than the concentration of the N-type dopant doped at the top by controlling the ion implantation process 107 to implant dopant energy and the like. As shown in FIG. 2, after performing the side process to remove a part of the polycrystalline layer, the width of the neck 200b of the virtual pattern 2〇() is, for example, smaller than the width of the top 2〇〇a, and the neck

The width is substantially equal to the width of the bottom 2〇〇c to form an upper width and a narrower profile. In the case of a shell, the energy of the doped N-type doping is increased from the polycrystalline layer to the bottom by using the parameters such as the energy of the n-type dopant in the control ion implantation process 1〇7. As shown in FIG. 3, after the etching process is performed, the width of the neck of the virtual pattern 3〇〇 is 3小于%, which is smaller than the top 3_ shouting degree, and the width of the neck is present. For example, ^ ^ the width of the bottom 30〇c, and form a ladder sound that gradually shrinks from top to bottom.

_ h Other implementations can also be used to dope a variety of N-type dopants in polycrystalline stone = to make the polycrystalline material touch different baths, and to help the formation of virtual patterns. When the #_ type doped (four) branches and * are limited to the actual clothes, it is sufficient to have a virtual pattern with a width greater than the neck width of the t-doped N-type dopant in the polycrystalline stone material. Usually the knowledge can be carried out according to the process requirements. 4 This program 12 201113935 UMco-2009-0030 31951twf.doc/n Please continue to refer to Figure 1C 'Using the virtual pattern uo as a mask to carry out the ion implantation process' in the first district 1Qla A dummy doping region 113a is formed in the substrate 100 on both sides of the dummy pattern iiq, and the substrate 1 wiper on both sides of the dummy pattern 11〇 of the second region 1〇1b forms a light_region mb, and the source is the source bungee. Extension area. When the first region l〇la is a PM〇s region, the lightly doped region is a P-type lightly doped region; when the second region 101b is a NM〇s region, the lightly doped region 113b is an N-type lightly doped region. Area. Thereafter, a spacer m is formed on the sidewall of the dummy pattern 11A. The material of the spacers 112 is, for example, oxidized stone, cerium nitride or cerium oxynitride. The spacers 112 are formed by, for example, forming a layer of spacer material (not shown) on the substrate 100 by a chemical vapor deposition process and then removing a portion of the spacer material layer by anisotropic etching. Further, although the spacers 112 are only shown in a single layer structure in FIG. 1C, the spacers 112 may be a multilayer spacer structure. Next, a source/nopole region 114a is formed in the substrate 100 on both sides of the dummy pattern 11() of the first region 101a, and is in the substrate 1〇〇 on both sides of the dummy pattern 110 of the second region i〇1b A source/drain region U4b is formed. When the first region 101a is a PMOS: region, the source/drain region 114a is, for example, a p-type heavily doped region or a germanium telluride (SiGe) epitaxial layer; when the second region i〇lb is an NMOS region, the source is The /drain region 114b is, for example, an n-type heavily doped region. In one embodiment, the method of forming the source/drain regions 114a, 114b is, for example, an ion implantation process, and forming a p-type or N-type heavily doped region in the substrate 1 分别, respectively. In another embodiment, the method of forming the source/drain region l14a is, for example, first removing a portion of the substrate 100' located on both sides of the dummy pattern no of the first region 10a to form a trench (not shown); A selective epitaxy growth process is then performed to form a doped layer of germanium telluride (SiGe) in a process of selective epitaxy growth (SEG). In addition to being used as the source/no-polar region of the transistor, the Shiyue Aphid crystal layer can also increase the stress of the channel of the PMOS transistor, so that the speed of the hole moves faster, thereby increasing the PM〇s electricity. The operating speed and performance of the crystal. After forming the source/drain regions 114a, 114b, a stop layer 116 is selectively formed on the substrate 100 to comprehensively cover the first region 1a and the second region 101b. The material of the stop layer 116 is, for example, tantalum nitride, and is formed by, for example, performing a chemical vapor deposition process. In an embodiment, the stop layer 116 can serve as a stressor layer that provides compressive stress or tensile stress to the channel region, and can cause the stop layer H6 to be applied to the NM〇s transistor by changing the process parameters for forming the stop layer 116. The tensile stress of the channel or the compressive stress that is applied to the channel of the PMQS transistor. Then, a dielectric layer 118 is formed on the substrate as an interlayer dielectric layer _). For example, the comprehensive cover substrate (10) and the dummy pattern ιι〇 are oxygen-cut and the formation method thereof is, for example, performing a photo-removal of the dielectric layers 118 and 116 to expose the dummy _ 11 〇 The method of increasing the ns and partially stopping the layer 116 by the upper blade Y is, for example, two =) or a process. Next, the dummy image is removed; = the method of forming the trench 120 and exposing the high dielectric constant y dummy pattern 110 is, for example, the surface of age, 仏, /. Remove with the help of (four) axis tilt, which can be profit 201113935 a ^2009-0030 31951twf.d〇c/n

It is explained here that a multi-dot doped with N-doping has a higher _ county, more, and is generally much higher than the doped _ rate. Since the previous step has formed a dummy pattern (10) in the polycrystal, there will be a more (four) removal rate when using '^, and the remaining multi-stones remaining in the dummy pattern U〇曰矽Materials. In addition, doping N in the multi-sand layer can also enter a cow.

, =mpensate) The p-type doping f implanted in the formation of the light rubbing area ma, (10), or the source/汲ς = 14a, 114b, which can help prevent the dummy pattern 11G from being doped with too much P-type doping f It is not easy to remove and other issues. Referring to Figure 1E', the surface of the trench 12() of the first region 1Gla is compliant with the topographical success function metal layer 122, and the surface of the second region 1 lbb is compliant with the topographical success function metal layer 124. The material of the work function metal layers 122, 124 includes all materials capable of achieving a desired work function, such as

TiN, TiAlx, TaC, TaCNO, TaCN or TaN. The method of forming the work function metals Zhan 122, 124 is, for example, a chemical vapor deposition or a physical vapor deposition (PVD) process. The material of the work function metal layer 122 is different from the material of the work function metal layer 124, for example. In one embodiment, when the first region 1〇1a is a PMOS region, the material of the work function metal layer 122 is, for example, TiN; and when the second region 101b is the NMOS region, the material of the work function metal layer 124 is, for example, TiAlx. Next, the metal layer 126 is filled in the trench 120 to form the gate structures 130a and 130b, respectively. The material of the metal layer 126 is, for example, A1, TiAlx rich in Al, Ti or a combination thereof' and its formation method is, for example, a chemical vapor deposition method or a physical vapor deposition method. 15 201113935 UMCD-2009-0030 3195 ltwf.doc/n • In terms of stocks, the JRP electric u-day nr禺叨 function value is between 5 〇 and 5·1 ev, and the required work function value of the NMOS transistor It is between 4 4.1 and 4.1 eV. The work function of the gate structure 13〇a is determined by the metal layer 122 of the work function of the metal layer, and the number of gate structures of the ostrich is determined by the metal layer 126 and the work function metal layer 124 underneath. The work required for the PMOS transistor and the NM0S transistor can be achieved by adjusting the material and thickness of the work function metal layers 122, 124:

Specifically, since the neck width of the virtual pattern is smaller than the top width, the trench 12 formed after removing the dummy pattern has a structure in which the upper opening is wider, that is, the top 12 of the trench 120 is The angle θι between the surfaces of the dielectric layer 118 is, for example, greater than 9 〇. . In this way, the wider trench 12 亡 opening is not only advantageous for quickly removing the dummy pattern, but also has a good metal filling effect when the metal layer 126 is opened, and the hole is not easily formed. The structure of the semiconductor device of the present invention will be described below by taking FIG. 1 as an example.

Referring to FIG. 1A, the semiconductor device of the present embodiment includes a substrate 1A, gate structures 130a, 130b, and source/no-polar regions 114a, 114b. The substrate 100 has a first region 1〇1&amp; and a second region 10b separated by an isolation structure 1〇2, and the first region l〇ia is, for example, a p-type metal oxide semiconductor (pM〇s) region. The first region 101b is, for example, an N-type metal oxide semiconductor (NMOS) region. For example, a dielectric layer is disposed on the substrate 1 and a trench 120 is disposed in the dielectric layer 118. The trench 120 has a top portion 120a, a neck portion 120b 16 201113935 um^-2009-0030 3l951twf.doc/n and a bottom portion 120c, and the neck portion i2〇b is located between the top portion 120a and the bottom portion i2〇c. The gate structure 13A is disposed, for example, in the first region 10a, and the gate structure 130a includes an insulating layer 103a, a high dielectric constant layer 104a, and a work function metal layer 122, which are sequentially disposed on the substrate 100. Metal layer 126. The high dielectric constant layer 104a and the insulating layer i 〇 3a are, for example, a thyristor layer which serves as the gate structure 13 〇 a. The work function of the gate structure 130a is determined, for example, by the metal layer 126 and the work function metal layer 122 under it. The source/drain regions 114a are disposed in the substrate 1〇〇 on both sides of the gate structure 13〇a. In an embodiment, the light-doped region 113a is further disposed in the substrate 10A between the gate structure 13a and the source/drain region 114a. The gate structure 130b is disposed, for example, in the second region i〇ib, and the gate structure 130b includes an insulating layer 1〇3a, a high dielectric constant layer 104a, and a work function metal layer 124, which are sequentially disposed on the substrate 1? Metal layer 126. The high dielectric abundance layer 104a and the insulating layer i〇3a are, for example, a gate dielectric layer which serves as a gate structure i3〇b. The work function of the gate structure 130b is determined, for example, by the metal layer 126 and the work function metal layer 124 under it. The source/drain region H4b is provided with φ in the substrate 1〇〇 on both sides of the gate structure 13〇b. In one embodiment, the lightly doped region 113b is further disposed in the substrate 10A between the gate structure i3.〇b and the source/drain region 114b. In the above, the gate structures 13A and 130b are disposed, for example, in the trenches 12A. The insulating layer 103a is disposed on the surface of the substrate 1 in the trench 120, and the dielectric constant layer 104a is disposed on the surface of the insulating layer 103a. The work function metal layer 122 and the work function metal layer 124 are respectively compliantly disposed on the surface of the trench 120 located in the first region 10a and the second region 10b, and cover 17 201113935 UMCD-2009-0030 31951twf.doc /n High dielectric constant layer 104a. The metal layer 126 fills the trenches 12 and the work function metal layers 122, 124. Specifically, the trench 120 is, for example, a structure having a wide upper opening, that is, an angle between the sidewall of the top 120a of the trench 120 and the surface of the dielectric layer 118. For example, it is greater than 90% of the neck of the trench 120. The width is smaller than the width of the top portion 120a, and the width of the neck portion 12b of the trench 12〇 is smaller than the width of the bottom portion 120c to form a funnel-like cross section. In one embodiment, the height ratio between the neck 120b and the top 120a and the height between the neck f〇b and the bottom 120c are substantially 2:1. That is, when the depth of the trench 120 is about 50 〇 to 6 〇〇, the height difference between the neck of the trench and the top 120a is, for example, 3 至 to 400 Å. Further, the gate structure in the semiconductor device of the present invention may have other configurations in addition to the above-described funnel-shaped trench. ® 4 is a schematic cross-sectional view of a semiconductor device in which the present invention is implemented. In Fig. 4, the same components as those in the drawings are denoted by the same reference numerals and the description thereof will be omitted. In the other embodiment, the main components constituting the semiconductor shown in FIG. 4 are mainly the same as those of the semiconductor component shown in FIG. m, but the difference between the two is mainly in the trench. The structure of the pole structures 130a, 130b is disposed, for example, in the trench 400. The trench 400 is, for example, a structure having a wide upper opening, and an angle between the top side wall and the surface of the dielectric layer 118 is, for example, greater than 9 Å. . The width of the ditch 4〇 neck 4_ is, for example, smaller than the width of the top_a, and the width of the neck 400b of the ditch 4〇〇201113935 UMCD-2009-0030 31951twf.doc/n is substantially equal to approximately the width of the bottom. The upper and lower narrow sections are formed. In summary, the semiconductor device of the above embodiment and the method of fabricating the same have at least the following advantages: 1. The gate structure of the semiconductor device of the above embodiment is disposed in a trench having a neck visibility smaller than the top width, thereby filling the trench There is no hole in the metal layer, and it has good component performance. 2. The trench of the semiconductor device of the above embodiment has a material having a neck width of 2 or a width of the bottom, and the width of the bottom of the single ditch is the same as that of the N. This can form a wide open trench. Therefore, the critical dimension of the component is not affected. (critical dimension, CD). 3. The method for fabricating a semiconductor device according to the above embodiment is to dope the polycrystalline germanium layer with an N-type dopant to form an etch rate of the polysilicon layer in a layered manner before forming a dummy pattern, thereby forming a neck width smaller than the top portion. A virtual pattern of width that helps to improve metal filling ability without forming holes. 4. The manufacturing method of the semiconductor device of the above embodiment can further compensate the p-type dopant implanted in the process by the doping of the N-type dopant in the germanium 矽=, thereby being able to quickly remove the dummy pattern without Residual polycrystalline stone material in the ditch. Ba 5* The manufacturing method of the semiconductor device of the above embodiment can be applied to all of the back gate processes, particularly the gate forming of the metal gate, and can be integrated with the existing semiconductor process, and the process is simple and Can effectively improve component reliability. 19 201113935 UMCD-2009-0030 31951twf.doc/n Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any of the technical tissues has the general knowledge of the invention. Make some changes and refinements, and the protection of X Ming will be subject to the definition of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1E are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. 2 and 3 are schematic cross-sectional views of a virtual pattern, respectively, according to another embodiment of the present invention. 4 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. [Main component symbol description] 100: Substrate 101a: First region 101b: Second region 102: Isolation structure о 103: Insulating material layer 103a: Insulating layer 104: High dielectric constant material layer 104a: High dielectric constant layer 106: Polycrystalline germanium layer 107: ion implantation process 20 201113935 ujvlcjj-2009-0030 3195 ltwf.doc/n 108: patterned hard mask layer 110, 200, 300: virtual patterns 110a, 120a, 200a, 300a, 400a: top 110b, 120b, 200b, 300b, 400b: neck 110c, 120c, 200c, 300c, 400c: bottom 113a, 113b: lightly doped region 112: spacers 114a, 114b: source and polar regions • 116: stop layer 118: Electrical layer 120, 400: trenches 122, 124: work function metal layer 126: metal layer 130a, 130b: gate structure: first height H2: second height • θι, 02: angle 21

Claims (1)

201113935 UMCD-2009-0030 3I95Itw£doc/n VII. Application for patents: I. - A semiconductor tree (4) method for forming a polycrystalline dream layer on a substrate, · doping a N in the polysilicon layer a type of dopant; each of the bottom portions of the matrix is formed to form a multi-shell virtual pattern, the dummy pattern has a top portion, a bottom portion, and a head portion at the top portion where the width of the portion is smaller than the ' A plurality of gate structures are formed in the trenches respectively. 2. The crystal doping as described in the scope of claim 2 is rich in the N-type dopant == the neck is substantially at the _ level. m clothing and square, please refer to the patent range of the semi-guided material produced in the first section: the thickness of the N-type dopant doped with the bottom of the crystal layer is large, on the top of the layer The N-type dopant concentration doped. Gu Mu 4. Gan 申请 申请 申请 申请 申请 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The method of fabricating a semiconductor device further includes doping the polysilicon layer with another germanium dopant. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the cerium-type dopant is phosphorus (strontium), antimony (Sb) or arsenic (As). 22 201113935 UMUU-2009-0030 31951twf.doc/n 7. A method of applying for a patented window, wherein the fabrication of the semiconductor component described in the N miscellaneous is performed when the gate of the 20 KeV gate is an arm The energy used is between cm_2. And the method of manufacturing the semiconductor device according to item (1) and (8) and 8E15, wherein the distance between the top portion and the _ portion ς and the bottom portion is the second height, and the ratio of the first height two = It is essentially 2:1. The door is reversed, and the Chengfu exhibition is a method. The manufacturing method of the semiconductor component described in the first item of the second method is the i 90. The ancient ice between the top side wall and the surface of the dielectric layer, it patent, the reactants for the manufacture of the semiconductor element described in the first item.方 的 — — — — 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. 11. _ Taisho 2, the manufacture of the semiconductor device described in item 1 of the range = the source on both sides of the gate structure is formed - source / 13. The semiconductor described in the scope of the patent application 帛 12 The method of meta-fabrication's method of wrapping the source-polar region of the source into the process or the selective crystal growth process. &amp; Ion ion root 14. The method for fabricating a semiconductor tree as described in the scope of the patent application, after calling the dummy patterns and before forming the dielectric layer, further 23 201113935 UMCD-2009-0030 31951twf.doc/ n is formed on a sidewall of each of the dummy patterns to form a spacer. A semiconductor device comprising: a substrate on which a dielectric layer is disposed, and a trench is disposed; the gate structure includes a work function metal layer and a gold-gate structure, which are located in the trench a high dielectric constant layer on the substrate; and a source/drain region, the substrate disposed on both sides of the gate structure Wherein the trench has a top portion, a bottom portion and a neck portion between the bottom portion of the top box, the neck portion having a width smaller than the width of the top portion, and the width of the neck portion being less than or equal to the width of the bottom portion. The semiconductor component according to claim 15, wherein the distance between the top portion 4 and the portion is - the height, the distance between the neck portion and the bottom portion - the second height, the first height and the The first example is essentially 2:1. 1 . The semiconductor device according to claim 15 , wherein an angle between the wall of the top of each of the trenches (4) and the surface of the dielectric layer is greater than 90 〇. The semiconductor device of claim 15, further comprising an insulating layer disposed between the substrate and the high dielectric constant layer. The semiconductor device of claim 15, wherein the source/drain region is a doped region or an epitaxial layer. The semiconductor component of claim 15, further comprising a spacer disposed on a sidewall of the gate structure. twenty four