CN110970492A - 半导体器件和形成半导体器件的方法 - Google Patents
半导体器件和形成半导体器件的方法 Download PDFInfo
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- CN110970492A CN110970492A CN201910927998.2A CN201910927998A CN110970492A CN 110970492 A CN110970492 A CN 110970492A CN 201910927998 A CN201910927998 A CN 201910927998A CN 110970492 A CN110970492 A CN 110970492A
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- plasma
- etch
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Abstract
形成半导体器件的方法包括提供具有衬底和从该衬底突出的鳍的结构;在鳍上方形成伪栅极堆叠件;在伪栅极堆叠件的侧壁上形成栅极间隔件;使用自由基蚀刻工艺去除伪栅极堆叠件,从而产生栅极沟槽;并且在栅极沟槽中形成金属栅极堆叠件。本发明的实施例还涉及半导体器件。
Description
技术领域
本发明的实施例涉及半导体器件和形成半导体器件的方法。
背景技术
半导体集成电路(IC)行业经历了指数型增长。IC材料和设计中的技术进步已经产生了多代IC,其中,每一代都比上一代具有更小且更复杂的电路。在IC演变过程中,功能密度(即,每芯片面积的互连器件的数量) 已经普遍增大,而几何尺寸(即,使用制造工艺可产生的最小组件(或线)) 已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小也增加了处理和制造IC的复杂性。
在一些IC设计中,随着技术节点缩小而实现的一项进步是用金属栅极替换典型的多晶硅栅极,以通过减小部件尺寸来改善器件性能。形成金属栅极的一个工艺称为替换栅极或“后栅极”工艺,其中,在去除多晶硅栅极之后制造金属栅极,这允许减少后续工艺的数量,包括高温工艺,这必须在形成栅极之后实施。然而,实现这种IC制造工艺存在挑战,尤其是在先进工艺节点中按比例缩小的IC部件。在一个实例中,在多晶硅栅极的去除期间,栅极间隔件的侧壁可能会损坏,从而导致侧壁轮廓不直。因此,需要对该领域进行改进。
发明内容
本发明的实施例提供了一种形成半导体器件的方法,包括:提供具有衬底和从所述衬底突出的鳍的结构;在所述鳍上方形成伪栅极堆叠件;在所述伪栅极堆叠件的侧壁上形成栅极间隔件;使用自由基蚀刻工艺去除所述伪栅极堆叠件,从而产生栅极沟槽;以及在所述栅极沟槽中形成金属栅极堆叠件。
本发明的另一实施例提供了一种形成半导体器件的方法,包括:在工艺室的蚀刻工艺区域中接收结构,所述结构包括位于衬底上方的伪栅极堆叠件和位于所述伪栅极堆叠件的侧壁上的栅极间隔件;用前体气体在所述工艺室的等离子体区域中生成等离子体,所述等离子体包括自由基和带电离子;使所述自由基流入蚀刻工艺区域,同时排除所述带电离子进入所述蚀刻工艺区域;用所述自由基蚀刻所述伪栅极堆叠件,从而产生栅极沟槽;以及在所述栅极沟槽中形成金属栅极堆叠件。
本发明的又一实施例提供了一种半导体器件,包括:衬底;鳍,从所述衬底突出,所述鳍在第一方向上纵向延伸;栅极堆叠件,与所述鳍接合,所述栅极堆叠件在垂直于所述第一方向的第二方向上纵向延伸;以及栅极间隔件,位于所述栅极堆叠件的侧壁上,所述栅极间隔件包括直接与所述栅极堆叠件的侧壁相接的内侧壁和与所述内侧壁相对的外侧壁,在沿所述第一方向的截面图中,所述内侧壁具有第一高度,并且弓形结构朝向所述栅极堆叠件延伸第一横向距离,所述第一横向距离从所述内侧壁的中点沿所述第一方向测量,其中,在沿所述第一方向的截面图中,所述外侧壁的第二高度低于所述内侧壁的第一高度。
附图说明
当结合附图进行阅读时,从以下详细描述可以最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1和图2示出了根据本发明的各个方面的用于形成半导体器件的方法的流程图。
图3、图4、图5、图6、图7A、图7B、图8A、图8B、图10A、图 10B、图12A、图12B、图13A、图13B、图14A、图14B和图15示出了根据一些实施例的在根据图1和图2的方法的制造工艺期间的半导体器件的截面图。
图9和图11示出了根据本发明的各个方面的在根据图1和图2的方法的蚀刻工艺中使用的示例性工艺室。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。更进一步,当用“约”、“近似”等描述数值或数值范围时,除非另有说明,否则该术语旨在涵盖在所描述的数值的+/- 10%内的数值。例如,术语“约5nm”涵盖从4.5nm至5.5nm的尺寸范围。
本发明总体上涉及半导体器件和制造方法,并且更具体地涉及使用选择性自由基蚀刻工艺的晶体管栅极形成。在替换栅极或“后栅极”工艺中,伪栅极去除工艺之后的栅极间隔件的侧壁轮廓限定了随后形成的金属栅极的侧壁轮廓。非直的栅极间隔件的侧壁轮廓可能包括弓形的弯曲、延伸的基脚和/或弯曲的侧壁,这将导致邻接栅极间隔件的金属栅极的类似侧壁轮廓。这可能会对金属栅极性能的均匀性产生负面影响。一些实施例在伪栅极去除工艺期间提供具有基本直的侧壁的栅极间隔件。虽然示例性方法在鳍式场效应晶体管(FinFET)半导体器件的工艺中发现了特殊的应用,但是它们也可以在其它应用中使用,诸如来自诸如平面晶体管等的其它工件上选择性地去除各个材料层。
图1和图2示出了根据本发明的各个方面的用于形成半导体器件的方法100的流程图。方法100仅是实例,并且不旨在限制本发明超出权利要求中明确记载的内容。可以在方法100之前、期间和之后提供附加操作,并且对于该方法的附加实施例,可以替换、消除或移动所描述的一些操作。下面结合图3至图15描述方法100。图3至图8B、图10A、图10B和图 12A至图15示出了在根据方法100的制造步骤期间的半导体器件200的各个截面图。图9和图11示出了适用于方法100的某些操作的各个示例性蚀刻工艺室。
在操作102中,方法100(图1)提供或配备有具有衬底202的半导体器件200,诸如图3所示。在所示的实施例中,衬底202是硅衬底。可选地,衬底202可以包括另一元素半导体,诸如锗;化合物半导体,包括碳化硅、氮化镓、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟;合金半导体,包括硅锗、磷砷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和磷砷化铟镓;等。在另一实施例中,衬底202包括氧化铟锡(ITO)玻璃。在一个实施例中,衬底202可以是晶圆,诸如硅晶圆,并且可以在其上部中包括一个或多个外延生长的半导体层。
在操作104中,方法100(图1)形成从衬底202向上突出的鳍204,如图4所示。在所示的实施例中,鳍204沿着X方向纵向延伸并且在Y方向上彼此间隔开。此外,鳍204总体上彼此平行。可以通过在衬底202的整个区域上方外延生长一个或多个半导体层,并且然后图案化一个或多个半导体层以形成单独的鳍204来形成鳍204。鳍204可以通过任何合适的方法来图案化。例如,可以使用一种或多种光刻工艺来图案化鳍204,该光刻工艺包括双重图案化或多重图案化工艺。通常,双重图案化或多重图案化工艺结合光刻和自对准工艺,从而允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如,在一个实施例中,在衬底上方形成牺牲层,并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层,并且然后可以通过蚀刻初始的外延半导体层来使用剩余的间隔件或芯轴来图案化鳍204。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其它合适的工艺。例如,干蚀刻工艺可以实施含氧气体、含氟气体(例如,CF4、SF6、 CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBR3)、含碘气体、其它合适的气体和/或等离子体、和/或它们的组合。例如,湿蚀刻工艺可以包括在稀释的氢氟酸(DHF);氢氧化钾(KOH)溶液;氨;含有氢氟酸(HF)、硝酸(HNO3) 和/或乙酸(CH3COOH)的溶液;或其它合适的湿蚀刻剂中蚀刻。
在一些实施例中,鳍204可以包括一种或多种半导体材料,诸如硅、锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、硅锗、磷砷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和磷砷化镓铟。在实施例中,鳍204可包括两种不同半导体材料的交替堆叠层,诸如交替堆叠的硅和硅锗层。鳍204可以另外包括用于改善半导体器件200的性能的掺杂剂。例如,鳍204可以包括诸如磷或砷的n型掺杂剂,或诸如硼或铟的p型掺杂剂。
在操作106中,方法100(图1)形成围绕鳍204的隔离结构206。操作106可以包括各种工艺,诸如沉积(例如,FCVD)、退火、化学机械平坦化(CMP)和回蚀刻。用于隔离结构206的材料可以包括未掺杂的硅酸盐玻璃(USG)、氟掺杂的硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)或其它合适的绝缘材料。例如,操作106可以将可流动介电材料沉积在衬底202上方并且填充鳍204之间的间隔,诸如图 5所示。在一些实施例中,可流动介电材料的沉积包括引入含硅化合物和含氧化合物,使其反应以形成可流动介电材料,从而填充间隙。随后,操作106通过一些退火工艺处理可流动材料,以将可流动介电材料转换成固体介电材料。退火工艺可以包括利用在从约400℃至约550℃的范围内的温度的干退火或湿退火。之后,操作106实施一个或多个CMP工艺和/或回蚀刻工艺以使隔离结构206凹进。例如,在各个实施例中,操作106可以采用一种或多种湿蚀刻、干蚀刻、反应离子蚀刻或其它合适的蚀刻方法,以使隔离结构206凹进以暴露鳍204的上部,诸如图6所示。
在操作108中,方法100(图1)形成与鳍204接合的伪(或临时)栅极堆叠件212,诸如图7A和图7B所示。图7A示出了Y-Z平面中的半导体器件200的截面图,而图7B示出了X-Z平面中的半导体器件200的截面图。在示出的实施例中,伪栅极堆叠件212沿着Y方向纵向延伸,该Y 方向垂直于鳍204的纵向方向。伪栅极堆叠件212随后将在后栅极工艺中由诸如高k金属栅极堆叠件的最终的栅极堆叠件替换。在一些实施例中,每个伪栅极堆叠件212包括伪栅极介电层和伪栅电极层(未示出)。伪栅极介电层形成在暴露的鳍204上方。伪栅极介电层可以通过热氧化、CVD、溅射或用于形成伪栅极介电层的本领域中已知和使用的任何其它方法来形成。在一实施例中,伪栅极介电层由与隔离结构206相同的材料形成。在其它实施例中,在其它实施例中,伪栅极介电层可以由一种或多种合适的介电材料制成,诸如氧化硅(例如,SiO2)、氮化硅(例如,Si3N4)、氮氧化硅(例如,SiON)、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如聚酰亚胺的聚合物等或它们的组合。在其它实施例中,伪栅极介电层包括具有高介电常数(k值)的介电材料,例如大于3.9。该材料可以包括金属氧化物,诸如HfO2、HfZrOx、HfSiOx、 HfTiOx、HfAlOx、TiN等或它们的组合。随后,在伪栅极介电层上方形成伪栅电极层。在一些实施例中,伪栅电极层是导电材料,并且可以选自包括多晶硅(poly-Si)、多晶硅锗(poly-SiGe)、氮化硅(例如,Si3N4)、金属氮化物、金属硅化物和金属氧化物。在实施例中,可以通过PVD、CVD、溅射沉积或用于沉积导电材料的本领域中已知和使用的其它技术来沉积伪栅电极层。伪栅电极层的顶面通常具有非平面顶面,并且可以在其沉积之后以一种或多种CMP工艺平坦化。可以通过光刻和蚀刻工艺来图案化伪栅极介电层和伪栅电极层,以形成伪栅极堆叠件212。
在操作110中,方法100(图1)在鳍204中或上方形成多种部件,包括栅极间隔件260、源极/漏极(S/D)部件262、接触蚀刻停止层(CESL) 264、层间介电(ILD)层266,诸如图8A和图8B所示。图8A示出了Y-Z 平面中的半导体器件200的截面图,而图8B示出了X-Z平面中的半导体器件200的截面图。操作110包括多种工艺。
在一些实施例中,操作110在伪栅极堆叠件212的侧壁上形成栅极间隔件260。在所示的实施例中,栅极间隔件260形成在伪栅极堆叠件212 的每一侧上。栅极间隔件260可以用于偏移随后形成的S/D部件262。栅极间隔件260可以包括介电材料,诸如氧化硅、氮化硅、氮氧化硅、碳化硅、其它介电材料或它们的组合,并且可以包括一个或多个材料层。可以通过在隔离结构206、鳍204和伪栅极堆叠件212上方将间隔件材料沉积为毯式层来形成栅极间隔件260。然后,通过各向异性蚀刻工艺来蚀刻间隔件材料。伪栅极堆叠件212的侧壁上的间隔件材料的部分保留并且变为栅极间隔件260。
然后,操作110在鳍204上方形成S/D部件262,在S/D部件262上方形成CESL 264,在CESL 264上方形成ILD层266。例如,操作216可以将凹槽蚀刻到与栅极间隔件260相邻的鳍204中,并且在凹槽中外延生长半导体材料。可以将半导体材料升高到鳍204的顶面之上。操作110可以形组分别用于NFET和PFET器件的S/D部件262。例如,操作110可以利用用于NFET器件的n型掺杂硅或用于PFET器件的p型掺杂硅锗形成 S/D部件262。在特定实施例中,S/D部件262在外延工艺期间通过引入掺杂物质原位掺杂,掺杂物质包括:p型掺杂剂,诸如硼或BF2;n型掺杂剂,诸如磷或砷;和/或其它合适的掺杂剂,包括它们的组合。如果未原位掺杂S/D部件262,则实施注入工艺(即,结注入工艺)以掺杂S/D部件262。例如,NFET器件中的S/D部件262包括SiP,而PFET器件中的S/D部件 262包括GeSnB(锡可以用于调整晶格常数)和/或SiGeSnB。可以实施一个或多个退火工艺以激活S/D部件262。合适的退火工艺包括快速热退火 (RTA)和/或激光退火工艺。
之后,操作110可以在S/D部件262上方沉积CESL 264和ILD层266。 CESL 264可以包括氮化硅、氮氧化硅、具有氧(O)或碳(C)元素的氮化硅和/或其它材料;并且可以通过CVD、PVD、ALD或其它合适的方法形成。ILD层266可以包括正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅,诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG)和/或其它合适的介电材料。ILD层266可以通过等离子体增强CVD(PECVD)、可流动CVD(FCVD) 或其它合适的方法形成。在特定实施例中,栅极间隔件260是富含氮化物的,诸如主要包含氮化硅,而ILD层266是富含氧化物的,诸如主要包含氧化硅。随后,操作110可以实施一个或多个CMP工艺以平坦化半导体器件200的顶面。
在操作112中,方法100(图1)去除伪栅极堆叠件212以形成栅极沟槽。在各个实施例中,操作112使用干蚀刻工艺。相对而言,与诸如湿蚀刻方法的其它工艺相比,实施干蚀刻工艺的优点主要是由于其控制气态蚀刻剂的简单性以及可产生更多可重复结果。在干蚀刻工艺期间,可以改变或修改许多工艺参数,诸如气压、化学组分和源/偏置功率,以进行微调。
干蚀刻工艺可以使用各向异性蚀刻(例如,等离子体蚀刻)或各向同性蚀刻(例如,自由基蚀刻,其中通过过滤等离子体来生成自由基)。在操作112的一个特定实施例中,各向异性蚀刻方法用于蚀刻伪栅极堆叠件 212,诸如等离子体蚀刻(或反应离子蚀刻(RIE))。在图9中示出了适合于等离子体蚀刻的示例性工艺室300。工艺室300包括作为蚀刻工艺区域的真空室310。真空室310经由通道322与真空源320流体连通。真空源320可包括一个或多个真空泵。真空源320可操作以将真空室310的内部保持在适当的低压(例如,低于100mTorr)下。工艺室300还包括用于保持半导体器件200的卡盘330。例如,卡盘330可以是悬臂式静电卡盘,并且半导体器件200通过静电夹具、机械夹具或其它夹持机构定位在卡盘 330上。卡盘330是导电的并且电耦合到偏置电压源332。气体喷射器342 提供前体气体343以在真空室310内生成等离子体。工艺室300进一步包括介电顶盖334,其上安装有多个电极336。介电顶盖334和电极336还可通过绝缘构件340与真空室310的侧面和底部绝缘。电极336,诸如天线或平面线圈,由适当的射频(RF)电源338供电,以将RF能量传输到真空室310中。RF能量可以将真空室310内的前体气体343激发成等离子体 344。与RF能量耦合,偏置电压源332朝向半导体器件200生成偏置电场 346。类似于溅射,在偏压电场346的驱动下,等离子体344中的带电离子轰击半导体器件200的顶面。轰击加速了平行于离子轨迹的刻蚀速率,产生了各向异性刻蚀。在进一步实施例中,前体气体343可包含CF4和Cl2的混合物(即,CF4/Cl2等离子体)。可选地,前体气体343可包含HBr和O2的混合物(即,HBr/O2等离子体)。可以以约500sccm的流速、约60mtorr 的气压、小于约1000W的RF功率和小于约200V的偏置电压的CF4/Cl2 (或HBr/O2)施加蚀刻工艺。
本发明的发明人已经观察到,各向异性蚀刻工艺期间的离子轰击可能导致对栅极间隔件260的侧壁的损坏,从而导致侧壁不直,如图10A和图 10B所示。图10A示出了Y-Z平面中的半导体器件200的截面图,而图10B 示出了X-Z平面中的半导体器件200的截面图。如图10A和图10B所示,面对栅极沟槽272的栅极间隔件260的侧壁270具有非直线的轮廓。非直线轮廓可能主要由轰击期间从伪栅极堆叠件的顶面反射的离子,其后撞击侧壁270引起。
如图10A所示,侧壁270的中点M被定义为与隔离结构206的顶面垂直距离是栅极间隔件260的高度H1的一半(H1是从栅极隔离层260的最顶部垂直至隔离结构206的顶面测量的)的点。侧壁270的中间部分在中点M周围具有远离栅极沟槽272弯曲的弯曲形状。侧壁270的顶部具有朝向栅极沟槽272延伸第一横向距离L1的弓形结构,第一横向距离L1从中点 M沿Y方向至弓形结构的尖端测量。侧壁270的底部具有朝向栅极沟槽272 延伸第二横向距离L1’的基脚结构,该第二横向距离L1’从中点M沿着Y方向至基脚结构的尖端测量。本发明的发明人已经观察到各向异性蚀刻工艺经常导致L1/H1和L1’/H1均大于约8%。
类似地,如图10B所示,中点M’被定义为侧壁270上的与鳍204的顶面的垂直距离为栅极间隔件260的高度H2(H2是从栅极间隔件260的最顶部分垂直于鳍204的顶面测量的)的一半的点。侧壁270的中间部分在中点M’周围具有远离栅极沟槽272弯曲的弯曲形状。侧壁270的顶部具有朝向栅极沟槽272延伸第一横向距离L2的弓形结构,第一横向距离L2从中点M’沿X方向至弓形结构的尖端测量。侧壁270的底部具有朝向栅极沟槽272 延伸第二横向距离L2’的基脚结构,该第二横向距离L2’从中点M’沿着X 方向至基脚结构的尖端测量。本发明的发明人已经观察到各向异性蚀刻工艺经常导致L2/H2和L2’/H2均大于约8%。
在操作112的可选实施例中,如图2所示,施加使用自由基的各向同性蚀刻方法来蚀刻伪栅极堆叠件212,而不向半导体器件200施加偏置电场以避免引起带电离子轰击。因此,该各向同性蚀刻方法也称为自由基蚀刻。如本文使用的术语“自由基”是指具有至少一个未成对的价电子的原子或分子,并且是电中性的。未成对的电子使自由基具有高度的化学反应性。如本文使用的术语“自由基蚀刻”表示使用自由基作为蚀刻剂并且基本上排除带电离子参与蚀刻的蚀刻工艺。
图11示出了适用于自由基蚀刻的示例性工艺室300’。工艺室300’的具有重复的参考标号的许多组件与图9所示的工艺室300的组件类似,并且为了简洁起见,下面不再重复。与工艺室300不同,工艺室300’不将卡盘 330偏置至电压源。因此,定位在卡盘330上的半导体器件200将不会由偏置电场围绕。此外,工艺室300’的真空室310被选择性调制器件370划分为等离子体区域310a和蚀刻工艺区域310b。半导体器件200定位在蚀刻工艺区域310b中。工艺室300’可以进一步包括气体注入器372,气体注入器372耦合到蚀刻工艺区域310b以将除了第一前体气体343之外的第二前体气体374提供到蚀刻工艺区域310b中。
选择性调制器件370可以是带电光栅,该带电光栅用作阻挡来自等离子体的带电离子运动的屏障,同时允许不带电的等离子体组分(例如,自由基)穿过选择性调制器件370。在实施例中,选择性调制器件370可通过排斥带电等离子体离子或通过吸引带电等离子体离子来防止带电等离子体离子(例如,带正电的离子或带负电的离子)通过。但是,可以使用可以将自由基与等离子体分离的任何合适的器件。
一起参考图2和图11,使用自由基蚀刻的操作112的一个实施例从步骤112a开始,其中将半导体衬底放置在工艺室300’的蚀刻工艺区域310b 中。在步骤112b中,利用第一前体气体343在等离子体区域310a中生成等离子体344。前体气体343可包括一种或多种第一气态组分。在代表性实例中,第一前体气体343可包含例如作为氟自由基源的三氟化氮(NF3);但是可以可选地、结合地或顺序地使用其它自由基源。例如,在另一代表性实例中,根据下式,第一前体气体450可包含作为氟自由基源的三氟化氮(NF3)和作为氢自由基源的分子氢(H2):NF3+H2→NF*+NF2 *+F*+ H*+HF+N*(*表示自由基组分)。对第一前体气体343通电以形成等离子体344,该等离子体344包括设置在等离子体区域310a中的正离子380p、负离子380n和自由基380r。例如,可以采用由RF电源338生成的RF(射频)能量来形成等离子体344。在一些实施例中,RF功率可以在约10瓦至约2500瓦之间,例如在约500瓦至约1500瓦之间。在特定实例中,RF功率为约1200瓦。在一些实施例中,等离子体344可以在单独的区域(例如,在远程等离子体的情况下)中生成,并且随后被引入等离子体区域310a。在步骤112c中,等离子体344的自由基380r分别从等离子体区域310a流至蚀刻工艺区域310b。在所示的实施例中,选择性调制器件370允许自由基380r进入蚀刻工艺区域310b,同时在等离子体区域310a中基本上保持等离子体344的正离子380p和负离子380n。在步骤112d中,将未激发气体374作为第二前体引入到(并且与之化学结合)蚀刻工艺区域310b中的自由基380r。未激发气体374可包括一种或多种气态组分。虽然图1代表性地示出了在引入未激发气体374之前将自由基380r引入到蚀刻工艺区域 310b,但是其它引入顺序也是可能的。例如,在一个实施例中,可以在自由基380r之前将未激发气体374引入到蚀刻工艺区域310b。在另一实施例中,未激发气体374可与自由基380r的引入基本同时地被引入。根据代表性实例,采用三氟化氮(NF3)和分子氢(H2)的混合物作为第一前体气体 343,并且采用分子氢(H2)作为未激发气体(第二前体气体)374,氟(F) 和氢(H)自由基380r与分子氢(H2)结合,根据下式形成原子氢(H) 和氟(F)自由基的络合物:F*+H2→HF+H*。将未激发气体374提供到蚀刻工艺区域310b中,可以微调蚀刻工艺区域310b中的氟原子数与氢原子数的比率(F/H),这将在下面进一步讨论。
在步骤112e中,利用在表面吸附/解吸工艺中通过自由基的化学反应形成的产物来蚀刻伪栅极堆叠件212。氢(H)催化蚀刻工艺。在一个实施例中,伪栅极堆叠件212包括多晶硅(Si),并且在表面吸附工艺中,原子氢(H)和氟(F)自由基的络合物与多晶硅(Si)结合形成四氟化硅(SiF4) 和分子氢(H2)作为表面脱附的气态反应副产物。根据本文所述的一些实施例,含多晶硅的伪栅极堆叠件212的蚀刻速率对含氮化硅的栅极间隔件260的蚀刻速率的选择性可以大于约25:1,诸如在从约50:1至约100:1(例如,约60:1)。因此,在操作112中的自由基蚀刻被认为是基本上没有离子轰击的选择性各向同性蚀刻。
图12A和图12B示出了在通过操作112的自由基蚀刻去除伪栅极堆叠件212之后的半导体器件200。图12A示出了Y-Z平面中的半导体器件200 的截面图,而图12B示出了X-Z平面中的半导体器件200的截面图。与施加离子轰击的图10A和图10B相比,由于施加了没有离子轰击的自由基蚀刻,栅极间隔件260基本上没有遭受侧壁损坏。侧壁270的中间部分基本上是直的。侧壁270的顶部中的弓形结构和侧壁270的底部中的基脚结构的尺寸都显着减小。在各个实施例中,利用自由基蚀刻的操作112通常使得L1/H1和L1’/H1(参考图12A)均小于约8%。诸如小于约3%(例如,在特定实例中为约2%),并且L2/H2和L2’/H2(见图12B)均小于约8%,诸如小于约3%(例如,在特定实例中约为2%)。本发明的发明人已经观察到,当上述比率大于约8%时,栅极结构性能的均匀性劣化,而当上述比率小于约8%时,栅极结构性能的均匀性提高。
在特定实施例中,栅极间隔件260是富氮化物,诸如主要包含氮化硅,而ILD层266是富氧化物,诸如主要包含氧化硅,操作112的自由基蚀刻使用氟(F)和氢(H)自由基作为蚀刻剂,该蚀刻剂对富氧化物材料比对富氮化物的材料具有更高的蚀刻速率。因此,在操作112期间,ILD层266 的顶面上的蚀刻损失可能比栅极间隔件260高。因此,如图12B所示,在两个相邻的栅极沟槽272之间,栅极间隔件-ILD层-栅极间隔件的组合结构的顶面具有凹槽276,该凹槽276的最低点在ILD层266的中心附近。面向栅极沟槽272的栅极间隔件260的侧壁270也高于面向ILD层266的相对侧壁。凹槽276的深度表示为D。在一些实例中,凹槽276的深度与栅极间隔件260的高度的比率(D/H2)可以大于约3%。本发明的发明人已经观察到,大于约3%的D/H2为随后形成的S/D接触件提供了更大的定位面积的性能益处。
对于使用氟(F)和氢(H)自由基作为蚀刻剂的操作112的自由基蚀刻,蚀刻工艺区域310b(图11)中氟原子数与氢原子数的比率(F/H)控制生成为副产物的硅烷的量。当在工艺室中接触水蒸气时,大量的氢(H) 将与衬底上的硅(Si)结合,从而形成硅烷。通过调整进入蚀刻工艺区域 310b的含氢的第二前体气体374的量,可以微调F/H比率。本发明的发明人已经观察到在约90:1000至约96:1000之间的F/H阈值,诸如在特定实例中,阈值为约93:1000,从而使得当F/H比率大于F/H阈值时,将没有足够的H生成硅烷。因此,图12A和图12B中所得的器件不含硅烷。相反地,当F/H比率小于阈值时,诸如在特定实例中小于约93:1000,由于大量的H,硅烷开始作为副产物出现。硅烷通常被认为是蚀刻工艺中的污染源。然而,通过小心地将蚀刻工艺区域310b中的F/H比率控制为略低于F/H阈值,诸如约88:1000,适当控制量的硅烷将形成为覆盖栅极沟槽272的侧壁和底面的薄覆盖膜278,如图13A和图13B所示,其可以用作在随后的操作之前保护半导体器件200的保护层。图13A示出了Y-Z平面中的半导体器件200 的截面图,而图13B示出了X-Z平面中的半导体器件200的截面图。
在操作114中,方法100(图1)示出了在栅极沟槽272中沉积高k金属栅极堆叠件280,诸如图14A和图14B所示。图14A示出了Y-Z平面中的半导体器件200的截面图,而图14B示出了X-Z平面中的半导体器件200 的截面图。如果在先前操作中形成了覆盖膜278,则操作114可以可选地预先实施湿清洁工艺以从栅极沟槽272的侧壁和底面去除硅烷覆盖膜278。高k金属栅极堆叠件280包括高k介电层282和导电层284。高k金属栅极堆叠件280可以进一步包括位于高k介电层282和鳍204之间的界面层 (例如,二氧化硅或氮氧化硅)(未示出)。可以使用化学氧化、热氧化、 ALD、CVD和/或其它合适的方法来形成界面层。
高k介电层282可以包括一种或多种高k介电材料(或一个或多个高 k介电材料层),诸如氧化铪硅(HfSiO)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或它们的组合。可以使用CVD、ALD和/或其它合适的方法来沉积高k介电层282。
导电层284包括一个或多个金属层,诸如功函金属层、导电阻挡层和金属填充层。取决于器件的类型(PFET或NFET),功函金属层可以是p 型或n型功函层。p型功函层包括具有足够大的有效功函数的金属,该金属选自但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合。n型功函层包括具有足够低的有效功函数的金属,该金属选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)或它们的组合。金属填充层可以包括铝(Al)、钨(W)、钴(Co)和/或其它合适的材料。可以使用诸如CVD、PVD、镀和/或其它合适的工艺的方法来沉积导电层 284。
在操作116中,方法100(图1)实施另外的步骤以完成半导体器件 200的制造。例如,如图15所示,方法100可以形成金属互连件,该金属互连件连接各个晶体管以形成完整的IC,诸如S/D接触件288,这是半导体器件200在X-Z平面中的截面图。操作116可以包括在半导体器件200 上方沉积介电层286,蚀刻暴露S/D部件262的接触孔(未示出),以及将一种或多种导电材料沉积到接触孔中以形成S/D接触件288。ILD层266 的凹进的顶面可以便于S/D接触件288的定位。
虽然不旨在限制,但是本发明的一个或多个实施例为半导体器件及其形成提供了许多益处。例如,本发明的实施例提供了栅极形成技术,其维持栅极间隔件的基本直的侧壁轮廓,并且因此维持栅极堆叠件的基本直的侧壁轮廓。栅极形成技术包括无离子轰击的自由基蚀刻。因此,提高了栅极结构性能的均匀性。此外,可以容易地将栅极形成中的自由基蚀刻集成到现有的半导体制造工艺中。
在一个示例性方面,本发明针对方法。该方法包括提供具有衬底和从衬底突出的鳍的结构;在鳍上方形成伪栅极堆叠件;在伪栅极堆叠件的侧壁上形成栅极间隔件;使用自由基蚀刻工艺去除伪栅极堆叠件,从而产生栅极沟槽;在栅极沟槽中形成金属栅极堆叠件。在一些实施例中,自由基蚀刻工艺是各向同性的。在一些实施例中,自由基蚀刻工艺包括将第一蚀刻前体激发成等离子体;以及在使自由基与伪栅极堆叠件接触之前,从等离子体中分离自由基。在一些实施例中,该方法还包括在从等离子体中分离出自由基之后,将自由基与第二蚀刻前体结合。在一些实施例中,第一蚀刻前体不含氧和氯。在一些实施例中,自由基蚀刻工艺包括施加包含氟和氢的自由基。在一些实施例中,自由基蚀刻工艺产生覆盖栅极沟槽的覆盖膜。在一些实施例中,覆盖膜包括硅烷。在一些实施例中,自由基蚀刻工艺包括以氟原子数与氢原子数的比率小于约93:1000施加蚀刻前体。在一些实施例中,伪栅极堆叠件的去除不向该结构施加偏置电场。
在另一示例性方面,本发明针对方法。该方法包括:在工艺室的蚀刻工艺区域中接收结构,该结构包括:位于衬底上方的伪栅极堆叠件和位于伪栅极堆叠件的侧壁上的栅极间隔件;用前体气体在工艺室的等离子体区域中生成等离子体,该等离子体包括自由基和带电离子;使自由基流入蚀刻工艺区域,同时基本上排除带电离子进入蚀刻工艺区域;用自由基蚀刻伪栅极堆叠件,从而形成栅极沟槽;以及在栅极沟槽中形成金属栅极堆叠件。在一些实施例中,该方法还包括在蚀刻工艺区域中接收未激发的气体以与自由基混合。在一些实施例中,自由基和未激发气体都包括氢。在一些实施例中,在蚀刻伪栅极堆叠件期间,自由基和未激发气体包括氟和氢。在一些实施例中,氟原子数与氢原子数的比率大于约93:1000。在一些实施例中,氟原子数与氢原子数的比率小于93:1000,从而使得伪栅极堆叠件的蚀刻使得在栅极沟槽的侧壁上方产生覆盖膜。在一些实施例中,该方法还包括在形成金属栅极堆叠件之前实施湿清洁工艺以去除覆盖膜。
在又一示例性方面,本发明针对半导体器件。该半导体器件包括衬底;从衬底突出的鳍,鳍在第一方向上纵向延伸;与鳍接合的栅极堆叠件,该栅极堆叠件在垂直于第一方向的第二方向上纵向延伸;以及位于栅极堆叠件的侧壁上的栅极间隔件,该栅极间隔件包括与栅极堆叠件的侧壁直接对接的内侧壁和与内侧壁相对的外侧壁,在沿着第一方向的截面图中,内侧壁具有第一高度,并且弓形结构朝向栅极堆叠件延伸第一横向距离,该第一横向距离从内侧壁的中点沿第一方向测量,其中在沿着第一方向的截面图中,外侧壁的第二高度低于内侧壁的第一高度。在一些实施例中,第一横向距离小于第一高度的约8%。在一些实施例中,在沿着第一方向的截面图中,内侧壁具有朝向栅极堆叠件横向延伸第二横向距离的基脚结构,该第二横向距离是从内侧壁的中点沿第一方向测量,其中第二横向距离小于第一高度的约8%。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成半导体器件的方法,包括:
提供具有衬底和从所述衬底突出的鳍的结构;
在所述鳍上方形成伪栅极堆叠件;
在所述伪栅极堆叠件的侧壁上形成栅极间隔件;
使用自由基蚀刻工艺去除所述伪栅极堆叠件,从而产生栅极沟槽;以及
在所述栅极沟槽中形成金属栅极堆叠件。
2.根据权利要求1所述的方法,其中,所述自由基蚀刻工艺是各向同性的。
3.根据权利要求1所述的方法,其中,所述自由基蚀刻工艺包括:
将第一蚀刻前体激发成等离子体;以及
在使自由基与所述伪栅极堆叠件接触之前,从所述等离子体中分离自由基。
4.根据权利要求3所述的方法,还包括:
从所述等离子体中分离所述自由基之后,将所述自由基与所述第二蚀刻前体结合。
5.根据权利要求3所述的方法,其中,所述第一蚀刻前体不含氧和氯。
6.根据权利要求1所述的方法,其中,所述自由基蚀刻工艺包括施加包含氟和氢的自由基。
7.根据权利要求1所述的方法,其中,所述自由基蚀刻工艺产生覆盖所述栅极沟槽的覆盖膜。
8.根据权利要求7所述的方法,其中,所述覆盖膜包括硅烷。
9.一种形成半导体器件的方法,包括:
在工艺室的蚀刻工艺区域中接收结构,所述结构包括位于衬底上方的伪栅极堆叠件和位于所述伪栅极堆叠件的侧壁上的栅极间隔件;
用前体气体在所述工艺室的等离子体区域中生成等离子体,所述等离子体包括自由基和带电离子;
使所述自由基流入蚀刻工艺区域,同时排除所述带电离子进入所述蚀刻工艺区域;
用所述自由基蚀刻所述伪栅极堆叠件,从而产生栅极沟槽;以及
在所述栅极沟槽中形成金属栅极堆叠件。
10.一种半导体器件,包括:
衬底;
鳍,从所述衬底突出,所述鳍在第一方向上纵向延伸;
栅极堆叠件,与所述鳍接合,所述栅极堆叠件在垂直于所述第一方向的第二方向上纵向延伸;以及
栅极间隔件,位于所述栅极堆叠件的侧壁上,所述栅极间隔件包括直接与所述栅极堆叠件的侧壁相接的内侧壁和与所述内侧壁相对的外侧壁,在沿所述第一方向的截面图中,所述内侧壁具有第一高度,并且弓形结构朝向所述栅极堆叠件延伸第一横向距离,所述第一横向距离从所述内侧壁的中点沿所述第一方向测量,其中,在沿所述第一方向的截面图中,所述外侧壁的第二高度低于所述内侧壁的第一高度。
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