TWI708349B - 電子機器 - Google Patents

電子機器 Download PDF

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Publication number
TWI708349B
TWI708349B TW108105416A TW108105416A TWI708349B TW I708349 B TWI708349 B TW I708349B TW 108105416 A TW108105416 A TW 108105416A TW 108105416 A TW108105416 A TW 108105416A TW I708349 B TWI708349 B TW I708349B
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Taiwan
Prior art keywords
semiconductor chip
terminal
bump
bumps
power supply
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Application number
TW108105416A
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English (en)
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TW202011549A (zh
Inventor
青木秀夫
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日商東芝記憶體股份有限公司
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Publication of TW202011549A publication Critical patent/TW202011549A/zh
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Publication of TWI708349B publication Critical patent/TWI708349B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種電子機器包括第一封裝及第二封裝。該第一封裝包括：一第一半導體晶片，其在該第一封裝之相對之第一表面與第二表面之間；複數個端子，其在該第一半導體晶片上面朝垂直於該第一表面及該第二表面之一第一方向，該等端子包括第一輸入/輸出端子及一第二輸入/輸出端子；及複數個凸塊，其在該第一方向上處於該第一半導體晶片正下方之位置處電性連接至該複數個第一輸入/輸出端子。該第二封裝包括：一第二半導體晶片，其設置於該第一封裝之該第二表面上；一導線，其將該第二半導體晶片電性連接至一導體，該導體電連接至該第二輸入/輸出端子；及塗層樹脂，其覆蓋該第一封裝之該第二表面、該第二半導體晶片及該導線。

Description

電子機器
本文中所描述之實施例大體上係關於一種電子機器。
控制器晶片及複數個記憶體晶片堆疊於基板上之半導體儲存裝置為吾人所知。半導體儲存裝置封裝為例如球狀柵格陣列(ball grid array，BGA)，其中複數個焊球設置於基板之底表面上。
控制器晶片經由焊球向處理器傳輸信號並自處理器接收信號。當處理器與控制器晶片之間的電路徑中存在阻抗失配時，信號品質會退化。
本文中所描述之實施例提供一種改良型電子機器。
一實施例提供，一種電子機器，其包含：一第一封裝，其包括：一第一表面，其面朝一第一方向；一第二表面，其與該第一表面相對；一第一半導體晶片，其設置於該第一表面與該第二表面之間；複數個第一端子，其設置於該第一半導體晶片上且面朝該第一方向；一第二端子，其設置於該第一半導體晶片上且面朝該第一方向；一電力供應端子；一第一層間連接導體，其在與該第一方向相交之一 第二方向上與該第一半導體晶片間隔開；一第一連接導體，其將該第二端子與該第一層間連接導體彼此連接；一第二連接導體，其至少一部分設置於該第二表面上且其連接至該第一層間連接導體；複數個第一凸塊，其電性連接至該複數個第一端子且在該第一方向上處於該第一半導體晶片正下方之位置處自該第一表面突出；及一電力供應凸塊，其電性連接至該電力供應端子，其中在該等第一凸塊與該電力供應凸塊之間不存在不在該第一方向上處於該第一半導體晶片正下方之凸塊；一第二半導體晶片，其設置於該第二表面上；一導線，其將該第二半導體晶片與該第二連接導體彼此電性連接；及一第二封裝，其包括覆蓋該第二表面、該第二半導體晶片及該導線之一塗層樹脂。
一實施例提供，一種電子機器，其包含：一第一半導體晶片，其包括：複數個第一端子，其面朝一第一方向；一第二端子，其面朝該第一方向；一電力供應端子，其面朝該第一方向；及複數個第一凸塊，其連接至該複數個第一端子；一第一基板，其包括：一第一端子表面，其面朝該第一方向；一第二端子表面，其與該第一端子表面相對且面朝該第一半導體晶片；複數個外部凸塊，其自該第一端子表面突出，且包括在該第一方向上處於該第一半導體晶片正下方之位置處之第二凸塊及電性連接至該電力供應端子之一電力供應凸塊，其中在該等第二凸塊與該電力供應凸塊之間不存在不在該第一方向上處於該第一半導體晶片正下方之外部凸塊；複數個連接導體， 其設置於該等連接導體在該第一方向上處於該第一半導體晶片正下方之位置處，且將該複數個第一凸塊與該複數個外部凸塊彼此連接；一第一連接端子，其設置於該第二端子表面上且電性連接至該第二端子；一第二連接端子，其設置於該第二端子表面上；及一連接佈線，其將該第一連接端子與該第二連接端子彼此連接；一第二半導體晶片，其設置於該第一半導體晶片上；一導線，其將該第二半導體晶片與該第二連接端子彼此電性連接；及一塗層樹脂，其覆蓋該第二端子表面、該第一半導體晶片及該第二半導體晶片。
另外，一實施例提供，一種電子機器，其包含：一第一封裝，其包括：一第一表面，其面朝一第一方向；一第二表面，其與該第一表面相對；一第一半導體晶片，其設置於該第一表面與該第二表面之間；複數個第一輸入/輸出端子，其設置於該第一半導體晶片上且面朝該第一方向；一第二輸入/輸出端子，其設置於該第一半導體晶片上且面朝該第一方向；一電力供應端子；一第一層間連接導體，其在與該第一方向相交之一第二方向上與該第一半導體晶片間隔開；一第一連接導體，其將該第二輸入/輸出端子與該第一層間連接導體彼此連接；一第二連接導體，其至少一部分設置於該第二表面上且其連接至該第一層間連接導體；複數個第一凸塊，其電性連接至該複數個第一輸入/輸出端子且在該第一方向上處於該第一半導體晶片正下方之位置處自該第一表面突出；及一電力供應凸塊，其電性連接至該電力供應端子，其中在該等第一 凸塊與該電力供應凸塊之間不存在不在該第一方向上處於該第一半導體晶片正下方之凸塊，一模製樹脂，其囊封該第一半導體晶片，及形成於該第一半導體晶片之面朝該第一方向之一表面上的一絕緣層；複數個第二半導體晶片，其堆疊於該第二表面上；一導線，其將該複數個第二半導體晶片與該第二連接導體彼此電性連接；一第二封裝，其包括覆蓋該第二表面、該第二半導體晶片及該導線之一塗層樹脂；一第三半導體晶片，其控制該第一半導體晶片；及一基板，其包括連接至該複數個第一凸塊及該第三半導體晶片之複數個佈線，其中該第一凸塊在該第二方向上之一最大寬度小於或等於該等佈線之一最大寬度。
1:電子機器
5:主板
5a:層
5b:層
6:處理器
7:半導體儲存裝置
8:底填充料
9:佈線
9a:第一部分
9b:第二部分
9c:通孔
11:第一封裝
11a:下表面
11b:上表面
12:記憶體晶片
12a:黏合層
13:導線
14:密封樹脂
15:記憶體控制器
15a:下表面
15b:上表面
15c:側表面
16:第一輸入/輸出端子
16a:襯墊
16b:障壁金屬
17:第二輸入/輸出端子
18:電力供應端子
21:封裝層
21a:下表面
21b:上表面
22:第一絕緣層
23:第一佈線層
23a:襯墊
23b:連接佈線
23c:電力供應佈線
24:第二絕緣層
25:第二佈線層
25a:連接端子
25b:連接佈線
26:第三絕緣層
27:通孔
28:凸塊
29:電力供應凸塊
31:導電層
41:基板
41a:下表面
41b:上表面
45:控制器凸塊
46:連接凸塊
47:電力供應凸塊
51:基座
51a:下表面
51b:上表面
52:連接導體
52a:第一襯墊
52b:第二襯墊
52c:通孔
53:第一連接端子
54:第二連接端子
55:連接佈線
56:電力供應佈線
56a:第一電力供應導體
56b:第二電力供應導體
56c:電力供應通孔
57:第一絕緣層
58:第二絕緣層
61:外部凸塊
62:電力供應凸塊
D1:直徑
D2:直徑
D3:直徑
D4:直徑
D5:直徑
W:寬度
圖1係示意性地繪示根據第一實施例之電子機器的平面圖。
圖2係示意性地繪示根據第一實施例之半導體儲存裝置的橫截面圖。
圖3係示意性地繪示根據第一實施例之半導體儲存裝置之一部分的橫截面圖。
圖4係示意性地繪示第一實施例中之佈線及凸塊的透視圖。
圖5係示意性地繪示根據第二實施例之半導體儲存裝置之一部分的橫截面圖。
圖6係示意性地繪示根據第三實施例之半導體儲存裝置的橫截面圖。
圖7係示意性地繪示根據第三實施例之半導體儲存裝置之一部分的橫截面圖。
相關申請案之交叉參考
本申請案係基於並主張2018年9月14日申請之日本專利申請案第2018-173030號的優先權益，該申請案之全部內容以引用之方式併入本文中。
一般而言，根據一個實施例，一種電子機器，具體而言，一種半導體儲存裝置，包括：第一封裝，其包括第一半導體晶片；及第二封裝，其包括第二半導體晶片。第一封裝包括：相對之第一表面與第二表面；複數個第一端子，其設置於第一半導體晶片上且面朝第一方向；第二端子，其設置於第一半導體晶片上且面朝第一方向；電力供應端子；第一層間連接導體，其在與第一方向相交之第二方向上與第一半導體晶片間隔開；第一連接導體，其將第二端子與第一層間連接導體彼此連接；第二連接導體，其至少一部分設置於第二表面上且其連接至第一層間連接導體；複數個第一凸塊，其電性連接至複數個第一端子且在第一方向上處於第一半導體晶片正下方之位置處自第一表面突出；及電力供應凸塊，其電性連接至電力供應端子，其中在第一凸塊與電力供應凸塊之間不存在不在第一方向上處於第一半導體晶片正下方之凸塊。第二封裝包括：塗層樹脂，其覆蓋第二表面；第二半導體晶片，其設置於第二表面上；及導線，其將第二半導體晶片與第二連接導體彼此電性連接。
第一實施例
在下文中，將參考圖1至圖4描述第一實施例。在本發明中，可使用兩個或更多個不同表達來描述根據實施例之相同組件及其描述。組件及其描述不限於本發明之表達。可使用不同於在本發明中使用之名稱的名稱來指定組件。另外，可使用不同於在本發明中使用之表達的表達來描述組件。
圖1係示意性地繪示根據第一實施例之電子機器1的平面圖。該實施例之電子機器1之一個實例係智慧型電話。電子機器1亦可為例如個人電腦、攜帶型電腦、平板電腦、其他類型之行動電話、電視接收器、USB隨身碟、SD卡、嵌入式多媒體卡(embedded Multi Media Card，eMMC®)、記憶卡、其他儲存裝置、可穿戴式裝置、智慧型揚聲器、家庭電氣設備或其他裝置。
如圖1中所繪示，電子機器1包括主板5、處理器6、半導體儲存裝置7及底填充料8。主板5係基板之實例。子板係基板之另一實例。處理器6係控制器之實例。電子機器1可進一步包括例如外殼或顯示裝置等其他組件。
主板5係例如印刷電路板(printed circuit board，PCB)。主板5包括複數個佈線9。佈線9將處理器6與半導體儲存裝置7彼此電性連接。
處理器6及半導體儲存裝置7安裝於主板5上。處理器6係例如系統單晶片(system-on-a-chip，SoC)。處理器6亦可為積體電路(integrated circuit，IC)或電路。處理器6控制包括半導體儲存裝置7之電子機器1。
圖2係示意性地繪示根據第一實施例之半導體儲存裝置7的 橫截面圖。該實施例之半導體儲存裝置7之一個實例係固態磁碟機(solid state drive，SSD)，更一般而言係半導體封裝。半導體儲存裝置7可為另一裝置，例如eMMC或通用快閃儲存體(Universal Flash Storage，UFS)。
在本發明中，X軸、Y軸及Z軸如圖式中之每一者中所繪示而定義。X軸、Y軸與Z軸彼此垂直。X軸被定義為沿著半導體儲存裝置7之寬度方向。Y軸被定義為沿著半導體儲存裝置7之長度(或深度)方向。Z軸被定義為沿著半導體儲存裝置7之高度(或厚度)方向。
半導體儲存裝置7包括第一封裝11，以及包括複數個記憶體晶片12、複數個導線13及密封樹脂14之第二封裝。密封樹脂14係塗層樹脂之實例。在第一實施例中，記憶體控制器15設置於第一封裝11中。
另外，半導體儲存裝置7可進一步包括例如電力供應電路等其他組件。半導體儲存裝置7之電力供應電路自供應自電子機器1之電力供應電路之外部直流電力產生複數個不同內部直流電力供應電壓。電力供應電路向半導體儲存裝置7中之各別電路供應內部直流電力供應電壓。電力供應電路偵測外部電力之升高，產生通電重設信號，且向記憶體控制器15供應通電重設信號。
第一封裝11係具有扇出封裝(fan out package，FOP)或扇出晶圓級封裝(fan out wafer level package，FOWLP)之結構之半導體封裝。第一封裝11不限於此實例。
第一封裝11包括下表面11a及上表面11b。為了易於理解，本發明中之表達「上」及「下」將基於圖式中之每一者之上下方向而使用，且不限制組件中之每一者之位置及方向。
下表面11a係面朝Z軸之負方向(與Z軸之箭頭相對之方向)之實質上平坦表面。上表面11b係與下表面11a相對之實質上平坦表面，且面朝Z軸之正方向(由Z軸之箭頭指示之方向)。
第一封裝11包括記憶體控制器15且覆蓋記憶體控制器15。因此，記憶體控制器15定位於第一封裝11之下表面11a與上表面11b之間。記憶體控制器15可形成第一封裝11之下表面11a上表面11b之至少一部分。換言之，記憶體控制器15可自下表面11a及上表面11b之至少一部分曝露。
記憶體控制器15控制例如在記憶體晶片12中儲存資料及自記憶體晶片12讀取資料。記憶體控制器15不僅可控制記憶體12，而且可控制半導體儲存裝置7中之其他電子組件。
記憶體控制器15經由連接介面(I/F)電性連接至處理器6。連接介面遵守例如UFS或PCI高速(周邊組件互連高速，Peripheral Component Interconnect Express，PCIe)等標準。
記憶體控制器15包括下表面15a、上表面15b及側表面15c。下表面15a係面朝Z軸之負方向之實質上平坦表面。上表面15b係與下表面15a相對地定位且面朝Z軸之正方向之實質上平坦表面。側表面15c定位於下表面15a之邊緣與上表面15b之邊緣之間，且面朝X軸方向及Y軸方向。
記憶體控制器15進一步包括複數個第一輸入/輸出端子16、第二輸入/輸出端子17及電力供應端子18。第一輸入/輸出端子16、第二輸入/輸出端子17及電力供應端子18中之每一者形成為圓形形狀，但可形成為例如四邊形形狀等另一形狀。
第一輸入/輸出端子16、第二輸入/輸出端子17及電力供應端子18設置於下表面15a上且面朝Z軸之負方向。第一輸入/輸出端子16、第二輸入/輸出端子17及電力供應端子18以例如點陣(矩陣)形狀配置。
第一輸入/輸出端子16設置於連接介面中，且係例如記憶體控制器15之用於傳輸及接收差分信號之端子。替代地，第一輸入/輸出端子16可為用於傳輸及接收另一信號之端子。當記憶體控制器15向處理器6傳輸資料及自處理器6接收資料時，使用第一輸入/輸出端子16。
當記憶體控制器15向記憶體12傳輸資料及自記憶體12接收資料時，使用第二輸入/輸出端子17。電力供應端子18電性連接至電子機器1之電力供應電路。記憶體控制器15經由電力供應端子18自電子機器1之電力供應電路供應外部直流電力。
記憶體控制器15可包括複數個其他端子，該等端子包括例如連接至接地之端子或與電路分離來固定記憶體控制器15之襯墊。
第一封裝11進一步包括封裝層21、第一絕緣層22、第一佈線層23、第二絕緣層24、第二佈線層25、第三絕緣層26、通孔27、複數個凸塊28及電力供應凸塊29。通孔27係層間連接導體之實例。
封裝層21由例如包括例如環氧樹脂等合成樹脂作為模製樹脂等及由無機材料形成之填充劑之材料形成，且具有絕緣性質。封裝層21覆蓋記憶體控制器15之上表面15b及側表面15c。因此，封裝層21之一部分相對於記憶體控制器15定位於與Z軸之負方向相交之方向上。
封裝層21包括下表面21a及上表面21b。下表面21a係面朝Z軸之負方向之實質上平坦表面。下表面21a與記憶體控制器15之下表面15a實質上相連。上表面21b係面朝Z軸之正方向之實質上平坦表面。上表 面21b在Z軸之正方向上與記憶體控制器15之上表面15b間隔開。
第一絕緣層22由例如合成樹脂形成且具有絕緣性質。第一絕緣層22可包括無機填充劑以便調整其彈性模數及熱膨脹係數。第一絕緣層22覆蓋記憶體控制器15之下表面15a及封裝層21之下表面21a。在第一絕緣層22中，設置複數個開口，第一輸入/輸出端子16、第二輸入/輸出端子17及電力供應端子18自該等開口曝露。
第一佈線層23由例如銅等導體形成且設置於第一絕緣層22上。第一佈線層23包括複數個襯墊23a、連接佈線23b及電力供應佈線23c。連接佈線23b係連接導體之實例。
圖3係示意性地繪示根據第一實施例之半導體儲存裝置7之一部分的橫截面圖。如圖3中所繪示，襯墊23a中之每一者處於對應第一輸入/輸出端子16正下方，且連接至第一輸入/輸出端子16。
襯墊23a之橫截面積實質上等於第一輸入/輸出端子16之橫截面積。在本發明中，除非另外規定，否則橫截面積係指垂直於Z軸之負方向之橫截面積。
連接佈線23b之一個末端部分連接至第二輸入/輸出端子17。在第二輸入/輸出端子17與在與Z軸之負方向相交之方向上與記憶體控制器15間隔開的位置之間，連接佈線23b沿著第一封裝11之下表面11a延伸。
如圖2中所繪示，電力供應佈線23c之一個末端部分連接至電力供應端子18。在電力供應端子18與在與Z軸之負方向相交之方向上與記憶體控制器15間隔開的位置之間，電力供應佈線23c沿著第一封裝11之下表面11a延伸。
第二絕緣層24係例如防焊劑，且設置於第一絕緣層22及第一佈線層23上。第二絕緣層24形成第一封裝11之下表面11a。在第二絕緣層24中，設置複數個開口，襯墊23a及電力供應佈線23c之另一末端部分自該等開口曝露。因此，襯墊23a及電力供應佈線23c之另一末端部分設置於第一封裝11之下表面11a上。
第二佈線層25由例如銅等導體形成，且設置於封裝層21之上表面21b上。第二佈線層25包括連接端子25a及連接佈線25b。連接端子25a及連接佈線25b各自係連接導體之實例。第二佈線層25可包括另一佈線。
連接佈線25b連接至連接端子25a。在連接端子25a與在與Z軸之負方向相交之方向上與記憶體控制器15間隔開的位置之間，連接佈線25b沿著第一封裝11之上表面11b延伸。
第三絕緣層26係例如防焊劑，且設置於封裝層21之上表面21b及第二佈線層25上。第三絕緣層26形成第一封裝11之上表面11b。在第三絕緣層26中，設置開口，連接端子25a自該開口曝露。因此，連接端子25a設置於第一封裝11之上表面11b上。
複數個通孔27設置於封裝層21中且在Z軸方向上穿透封裝層21。通孔27包括通過封裝層21之孔及設置於孔中或孔之內部表面上之導體。藉由例如雷射束加工或鍍敷，孔設置於由合成樹脂形成之封裝層21中。
通孔27在與Z軸之負方向相交之方向上與記憶體控制器15間隔開，且將第一佈線層23之連接佈線23b與第二佈線層25之連接佈線25b彼此連接。因此，第一佈線層23之連接佈線23b將第二輸入/輸出端子 17與通孔27彼此連接。另外，第二佈線層25之連接佈線25b連接至通孔27以便將通孔27與連接端子25a彼此連接。替代地，在未提供連接佈線25b之情況下，通孔27可將第一佈線層23之連接佈線23b與連接端子25a彼此連接。
如圖3中所繪示，凸塊28係例如半球面焊料凸塊。凸塊28可形成為另一形狀。當連接至襯墊23a時，凸塊28經由襯墊23a電性連接至第一輸入/輸出端子16。
襯墊23a及凸塊28定位於襯墊23a及凸塊28在Z軸之負方向上處於襯墊23a及凸塊28電性連接至之第一輸入/輸出端子16正下方之位置處。因此，襯墊23a及凸塊28設置於襯墊23a及凸塊28在Z軸之負方向上處於記憶體控制器15正下方之位置處。凸塊28在Z軸之負方向上自設置於第一封裝11之下表面11a上之襯墊23a突出。
如圖2中所繪示，電力供應凸塊29係例如半球面焊料凸塊。電力供應凸塊29可形成為另一形狀。在與Z軸之負方向相交之方向上與記憶體控制器15間隔開的位置處，電力供應凸塊29連接至電力供應佈線23c之末端部分。因此，電力供應佈線23c將電力供應端子18與電力供應凸塊29彼此連接。電力供應凸塊29在Z軸之負方向上自電力供應佈線23c之設置於第一封裝11之下表面11a上之末端部分突出。
藉由覆晶安裝，半導體儲存裝置7安裝於主板5上。凸塊28及電力供應凸塊29連接至設置於主板5上之襯墊。當半導體儲存裝置7安裝於主板5上時，凸塊28經由圖1之佈線9連接至處理器6。另外，電力供應凸塊29連接至電子機器1之電力供應電路。
第一封裝11可包括複數個其他凸塊。凸塊包括例如連接至 接地襯墊之凸塊或與電路分離來固定半導體儲存裝置7之凸塊。
第一封裝11可進一步包括由圖2中之兩點劃線指示之導電層31。導電層31係例如金屬板。導電層31設置於封裝層21中且定位於封裝層21之上表面21b與記憶體控制器15之上表面15b之間。
導電層31在Z軸之負方向上與記憶體控制器15重疊。因此，導電層31阻擋自記憶體控制器15及外部源產生之電磁雜訊。另外，導電層31用於記憶體控制器15之熱耗散。
記憶體12係例如NAND快閃記憶體且儲存資訊。記憶體12可為例如NOR快閃記憶體等另一記憶體。記憶體晶片12堆疊於第一封裝11之上表面11b上。
在記憶體晶片12中之每一者之下表面上，設置有黏合層12a。黏合層12a係晶粒附接膜(die attach film，DAF)，且由例如包括丙烯酸聚合物及環氧樹脂之材料形成。晶粒附接膜將亦被稱作晶粒接合膜。黏合層12a可含有黏合材料。記憶體12可經由黏合層12a接合至另一記憶體12或第一封裝11之上表面11b。
導線13係例如接合線。導線13將一個記憶體12與另一記憶體12彼此連接，或將記憶體12與設置於第一封裝11之上表面11b上之連接端子25a彼此連接。因此，導線13將記憶體晶片12與連接端子25a彼此電性連接。
記憶體控制器15之第二輸入/輸出端子17經由連接佈線23b、通孔27、連接佈線25b、連接端子25a及導線13電性連接至記憶體晶片12。因此，記憶體控制器15向記憶體晶片12傳輸信號及自記憶體晶片12接收信號，且可控制記憶體晶片12。
密封樹脂14係例如模製樹脂，且由包括其中混合例如二氧化矽等無機材料之環氧樹脂之合成樹脂形成。密封樹脂14可由包括另一種合成樹脂之材料形成。密封樹脂14之材料及封裝層21之材料都包括環氧樹脂。因此，密封樹脂14之熱膨脹係數與封裝層21之熱膨脹係數彼此類似。
密封樹脂14密封並覆蓋第一封裝11之上表面11b、記憶體晶片12及導線13。第一封裝11之上表面11b、記憶體晶片12及導線13嵌入於密封樹脂14中。換言之，第一封裝11之上表面11b、記憶體晶片12及導線13容納於密封樹脂14中且存在於密封樹脂14中。
圖3中所繪示之凸塊28之直徑D1小於或等於凸塊28電性連接至之第一輸入/輸出端子16之直徑D2，其中直徑D1係凸塊28之垂直於Z軸之負方向之方向上的寬度。因此，凸塊28之橫截面積小於或等於凸塊28電性連接至之第一輸入/輸出端子16之橫截面積。
圖4係示意性地繪示第一實施例中之佈線9及凸塊28的透視圖。圖4中所繪示之主板5係多層板且包括複數個層5a及5b。層5a及5b可為設置於主板5之表面上之層，或可為設置於主板5中之層。
佈線9包括第一部分9a、第二部分9b及通孔9c。通孔9c係層間連接導體之實例。第一部分9a係設置於層5a中之佈線圖案。第二部分9b係設置於層5b中之佈線圖案。通孔9c在層5a與層5b之間穿透主板5，且將第一部分9a與第二部分9b彼此連接。在一些實施例中，佈線9可設置於單層中，使得不提供通孔9c。
凸塊28之直徑D1小於或等於通孔9c之直徑D3。直徑D3係通孔9c之寬度。另外，凸塊28之直徑D1小於或等於佈線9之第一部分9a之 寬度W。除了通孔9c以外，佈線9之寬度實質上恆定。因此，凸塊28之直徑D1亦小於或等於佈線9之第二部分9b之寬度。
如由圖2中之兩個點劃線所指示，底填充料8填充於藉由覆晶安裝而安裝之半導體儲存裝置7與主板5之間。底填充料8防止對凸塊28與電力供應凸塊29之間的連接部分及主板5之襯墊之損壞。
在處理器6與記憶體控制器15之間的電路徑中，大寄生電容可產生於比其他部分具有更大橫截面積之部分(下文被稱作「延伸部分」)中。在延伸部分中，阻抗減小。阻抗減小之量在延伸部分之橫截面積增大時變得更大。阻抗減小會引起電路徑中之阻抗失配，使得UFS或PCIe中傳輸及接收之信號之品質高速退化。
在該實施例中，凸塊28之橫截面積小於或等於第一輸入/輸出端子16之橫截面積。另外，凸塊28之直徑D1小於或等於通孔9c之直徑D3及佈線9之寬度中之每一者。因此，使凸塊28中之阻抗減小之量更小，且避免處理器6與記憶體控制器15傳輸及接收之信號之品質退化。
在根據上文所描述之第一實施例之電子機器1中，凸塊28在凸塊28在Z軸之負方向上處於記憶體控制器15正下方之位置處自第一封裝11之下表面11a突出，且電性連接至第一輸入/輸出端子16。因此，凸塊28與第一輸入/輸出端子16之間的電路徑比凸塊28在與Z軸之負方向相交之方向上與記憶體控制器15間隔開時更短。另外，凸塊28容納於凸塊28在Z軸之負方向上處於記憶體控制器15正下方之位置處，使得凸塊28之大小受到限制。因此，凸塊28之大小被設定成比至少一個凸塊28在與Z軸之負方向相交之方向上與記憶體控制器15間隔開時更小。因此，在第一輸入/輸出端子16與凸塊28之間的電路徑中，避免了由寄生電容增大引起之阻 抗減小，且避免了由阻抗失配引起之半導體儲存裝置7之信號品質退化。
記憶體控制器15設置於第一封裝11中，且定位於第一封裝11之下表面11a與上表面11b之間。因此，可使半導體儲存裝置7比記憶體控制器15安裝於基板上時更薄。
凸塊28設置於凸塊28在Z軸之負方向上處於凸塊28電性連接至之第一輸入/輸出端子16正下方之位置處。因此，減少凸塊28與第一輸入/輸出端子16之間的電路徑，且電路徑之設計係簡單的。
凸塊28垂直於Z軸之負方向之橫截面積小於或等於第一輸入/輸出端子16之橫截面積。因此，在第一輸入/輸出端子16與凸塊28之間的電路徑中，避免了由凸塊28之寄生電容增大引起之阻抗減小。因此，避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
凸塊28之垂直於Z軸之負方向之方向上的直徑D1小於或等於佈線9之寬度W。因此，在第一輸入/輸出端子16與處理器6之間的電路徑中，避免了由凸塊28之寄生電容增大引起之阻抗減小。因此，避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
垂直於Z軸之負方向之方向上之凸塊28之直徑D1小於或等於通孔9c之直徑D3。因此，在第一輸入/輸出端子16與處理器6之間的電路徑中，避免了由凸塊28之寄生電容增大引起之阻抗減小。因此，避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
第一封裝11之上表面11b大於記憶體控制器15之上表面15b。記憶體晶片12堆疊於第一封裝11之上表面11b上。因此，記憶體晶片12可穩定地堆疊。
在第一實施例中，凸塊28設置於凸塊28在Z軸之負方向上 處於第一輸入/輸出端子16正下方之位置處。但是，在其他實施例中，凸塊28可在與Z軸之負方向相交之方向上與第一輸入/輸出端子16間隔開，只要凸塊28定位於凸塊28在Z軸之負方向上處於記憶體控制器15正下方之位置處即可。
第二實施例
在下文中，將參考圖5描述第二實施例。在以下實施例之描述中，與上文所描述之組件具有相同功能之組件由與上述組件相同之附圖標記表示，且將不重複描述。另外，由相同附圖標記表示之組件之所有功能及性質不必共用，且由相同附圖標記表示之組件可具有根據實施例中之每一者之不同功能及性質。
圖5係示意性地繪示根據第三實施例之半導體儲存裝置7之一部分的橫截面圖。如圖5中所繪示，在第二實施例中，第一輸入/輸出端子16包括襯墊16a及障壁金屬16b。
襯墊16a由例如銅、銅合金、鋁或鋁合金等導體形成，且係設置於記憶體控制器15之下表面15a上之端子。襯墊16a自設置於第一絕緣層22中之開口曝露。
障壁金屬16b由導體形成，例如鈦、鎳、鎢、鈷、鈀或金。障壁金屬16b覆蓋曝露之襯墊16a且連接至襯墊16a。
凸塊28係例如焊料凸塊或包括銅及焊料之銅柱凸塊，且連接至障壁金屬16b。亦即，凸塊28直接連接至第一輸入/輸出端子16。因此，記憶體控制器15之第一輸入/輸出端子16實際上用作半導體儲存裝置7之輸入/輸出端子。替代地，可不提供障壁金屬16b，使得凸塊28直接連接至襯墊16a。
在根據第二實施例之電子機器1中，凸塊28直接連接至第一輸入/輸出端子16。因此，凸塊28之大小類似於第一輸入/輸出端子16之大小。因此，在第一輸入/輸出端子16與凸塊28之間的電路徑中，避免了由寄生電容增大引起之阻抗減小，且避免了由阻抗失配引起之半導體儲存裝置7之信號品質退化。
第三實施例
在下文中，將參考圖6及圖7描述第三實施例。圖6係示意性地繪示根據第三實施例之半導體儲存裝置7之一部分的橫截面圖。如圖6中所繪示，根據第三實施例之半導體儲存裝置7包括記憶體晶片12、導線13、密封樹脂14、記憶體控制器15及基板41。
根據第三實施例之記憶體控制器15進一步包括複數個控制器凸塊45、連接凸塊46及電力供應凸塊47。控制器凸塊45、連接凸塊46及電力供應凸塊47係例如半球面焊料凸塊，且在Z軸之負方向上自記憶體控制器15之下表面15a突出。
控制器凸塊45連接至第一輸入/輸出端子16。連接凸塊46連接至第二輸入/輸出端子17。電力供應凸塊47連接至電力供應端子18。
基板41係例如印刷佈線板。基板41包括下表面41a及上表面41b。下表面41a係端子表面之實例。上表面41b係端子表面之實例。
下表面41a係面朝Z軸之負方向之實質上平坦表面。上表面41b係與下表面41a相對地定位且面朝Z軸之正方向之實質上平坦表面。上表面41b面朝記憶體控制器15之下表面15a。
基板41進一步包括基座51、複數個連接導體52、第一連接端子53、第二連接端子54、連接佈線55、電力供應佈線56、第一絕緣層 57、第二絕緣層58、複數個外部凸塊61及電力供應凸塊62。
基座51由絕緣材料形成。基座51包括下表面51a及上表面51b。下表面51a係面朝Z軸之負方向之實質上平坦表面。上表面51b係面朝Z軸之正方向之實質上平坦表面。
圖7係示意性地繪示根據第三實施例之半導體儲存裝置7之一部分的橫截面圖。連接導體52由例如銅等導體形成。連接導體52中之每一者包括第一襯墊52a、第二襯墊52b及通孔52c。
第一襯墊52a設置於基座51之下表面51a上。第二襯墊52b設置於基座51之上表面51b上，且面朝第一輸入/輸出端子16及控制器凸塊45。第一襯墊52a及第二襯墊52b中之每一者形成為圓形形狀，但可形成為例如四邊形形狀等另一形狀。通孔52c設置於基座51中，且在Z軸方向上穿透基座51。通孔52c連接第一襯墊52a與第二襯墊52b。
第一連接端子53、第二連接端子54及連接佈線55由例如銅等導體形成，且設置於基座51之上表面51b上。第一連接端子53面朝第二輸入/輸出端子17。第二連接端子54設置於在與Z軸之負方向相交之方向上與記憶體控制器15間隔開的位置處。連接佈線55連接第一連接端子53與第二連接端子54。障壁金屬可形成於第一連接端子53之表面上以便改良焊料連接性，且鎳/金鍍層可形成於第二連接端子54之表面上以便改良導線黏合性。
圖6中所繪示之電力供應佈線56由例如銅等導體形成，且包括第一電力供應導體56a、第二電力供應導體56b及電力供應通孔56c。在該實施例中，第一電力供應導體56a及第二電力供應導體56b係佈線圖案，但襯墊僅可為襯墊。
第一電力供應導體56a設置於基座51之下表面51a上。第二電力供應導體56b設置於基座51之上表面51b上。電力供應通孔56c設置於基座51中，且在Z軸方向上穿透基座51。電力供應通孔56c連接第一電力供應導體56a與第二電力供應導體56b。
在電力供應通孔56c與在與Z軸之負方向相交之方向上與記憶體控制器15間隔開的位置之間，第一電力供應導體56a沿著基板41之下表面41a延伸。在電力供應通孔56c與第二電力供應導體56b在Z軸之負方向上處於記憶體控制器15正下方之位置之間，第二電力供應導體56b沿著基板41之上表面41b延伸。
第一絕緣層57係例如防焊劑，且設置於基座51之下表面51a上。第一絕緣層57形成基板41之下表面41a。在第一絕緣層57中，設置複數個開口，第一襯墊52a及第一電力供應導體56a之末端部分自該等開口曝露。因此，第一襯墊52a及第一電力供應導體56a之末端部分設置於基板41之下表面41a上。第一電力供應導體56a之末端部分可處於襯墊正下方，如同其他連接導體之狀況下。
第二絕緣層58係例如防焊劑且設置於基座51之上表面51b上。第二絕緣層58形成基板41之上表面41b。在第二絕緣層58中，設置複數個開口，第二襯墊52b、第一連接端子53、第二連接端子54及第二電力供應導體56b之末端部分自該等開口曝露。因此，第二襯墊52b、第一連接端子53、第二連接端子54及第二電力供應導體56b之末端部分設置於基板41之上表面41b上。
藉由覆晶安裝，記憶體控制器15安裝於基板41上。控制器凸塊45連接至連接導體52之第二襯墊52b。連接凸塊46連接至第一連接端 子53。因此，第一連接端子53經由連接凸塊46電性連接至第二輸入/輸出端子17。另外，電力供應凸塊47連接至第二電力供應導體56b之末端部分。因此，電力供應佈線56電性連接至電力供應端子18。
如圖7中所繪示，連接導體52中之每一者設置於連接導體52在Z軸之負方向上處於連接導體52電性連接至之第一輸入/輸出端子16正下方之位置處。因此，連接導體52設置於連接導體52在Z軸之負方向上處於記憶體控制器15正下方之位置處。
外部凸塊61係例如半球面焊料凸塊且連接至連接導體52之第一襯墊52a。因此，連接導體52將控制器凸塊45與外部凸塊61彼此連接。外部凸塊61經由連接導體52及控制器凸塊45電性連接至第一輸入/輸出端子16。
外部凸塊61定位於外部凸塊61在Z軸之負方向上處於外部凸塊61電性連接至之第一輸入/輸出端子16正下方之位置處。因此，外部凸塊61定位於外部凸塊61在Z軸之負方向上處於記憶體控制器15正下方之位置處。外部凸塊61在Z軸之負方向上自設置於基板41之下表面41a上之第一襯墊52a突出。
如圖6中所繪示，電力供應凸塊62係例如半球面焊料凸塊。在與Z軸之負方向相交之方向上，電力供應凸塊62在與記憶體控制器15間隔開之位置處連接至電力供應佈線56之第一電力供應導體56a之末端部分。因此，電力供應佈線56將電力供應端子18與電力供應凸塊62彼此連接。電力供應凸塊62在Z軸之負方向上自第一電力供應導體56a之設置於基板41之下表面41a上之末端部分突出。
藉由覆晶安裝，半導體儲存裝置7安裝於主板5上。外部凸 塊61連接至設置於主板5中之襯墊。當半導體儲存裝置7安裝於主板5上時，外部凸塊61經由圖1之佈線9連接至處理器6。另外，電力供應凸塊62連接至電子機器1之電力供應電路。
基板41可包括複數個其他凸塊。凸塊包括例如連接至接地襯墊之凸塊或與電路分離來固定半導體儲存裝置7之凸塊。
記憶體晶片12堆疊於記憶體控制器15之上表面15b上。記憶體12可經由黏合層12a接合至另一記憶體12或記憶體控制器15之上表面15b。記憶體控制器15嵌入於黏合層12a中。
導線13將一個記憶體12與另一記憶體12彼此連接，且將記憶體12與設置於基板41之上表面41b上之第二連接端子54彼此連接。因此，導線13將記憶體晶片12與第二連接端子54彼此電性連接。
記憶體控制器15之第二輸入/輸出端子17經由連接凸塊46、第一連接端子53、連接佈線55、第二連接端子54及導線13電性連接至記憶體晶片12。因此，記憶體控制器15向記憶體晶片12傳輸信號及自記憶體晶片12接收信號，且可控制記憶體晶片12。
密封樹脂14密封並覆蓋基板41之上表面41b、記憶體控制器15、記憶體晶片12及導線13。基板41之上表面41b、記憶體控制器15、記憶體晶片12及導線13嵌入於密封樹脂14中。
現參考圖7，外部凸塊61之直徑D4小於或等於外部凸塊61電性連接至之第一輸入/輸出端子16之直徑D2。因此，外部凸塊61之橫截面積小於或等於外部凸塊61電性連接至之第一輸入/輸出端子16之橫截面積。直徑D4係外部凸塊61之垂直於Z軸之負方向之方向上的寬度。
外部凸塊61之直徑D4小於或等於外部凸塊61連接至之連接 導體52之直徑D5。因此，外部凸塊61之橫截面積小於或等於外部凸塊61連接至之連接導體52之橫截面積。
在該實施例中，連接導體52之第一襯墊52a、第二襯墊52b與通孔52c中之每一者具有相同直徑D5。但是，第一襯墊52a、第二襯墊52b與通孔52c可具有不同直徑。在此狀況下，直徑D5係第一襯墊52a、第二襯墊52b及通孔52c之直徑當中之最大直徑。
如上文所描述，連接導體52及外部凸塊61之大小及間距與第一輸入/輸出端子16之大小及間距實質上匹配。但是，外部凸塊61可在與Z軸之負方向相交之方向上比第一輸入/輸出端子16間隔開更大地間隔開，只要其設置於凸塊在Z軸之負方向上處於記憶體控制器15正下方之位置處即可。
外部凸塊61之直徑D4小於或等於圖4之通孔9c之直徑D3。另外，外部凸塊61之直徑D4小於或等於佈線9之第一部分9a及第二部分9b中之每一者之寬度W。
在根據上文所描述之第三實施例之電子機器1中，外部凸塊61在外部凸塊61在Z軸之負方向上處於記憶體控制器15正下方之位置處自基板41之下表面41a突出。連接導體52在Z軸之負方向上設置於連接導體52處於記憶體控制器15正下方之位置處，且將控制器凸塊45與外部凸塊61彼此連接。因此，控制器凸塊45與外部凸塊61之間的電路徑比外部凸塊61及連接導體52在與Z軸之負方向相交之方向上與記憶體控制器15間隔開時更短。另外，外部凸塊61容納於外部凸塊61在Z軸之負方向上處於記憶體控制器15正下方之位置處，使得外部凸塊61之大小受到限制。因此，外部凸塊61之大小被設定成比至少一個外部凸塊61在與Z軸之負方向 相交之方向上與記憶體控制器15間隔開時更小。因此，在第一輸入/輸出端子16與外部凸塊61之間的電路徑中，避免了由寄生電容增大引起之阻抗減小，且避免了由阻抗失配引起之半導體儲存裝置7之信號品質退化。
藉由覆晶安裝，記憶體控制器15經由控制器凸塊45、連接凸塊46及電力供應凸塊47安裝於基板41上。因此，接合線或DAF並非必需的，且可使半導體儲存裝置7變薄。
外部凸塊61定位於外部凸塊61在Z軸之負方向上處於外部凸塊61電性連接至之第一輸入/輸出端子16正下方之位置處。因此，減少外部凸塊61與第一輸入/輸出端子16之間的電路徑，且電路徑之設計係簡單的。
外部凸塊61垂直於Z軸之負方向之橫截面積小於或等於第一輸入/輸出端子16之橫截面積。因此，在第一輸入/輸出端子16與外部凸塊61之間的電路徑中，避免了由外部凸塊61之寄生電容增大引起之阻抗減小。因此，避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
外部凸塊61之垂直於Z軸之負方向之橫截面積小於或等於連接導體52之垂直於Z軸之負方向之橫截面積。因此，在第一輸入/輸出端子16與外部凸塊61之間的電路徑中，避免了由外部凸塊61之寄生電容增大引起之阻抗減小。因此，避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
外部凸塊61之垂直於Z軸之負方向之方向上的直徑D4小於或等於佈線9之寬度W。因此，在第一輸入/輸出端子16與處理器6之間的電路徑中，避免了由外部凸塊61之寄生電容增大引起之阻抗減小。因此， 避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
外部凸塊61之垂直於Z軸之負方向之方向上的直徑D4小於或等於通孔9c之直徑D3。因此，在第一輸入/輸出端子16與處理器6之間的電路徑中，避免了由外部凸塊61之寄生電容增大引起之阻抗減小。因此，避免了半導體儲存裝置7之由阻抗失配引起之信號品質退化。
根據上述實施例中之至少一者，凸塊在第一方向上在凸塊處於記憶體控制器正下方之位置處自第一表面突出，且電性連接至第一輸入/輸出端子。因此，凸塊與第一輸入/輸出端子之間的電路徑比凸塊在與第一方向相交之方向上與記憶體控制器間隔開時更短。舉例而言，凸塊直接連接至第一輸入/輸出端子。另外，凸塊容納於凸塊在第一方向上處於記憶體控制器正下方之位置處，使得凸塊之大小受到限制。因此，凸塊之大小被設定成比至少一個凸塊在與同一第一方向相交之方向上與記憶體控制器間隔開時更小。因此，在第一輸入/輸出端子與凸塊之間的電路徑中，避免了由寄生電容增大引起之阻抗減小，且避免了由阻抗失配引起之半導體儲存裝置之信號品質退化。
另外，第一實施例之圖1及圖4中所描述之解釋亦適用於第二及第三實施例。
雖然已描述某些實施例，但此等實施例僅作為實例而呈現，且其並不意欲限制本發明之範疇。實際上，本文中所描述之新穎實施例可以多種其他形式體現；此外，可在不脫離本發明之精神之情況下進行本文中所描述之實施例之形式之各種省略、取代及改變。所附申請專利範圍及其等效物希望涵蓋將屬於本發明之範疇及精神之此類形式或修改。
1:電子機器
5:主板
7:半導體儲存裝置
8:底填充料
9a:第一部分
9b:第二部分
9c:通孔
11:第一封裝
11a:下表面
11b:上表面
12:記憶體晶片
12a:黏合層
13:導線
14:密封樹脂
15:記憶體控制器
15a:下表面
15b:上表面
15c:側表面
16:第一輸入/輸出端子
17:第二輸入/輸出端子
18:電力供應端子
21:封裝層
21a:下表面
21b:上表面
22:第一絕緣層
23:第一佈線層
23a:襯墊
23b:連接佈線
23c:電力供應佈線
24:第二絕緣層
25:第二佈線層
25a:連接端子
25b:連接佈線
26:第三絕緣層
27:通孔
28:凸塊
29:電力供應凸塊
31:導電層

Claims (20)

  1. 一種電子機器，其包含：一第一封裝，其包括：一第一表面，其面朝一第一方向；一第二表面，其與該第一表面相對；一第一半導體晶片，其設置於該第一表面與該第二表面之間；複數個第一端子，其設置於該第一半導體晶片上且面朝該第一方向；一第二端子，其設置於該第一半導體晶片上且面朝該第一方向；一電力供應端子；一第一層間連接導體，其在與該第一方向相交之一第二方向上與該第一半導體晶片間隔開；一第一連接導體，其將該第二端子與該第一層間連接導體彼此連接；一第二連接導體，其至少一部分設置於該第二表面上且其連接至該第一層間連接導體；複數個第一凸塊，其電性連接至該複數個第一端子且在該第一方向上處於該第一半導體晶片正下方(directly below)之位置處自該第一表面突出；及一電力供應凸塊，其電性連接至該電力供應端子，其中在該等第一凸塊與在該第一方向上不處於該第一半導體晶片正下方之該電力供應凸塊之間不存在凸塊；一第二半導體晶片，其設置於該第二表面上；一導線，其將該第二半導體晶片與該第二連接導體彼此電性連接；及一第二封裝，其包括覆蓋該第二表面、該第二半導體晶片及該導線之一塗層樹脂。
  2. 如請求項1之電子機器，其中該等第一凸塊中之每一者設置於該第一凸塊在該第一方向上處 電性連接於該第一凸塊電性連接至之該第一端子正下方之一位置處。
  3. 如請求項1之電子機器，其中該複數個第一凸塊直接連接至該複數個第一端子。
  4. 如請求項3之電子機器，其中該等第一端子中之每一者包括一襯墊及在該襯墊與該對應第一凸塊之間的一障壁金屬。
  5. 如請求項1之電子機器，其中該等第一凸塊中之每一者的沿著垂直於該第一方向之一平面取得之一橫截面之一最大面積小於或等於該第一凸塊電性連接至之該第一端子的沿著垂直於該第一方向之一平面取得之一橫截面之一最大面積。
  6. 如請求項1之電子機器，其中該第一封裝包括一模製樹脂，其覆蓋該第一半導體晶片，及一絕緣層，其形成於該第一半導體晶片之面朝該第一方向之一表面上。
  7. 如請求項1之電子機器，其進一步包含：一第三半導體晶片，其控制該第一半導體晶片；及一基板，其包括連接至該複數個第一凸塊及該第三半導體晶片之複數個佈線， 其中該第一凸塊在該第二方向上之一最大寬度小於或等於該佈線之一寬度。
  8. 如請求項1之電子機器，其進一步包含：一第三半導體晶片，其控制該第一半導體晶片；及一基板，其包括：複數個層；複數個佈線，其設置於該等層中且將該複數個第一凸塊與該第三半導體晶片彼此連接；及一第二層間連接導體，其將該佈線之設置於該等層中之一者中之一部分與該佈線之設置於該等層中之另一者中之一部分彼此連接，其中該第一凸塊在該第二方向上之一最大寬度小於或等於該第二層間連接導體在該第二方向上之一最大寬度。
  9. 如請求項1之電子機器，其中該第一半導體晶片係一記憶體控制器，該第二半導體晶片係一記憶體晶片，且進一步包含：複數個額外記憶體晶片，其堆疊於該第二半導體晶片上。
  10. 如請求項1之電子機器，其中該複數個第一端子係向該第一封裝及該第二封裝外部之一裝置傳輸一信號及自該裝置接收一信號之輸入/輸出端子，該第二端子係向該第二半導體晶片傳輸一信號及自該第二半導體晶片接收一信號之一輸入/輸出端子。
  11. 一種電子機器，其包含：一第一半導體晶片，其包括：複數個第一端子，其面朝一第一方向；一第二端子，其面朝該第一方向；一電力供應端子，其面朝該第一方向；及複數個第一凸塊，其連接至該複數個第一端子；一第一基板，其包括：一第一端子表面，其面朝該第一方向；一第二端子表面，其與該第一端子表面相對且面朝該第一半導體晶片；複數個外部凸塊，其自該第一端子表面突出，且包括在該第一方向上處於該第一半導體晶片正下方之位置處之第二凸塊及電性連接至該電力供應端子之一電力供應凸塊，其中在該等第二凸塊與在該第一方向上不處於該第一半導體晶片正下方之該電力供應凸塊之間不存在外部凸塊；複數個連接導體，其設置於該等連接導體在該第一方向上處於該第一半導體晶片正下方之位置處，且將該複數個第一凸塊與該複數個外部凸塊彼此連接；一第一連接端子，其設置於該第二端子表面上且電性連接至該第二端子；一第二連接端子，其設置於該第二端子表面上；及一連接佈線，其將該第一連接端子與該第二連接端子彼此連接；一第二半導體晶片，其設置於該第一半導體晶片上；一導線，其將該第二半導體晶片與該第二連接端子彼此電性連接；及一塗層樹脂，其覆蓋該第二端子表面、該第一半導體晶片及該第二半導體晶片。
  12. 如請求項11之電子機器，其中該等第二凸塊中之每一者設置於該第二凸塊在該第一方向上處 於該第二凸塊電性連接至之該第一端子正下方之一位置處。
  13. 如請求項11之電子機器，其中該等第二凸塊中之每一者的沿著垂直於該第一方向之一平面取得之一橫截面之一最大面積小於或等於該第二凸塊電性連接至之該第一端子的沿著垂直於該第一方向之一平面取得之一橫截面之一最大面積。
  14. 如請求項11之電子機器，其中該等第二凸塊中之每一者的沿著垂直於該第一方向之一平面取得之一橫截面之一最大面積小於或等於該第二凸塊電性連接至之該連接導體的沿著垂直於該第一方向之一平面取得之一橫截面之一最大面積。
  15. 如請求項11之電子機器，其中該第一半導體晶片係一記憶體控制器，該第二半導體晶片係一記憶體晶片，且進一步包含：複數個額外記憶體晶片，其堆疊於該第二半導體晶片上。
  16. 如請求項11之電子機器，其中該複數個第一端子係向該第一半導體晶片及該第二半導體晶片外部之一裝置傳輸一信號及自該裝置接收一信號之輸入/輸出端子，該第二端子係向該第二半導體晶片傳輸一信號及自該第二半導體晶片接收一信號之一輸入/輸出端子。
  17. 如請求項11之電子機器，其進一步包含：一第三半導體晶片，其控制該第一半導體晶片；及一基板，其包括連接至該複數個第二凸塊及該第三半導體晶片之複數個佈線，其中該第二凸塊在該第二方向上之一最大寬度小於或等於該佈線之一寬度。
  18. 如請求項11之電子機器，其進一步包含：一第三半導體晶片，其控制該第一半導體晶片；及一基板，其包括：複數個層；複數個佈線，其設置於該等層中且將該複數個第二凸塊與該第三半導體晶片彼此連接；及一第二層間連接導體，其將該佈線之設置於該等層中之一者中之一部分與該佈線之設置於該等層中之另一者中之一部分彼此連接，其中該第二凸塊在該第二方向上之一最大寬度小於或等於該第二層間連接導體在該第二方向上之一最大寬度。
  19. 一種電子機器，其包含：一第一封裝，其包括：一第一表面，其面朝一第一方向；一第二表面，其與該第一表面相對；一第一半導體晶片，其設置於該第一表面與該第二表面之間；複數個第一輸入/輸出端子，其設置於該第一半導體晶片上且面朝該第一方向；一第二輸入/輸出端子，其設置於該第一半導體晶片上且面朝該第一方向；一電力供應端子；一第一層間連接導體，其在與該第一方向相交之一第二方向上與該第一半導體晶片間隔開；一第一連接 導體，其將該第二輸入/輸出端子與該第一層間連接導體彼此連接；一第二連接導體，其至少一部分設置於該第二表面上且其連接至該第一層間連接導體；複數個第一凸塊，其電性連接至該複數個第一輸入/輸出端子且在該第一方向上處於該第一半導體晶片正下方之位置處自該第一表面突出；及一電力供應凸塊，其電性連接至該電力供應端子，其中在該等第一凸塊與在該第一方向上不處於該第一半導體晶片正下方之該電力供應凸塊之間不存在凸塊，一模製樹脂，其囊封該第一半導體晶片，及形成於該第一半導體晶片之面朝該第一方向之一表面上的一絕緣層；複數個第二半導體晶片，其堆疊於該第二表面上；一導線，其將該複數個第二半導體晶片與該第二連接導體彼此電性連接；一第二封裝，其包括覆蓋該第二表面、該第二半導體晶片及該導線之一塗層樹脂；一第三半導體晶片，其控制該第一半導體晶片；及一基板，其包括連接至該複數個第一凸塊及該第三半導體晶片之複數個佈線，其中該第一凸塊在該第二方向上之一最大寬度小於或等於該等佈線之一最大寬度。
  20. 如請求項17之電子機器，其中該基板包括：複數個層；複數個佈線，其設置於該等層中；及一第二層間連接導體，其將該佈線之設置於該等層中之一者中之一部分與該佈 線之設置於該等層中之另一者中之一部分彼此連接，該第一半導體晶片係一記憶體控制器，該第二半導體晶片係一記憶體晶片，該第三半導體晶片係一處理器，該記憶體控制器與該處理器經由該等第一輸入/輸出端子彼此通信，且該記憶體控制器與該記憶體晶片經由該第二輸入/輸出端子彼此通信。
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