CN110911380B - 电子设备 - Google Patents
电子设备 Download PDFInfo
- Publication number
- CN110911380B CN110911380B CN201910170127.0A CN201910170127A CN110911380B CN 110911380 B CN110911380 B CN 110911380B CN 201910170127 A CN201910170127 A CN 201910170127A CN 110911380 B CN110911380 B CN 110911380B
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- Prior art keywords
- semiconductor chip
- input
- bump
- bumps
- output terminal
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- 239000004065 semiconductor Substances 0.000 claims abstract description 158
- 239000004020 conductor Substances 0.000 claims abstract description 93
- 229920005989 resin Polymers 0.000 claims abstract description 27
- 239000011347 resin Substances 0.000 claims abstract description 27
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 83
- 239000000758 substrate Substances 0.000 claims description 33
- 239000011229 interlayer Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 14
- 230000015556 catabolic process Effects 0.000 description 13
- 238000006731 degradation reaction Methods 0.000 description 13
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- 230000003071 parasitic effect Effects 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000003860 storage Methods 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229920003002 synthetic resin Polymers 0.000 description 5
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/114—Pad being close to via, but not surrounding the via
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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Abstract
一种电子设备包含第一封装和第二封装。所述第一封装包含:所述第一封装的相对第一表面与第二表面之间的第一半导体芯片;所述第一半导体芯片上的面朝垂直于所述第一表面和所述第二表面的第一方向的多个端子,所述端子包含第一输入/输出端子和第二输入/输出端子;以及在所述第一方向上处于所述第一半导体芯片正下方的位置处电连接到所述多个第一输入/输出端子的多个凸块。所述第二封装包含:设置于所述第一封装的所述第二表面上的第二半导体芯片;将所述第二半导体芯片电连接到被电连接到所述第二输入/输出端子的导体的导线;以及覆盖所述第一封装的所述第二表面、所述第二半导体芯片和所述导线的涂层树脂。
Description
相关申请的交叉引用
本申请是基于并要求来自2018年9月14日提交的日本专利申请第2018-173030号的优先权,所述申请的全部内容被以引用的方式并入本文中。
技术领域
本文中所描述的实施例大体上涉及一种电子设备。
背景技术
已知控制器芯片和多个存储器芯片堆叠于衬底上的半导体存储装置。半导体存储装置封装为例如球状栅格阵列(ball grid array,BGA),其中多个焊球设置于衬底的底表面上。
控制器芯片通过焊球向处理器发射信号并从处理器接收信号。当处理器与控制器芯片之间的电路径中存在阻抗误配时,信号质量会退化。
发明内容
本文中所描述的实施例提供一种改良型电子设备。
一实施例提供,
一种电子设备,其包括:
第一封装,其包含面朝第一方向的第一表面、与所述第一表面相对的第二表面、设置于所述第一表面与所述第二表面之间的第一半导体芯片、设置于所述第一半导体芯片上且面朝所述第一方向的多个第一端子、设置于所述第一半导体芯片上且面朝所述第一方向的第二端子、电源端子、在与所述第一方向相交的第二方向上与所述第一半导体芯片间隔开的第一层间连接导体、将所述第二端子与所述第一层间连接导体彼此连接的第一连接导体、其至少一部分设置于所述第二表面上且连接到所述第一层间连接导体的第二连接导体、电连接到所述多个第一端子并在所述第一方向上处于所述第一半导体芯片正下方的位置处从所述第一表面突出的多个第一凸块,以及电连接到所述电源端子的电源凸块,其中在所述第一凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的凸块;
第二半导体芯片,其设置于所述第二表面上;
导线,其将所述第二半导体芯片与所述第二连接导体彼此电连接;以及
第二封装,其包含覆盖所述第二表面、所述第二半导体芯片和所述导线的涂层树脂。
一实施例提供,
一种电子设备,其包括:
第一半导体芯片,其包含面朝第一方向的多个第一端子、面朝所述第一方向的第二端子、面朝所述第一方向的电源端子,以及连接到所述多个第一端子的多个第一凸块;
第一衬底,其包含面朝所述第一方向的第一端子表面;与所述第一端子表面相对并面朝所述第一半导体芯片的第二端子表面;多个外部凸块,所述多个外部凸块自所述第一端子表面突出并包含在所述第一方向上处于所述第一半导体芯片正下方的位置处的第二凸块和电连接到所述电源端子的电源凸块,其中在所述第二凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的外部凸块;多个连接导体,所述多个连接导体设置于所述连接导体在所述第一方向上处于所述第一半导体芯片正下方的位置处,并将所述多个第一凸块与所述多个外部凸块彼此连接;设置于所述第二端子表面上并电连接到所述第二端子的第一连接端子;设置于所述第二端子表面上的第二连接端子;以及将所述第一连接端子与所述第二连接端子彼此连接的连接布线;
第二半导体芯片,其设置于所述第一半导体芯片上;
导线,其将所述第二半导体芯片与所述第二连接端子彼此电连接;以及
涂层树脂,其覆盖所述第二端子表面、所述第一半导体芯片和所述第二半导体芯片。
另外,一实施例提供,
一种电子设备,其包括:
第一封装,其包含面朝第一方向的第一表面、与所述第一表面相对的第二表面、设置于所述第一表面与所述第二表面之间的第一半导体芯片、设置于所述第一半导体芯片上且面朝所述第一方向的多个第一输入/输出端子、设置于所述第一半导体芯片上且面朝所述第一方向的第二输入/输出端子、电源端子、在与所述第一方向相交的第二方向上与所述第一半导体芯片间隔开的第一层间连接导体、将所述第二输入/输出端子与所述第一层间连接导体彼此连接的第一连接导体、其至少一部分设置于所述第二表面上且连接到所述第一层间连接导体的第二连接导体、电连接到所述多个第一输入/输出端子并在所述第一方向上处于所述第一半导体芯片正下方的位置处从所述第一表面突出的多个第一凸块,以及电连接到所述电源端子的电源凸块,其中在所述第一凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的凸块,
模制树脂,其囊封所述第一半导体芯片,以及形成于所述第一半导体芯片的面朝所述第一方向的表面上的绝缘层;
多个第二半导体芯片,其堆叠于所述第二表面上;
导线,其将所述多个第二半导体芯片与所述第二连接导体彼此电连接;
第二封装,其包含覆盖所述第二表面、所述第二半导体芯片和所述导线的涂层树脂;
第三半导体芯片,其控制所述第一半导体芯片;以及
衬底,其包含连接到所述多个第一凸块和所述第三半导体芯片的多个布线,
其中所述第二方向上的所述第一凸块的最大宽度小于或等于所述布线的最大宽度。
附图说明
图1是示意性地说明根据第一实施例的电子设备的平面图。
图2是示意性地说明根据第一实施例的半导体存储装置的横截面图。
图3是示意性地说明根据第一实施例的半导体存储装置的一部分的横截面图。
图4是示意性地说明第一实施例中的布线和凸块的透视图。
图5是示意性地说明根据第二实施例的半导体存储装置的一部分的横截面图。
图6是示意性地说明根据第三实施例的半导体存储装置的横截面图。
图7是示意性地说明根据第三实施例的半导体存储装置的一部分的横截面图。
具体实施方式
总的来说,根据一个实施例,一种电子设备,具体地说,一种半导体存储装置,包含包含第一半导体芯片的第一封装和包含第二半导体芯片的第二封装。所述第一封装包含相对的第一表面与第二表面、设置于所述第一表面与所述第二表面之间的第一半导体芯片、设置于所述第一半导体芯片上且面朝所述第一方向的多个第一端子、设置于所述第一半导体芯片上且面朝所述第一方向的第二端子、电源端子、在与所述第一方向相交的第二方向上与所述第一半导体芯片间隔开的第一层间连接导体、将所述第二端子与所述第一层间连接导体彼此连接的第一连接导体、其至少一部分设置于所述第二表面上且连接到所述第一层间连接导体的第二连接导体、电连接到所述多个第一端子并在所述第一方向上处于所述第一半导体芯片正下方的位置处从所述第一表面突出的多个第一凸块,以及电连接到所述电源端子的电源凸块,其中在所述第一凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的凸块。所述第二封装包含涂层树脂,所述涂层树脂覆盖所述第二表面、设置于所述第二表面上的所述第二半导体芯片,以及将所述第二半导体芯片与所述第二连接导体彼此电连接的导线。
第一实施例
在下文中,将参考图1到4描述第一实施例。在本公开中,可使用两个或更多个不同表达来描述根据实施例的相同组件和其描述。组件和其描述不限于本公开的表达。可使用不同于在本公开中使用的名称的名称来指定组件。另外,可使用不同于在本公开中使用的表达的表达来描述组件。
图1是示意性地说明根据第一实施例的电子设备1的平面图。所述实施例的电子设备1的一个实例是智能电话。电子设备1还可以是例如个人计算机、便携式计算机、平板电脑、其它类型的移动电话、电视接收机、USB闪存驱动器、SD卡、嵌入式多媒体卡(embeddedMulti Media Card,)、存储卡、其它存储装置、可佩戴式装置、智能扬声器、家庭电气设备或其它装置。
如图1中所说明,电子设备1包含主板5、处理器6、半导体存储装置7和底填充料8。主板5是衬底的实例。子板是衬底的另一实例。处理器6是控制器的实例。电子设备1可进一步包含例如外壳或显示装置等其它组件。
主板5是例如印刷电路板(printed circuit board,PCB)。主板5包含多个布线9。布线9将处理器6与半导体存储装置7彼此电连接。
处理器6和半导体存储装置7安装于主板5上。处理器6是例如芯片上系统(system-on-a-chip,SoC)处理器6还可以是集成电路(integrated circuit,IC)或电路。处理器6控制包含半导体存储装置7的电子设备1。
图2是示意性地说明根据第一实施例的半导体存储装置7的横截面图。所述实施例的半导体存储装置7的一个实例是固态驱动器(solid state drive,SSD),更一般来说半导体封装。半导体存储装置7可以是另一装置例如eMMC或通用快闪存储装置(UniversalFlash Storage,UFS)。
在本公开中,X轴、Y轴和Z轴如图式中的每一个中所说明而定义。X轴、Y轴与Z轴彼此垂直。X轴被定义为沿着半导体存储装置7的宽度方向。Y轴被定义为沿着半导体存储装置7的长度(或深度)方向。Z轴被定义为沿着半导体存储装置7的高度(或厚度)方向。
半导体存储装置7包含第一封装11,以及包含多个存储器芯片12、多个导线13和密封树脂14的第二封装。密封树脂14是涂层树脂的实例。在第一实施例中,存储器控制器15设置于第一封装11中。
另外,半导体存储装置7可进一步包含例如电源电路等其它组件。半导体存储装置7的电源电路从供应自电子设备1的电源电路的外部直流电力产生多个不同内部直流电力供应电压。电源电路向半导体存储装置7中的相应电路供应内部直流电力供应电压。电源电路检测外部电力的升高,产生上电复位信号,并向存储器控制器15供应所述上电复位信号。
第一封装11是具有扇出封装(fan out package,FOP)或扇出晶片级封装(fan outwafer level package,FOWLP)的结构的半导体封装。第一封装11不限于此实例。
第一封装11包含下表面11a和上表面11b。为了易于理解,本公开中的表达“上”和“下”将基于图式中的每一个的上下方向而使用,并且不限制组件中的每一个的位置和方向。
下表面11a是面朝Z轴的负方向(与Z轴的箭头相对的方向)的大体上平坦的表面。上表面11b是与下表面11a相对的大体上平坦的表面,并面朝Z轴的正方向(由Z轴的箭头指示的方向)。
第一封装11包含存储器控制器15并覆盖存储器控制器15。因此,存储器控制器15定位于第一封装11的下表面11a与上表面11b之间。存储器控制器15可形成第一封装11的下表面11a上表面11b的至少一部分。换句话说,存储器控制器15可从下表面11a和上表面11b的至少一部分暴露。
存储器控制器15控制例如在存储器芯片12中存储数据和从存储器芯片12读取数据。存储器控制器15不仅可控制存储器12,而且可控制半导体存储装置7中的其它电子组件。
存储器控制器15通过连接接口(I/F)电连接到处理器6。连接接口遵守例如UFS或PCI高速(外围组件互连高速,Peripheral Component Interconnect Express,PCIe)等标准。
存储器控制器15包含下表面15a、上表面15b和侧表面15c。下表面15a是面朝Z轴的负方向的大体上平坦的表面。上表面15b是与下表面15a相对的定位并面朝Z轴的正方向的大体上平坦的表面。侧表面15c定位于下表面15a的边缘与上表面15b的边缘之间,并面朝X轴方向和Y轴方向。
存储器控制器15进一步包含多个第一输入/输出端子16、第二输入/输出端子17和电源端子18。第一输入/输出端子16、第二输入/输出端子17和电源端子18中的每一个形成为圆形形状,但可形成为例如四边形形状等另一形状。
第一输入/输出端子16、第二输入/输出端子17和电源端子18设置于下表面15a上并面朝Z轴的负方向。第一输入/输出端子16、第二输入/输出端子17和电源端子18以例如晶格(矩阵)形状布置。
第一输入/输出端子16设置于连接接口中,并且是例如存储器控制器15的用于发射和接收差分信号的端子。替代地,第一输入/输出端子16可以是用于发射和接收另一信号的端子。当存储器控制器15向处理器6发射数据和从其接收数据时,使用第一输入/输出端子16。
当存储器控制器15向存储器12发射数据和从其接收数据时,使用第二输入/输出端子17。电源端子18电连接到电子设备1的电源电路。存储器控制器15通过电源端子18从电子设备1的电源电路供应外部直流电力。
存储器控制器15可包含多个其它端子,所述端子包含例如连接到接地的端子或与电路分离来固定存储器控制器15的垫。
第一封装11进一步包含封装层21、第一绝缘层22、第一布线层23、第二绝缘层24、第二布线层25、第三绝缘层26、通孔27、多个凸块28和电源凸块29。通孔27是层间连接导体的实例。
封装层21由例如包含例如环氧树脂等合成树脂作为模制树脂等和由无机材料形成的填充剂的材料形成,并具有绝缘性质。封装层21覆盖存储器控制器15的上表面15b和侧表面15c。因此,封装层21的一部分相对于存储器控制器15定位于与Z轴的负方向相交的方向上。
封装层21包含下表面21a和上表面21b。下表面21a是面朝Z轴的负方向的大体上平坦的表面。下表面21a与存储器控制器15的下表面15a大体上连续。上表面21b是面朝Z轴的正方向的大体上平坦的表面。上表面21b在Z轴的正方向上与存储器控制器15的上表面15b间隔开。
第一绝缘层22由例如合成树脂形成并具有绝缘性质。第一绝缘层22可包含无机填充剂以便调整其弹性模数和热膨胀系数。第一绝缘层22覆盖存储器控制器15的下表面15a和封装层21的下表面21a。在第一绝缘层22中,设置多个开口,第一输入/输出端子16、第二输入/输出端子17和电源端子18从所述开口暴露。
第一布线层23由例如铜等导体形成且设置于第一绝缘层22上。第一布线层23包含多个垫23a、连接布线23b和电源布线23c。连接布线23b是连接导体的实例。
图3是示意性地说明根据第一实施例的半导体存储装置7的一部分的横截面图。如图3中所说明,垫23a中的每一个处于对应第一输入/输出端子16正下方,并连接到第一输入/输出端子16。
垫23a的横截面积大体上等于第一输入/输出端子16的横截面积。在本公开中,除非另外规定,否则横截面积指代垂直于Z轴的负方向的横截面积。
连接布线23b的一个末端部分连接到第二输入/输出端子17。在第二输入/输出端子17与在与Z轴的负方向相交的方向上与存储器控制器15间隔开的位置之间,连接布线23b沿着第一封装11的下表面11a延伸。
如图2中所说明,连接布线23c的一个末端部分连接到电源端子18。在电源端子18与在与Z轴的负方向相交的方向上与存储器控制器15间隔开的位置之间,连接布线23c沿着第一封装11的下表面11a延伸。
第二绝缘层24是例如防焊剂,并设置于第一绝缘层22和第一布线层23上。第二绝缘层24形成第一封装11的下表面11a。在第二绝缘层24中,设置多个开口,垫23a和电源布线23c的另一末端部分从所述开口暴露。因此,垫23a和电源布线23c的另一末端部分设置于第一封装11的下表面11a上。
第二布线层25由例如铜等导体形成,并设置于封装层21的上表面21b上。第二布线层25包含连接端子25a和连接布线25b。连接端子25a和连接布线25b各自是连接导体的实例。第二布线层25可包含另一布线。
连接布线25b连接到连接端子25a。在连接端子25a与在与Z轴的负方向相交的方向上与存储器控制器15间隔开的位置之间,连接布线25b沿着第一封装11的上表面11b延伸。
第三绝缘层26是例如防焊剂,并设置于封装层21的上表面21b和第二布线层25上。第三绝缘层26形成第一封装11的上表面11b。在第三绝缘层26中,设置开口,连接端子25a从所述开口暴露。因此,连接端子25a设置于第一封装11的上表面11b上。
多个通孔27设置于封装层21中并在Z轴方向上穿透封装层21。通孔27包含通过封装层21的孔和设置于孔中或孔的内部表面上的导体。通过例如激光束加工或镀敷,孔设置于由合成树脂形成的封装层21中。
通孔27在与Z轴的负方向相交的方向上与存储器控制器15间隔开,并将第一布线层23的连接布线23b与第二布线层25的连接布线25b彼此。因此,第一布线层23的连接布线23b将第二输入/输出端子17与通孔27彼此连接。另外,第二布线层25的连接布线25b连接到通孔27以便将通孔27与连接端子25a彼此连接。替代地,在未提供连接布线25b的情况下,通孔27可将第一布线层23的连接布线23b与连接端子25a彼此连接。
如图3中所说明,凸块28是例如半球面焊料凸块。凸块28可形成为另一形状。当连接到垫23a时,凸块28通过垫23a电连接到第一输入/输出端子16。
垫23a和凸块28定位于垫23a和凸块28在Z轴的负方向上处于垫23a和凸块28电连接到的第一输入/输出端子16正下方的位置处。因此,垫23a和凸块28设置于垫23a和凸块28在Z轴的负方向上处于存储器控制器15正下方的位置处。凸块28在Z轴的负方向上从设置于第一封装11的下表面11a上的垫23a突出。
如图2中所说明,电源凸块29是例如半球面焊料凸块。电源凸块29可形成为另一形状。在与Z轴的负方向相交的方向上与存储器控制器15间隔开的位置处,电源凸块29连接到电源布线23c的末端部分。因此,电源布线23c将电源端子18与电源凸块29彼此连接。电源凸块29在Z轴的负方向上从电源布线23c的设置于第一封装11的下表面11a上的末端部分突出。
通过倒装芯片安装,半导体存储装置7安装于主板5上。凸块28和电源凸块29连接到设置于主板5上的垫。当半导体存储装置7安装于主板5上时,凸块28通过图1的布线9连接到处理器6。另外,电源凸块29连接到电子设备1的电源电路。
第一封装11可包含多个其它凸块。凸块包含例如连接到接地垫的凸块或与电路分离来固定半导体存储装置7的凸块。
第一封装11可进一步包含由图2中的两点划线指示的导电层31。导电层31是例如金属板。导电层31设置于封装层21中并定位于封装层21的上表面21b与存储器控制器15的上表面15b之间。
导电层31在Z轴的负方向上与存储器控制器15重叠。因此,导电层31阻挡从存储器控制器15和外部源产生的电磁噪声。另外,导电层31用于存储器控制器15的热耗散。
存储器12是例如NAND快闪存储器并存储信息。存储器12可以是例如NOR快闪存储器等另一存储器。存储器芯片12堆叠于第一封装11的上表面11b上。
在存储器芯片12中的每一个的下表面上,设置有粘合层12a。粘合层12a是裸片膜(die attach film,DAF),并由包含丙烯酸聚合物和环氧树脂的材料例如形成。管芯附接膜将还被称作裸片接合膜。粘合层12a可含有粘合材料。存储器12可通过粘合层12a接合到另一存储器12或第一封装11的上表面11b。
导线13是例如接合线。导线13将一个存储器12与另一存储器12彼此连接,或将存储器12与设置于第一封装11的上表面11b上的连接端子25a彼此连接。因此,导线13将存储器芯片12与连接端子25a彼此电连接。
存储器控制器15的第二输入/输出端子17通过连接布线23b、通孔27、连接布线25b、连接端子25a和导线13电连接到存储器芯片12。因此,存储器控制器15向存储器芯片12发射信号并从其接收信号,并可控制存储器芯片12。
密封树脂14是例如模制树脂,并由包含其中混合例如二氧化硅等无机材料的环氧树脂的合成树脂形成。密封树脂14可由包含另一种合成树脂的材料形成。密封树脂14的材料和封装层21的材料都包含环氧树脂。因此,密封树脂14的热膨胀系数与封装层21东风恶热膨胀系数彼此类似。
密封树脂14密封并覆盖第一封装11的上表面11b、存储器芯片12和导线13。第一封装11的上表面11b、存储器芯片12和导线13嵌入于密封树脂14中。换句话说,第一封装11的上表面11b、存储器芯片12和导线13容纳于密封树脂14中并存在于密封树脂14中。
图3中所说明的凸块28的直径D1小于或等于凸块28电连接到的第一输入/输出端子16的直径D2,其中直径D1是凸块28的垂直于Z轴的负方向的方向上的宽度。因此,凸块28的横截面积小于或等于凸块28电连接到的第一输入/输出端子16的横截面积。
图4是示意性地说明第一实施例中的布线9和凸块28的透视图。图4中所说明的主板5是多层板并包含多个层5a和5b。层5a和5b可以是设置于主板5的表面上的层,或可以是设置于主板5中的层。
布线9包含第一部分9a、第二部分9b和通孔9c。通孔9c是层间连接导体的实例。第一部分9a是设置于层5a中的布线图案。第二部分9b是设置于层5b中的布线图案。通孔9c在层5a与层5b之间穿透主板5,并将第一部分9a与第二部分9b彼此连接。在一些实施例中,布线9可设置于单层中使得不提供通孔9c。
凸块28的直径D1小于或等于通孔9c的直径D3。直径D3是通孔9c的宽度。另外,凸块28的直径D1小于或等于布线9的第一部分9a的宽度W。除了通孔9c以外,布线9的宽度基本恒定。因此,凸块28的直径D1还小于或等于布线9的第二部分9b的宽度。
如由图2中的两个点划线指示,底填充料8填充于通过倒装芯片安装来安装的半导体存储装置7与主板5之间。底填充料8防止对凸块28与电源凸块29之间的连接部分和主板5的垫的损坏。
在处理器6与存储器控制器15之间的电路径中,大寄生电容可产生于比其它部分具有更大横截面积的部分(下文被称作“延伸部分”)中。在延伸部分中,阻抗减小。阻抗减小的量在延伸部分的横截面积增大时变成更大。阻抗减小会引起电路径中的阻抗失配,使得UFS或PCIe中发射和接收的信号的质量高速退化。
在所述实施例中,凸块28的横截面积小于或等于第一输入/输出端子16的横截面积。另外,凸块28的直径D1小于或等于通孔9c的直径D3和布线9的宽度中的每一个。因此,使凸块28中的阻抗减小的量更小,且避免处理器6与存储器控制器15发射和接收的信号的质量退化。
在根据上文所描述的第一实施例的电子设备1中,凸块28在凸块28在Z轴的负方向上处于存储器控制器15正下方的位置处从第一封装11的下表面11a突出,并电连接到第一输入/输出端子16。因此,凸块28与第一输入/输出端子16之间的电路径比凸块28在与Z轴的负方向相交的方向上与存储器控制器15间隔开时更短。另外,凸块28容纳于凸块28在Z轴的负方向上处于存储器控制器15正下方的位置处,使得凸块28的大小受到限制。因此,凸块28的大小被设定成比至少一个凸块28在与Z轴的负方向相交的方向上与存储器控制器15间隔开时更小。因此,在第一输入/输出端子16与凸块28之间的电路径中,避免了由寄生电容增大引起的阻抗减小,且避免了由阻抗失配引起的半导体存储装置7的信号质量退化。
存储器控制器15设置于第一封装11中,且定位于第一封装11的下表面11a与上表面11b之间。因此,可使半导体存储装置7比存储器控制器15安装于衬底上时更薄。
凸块28设置于凸块28在Z轴的负方向上处于凸块28电连接到的第一输入/输出端子16正下方的位置处。因此,减少凸块28与第一输入/输出端子16之间的电路径,且电路径的设计是简单的。
凸块28垂直于Z轴的负方向的横截面积小于或等于第一输入/输出端子16的横截面积。因此,在第一输入/输出端子16与凸块28之间的电路径中,避免了由凸块28的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
凸块28的垂直于Z轴的负方向的方向上的直径D1小于或等于布线9的宽度W。因此,在第一输入/输出端子16与处理器6之间的电路径中,避免了由凸块28的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
垂直于Z轴的负方向的方向上的凸块28的直径D1小于或等于通孔9c的直径D3。因此,在第一输入/输出端子16与处理器6之间的电路径中,避免了由凸块28的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
第一封装11的上表面11b大于存储器控制器15的上表面15b。存储器芯片12堆叠于第一封装11的上表面11b上。因此,存储器芯片12可稳定地堆叠。
在第一实施例中,凸块28设置于凸块28在Z轴的负方向上处于第一输入/输出端子16正下方的位置处。但是,在其它实施例中,凸块28可在与Z轴的负方向相交的方向上与第一输入/输出端子16间隔开,只要凸块28定位于凸块28在Z轴的负方向上处于存储器控制器15正下方的位置处即可。
第二实施例
在下文中,将参考图5描述第二实施例。在以下实施例的描述中,与上文所描述的组件具有相同功能的组件由与上述组件相同的附图标记表示,且将不重复描述。另外,由相同附图标记表示的组件的所有功能和性质不必共用,且由相同附图标记表示的组件可具有根据实施例中的每一个的不同功能和性质。
图5是示意性地说明根据第三实施例的半导体存储装置7的一部分的横截面图。如图5中所说明,在第二实施例中,第一输入/输出端子16包含垫16a和势垒金属16b。
垫16a由例如铜、铜合金、铝或铝合金等导体形成,并且是设置于存储器控制器15的下表面15a上的端子。垫16a从设置于第一绝缘层22中的开口暴露。
势垒金属16b由导体形成,例如钛、镍、钨、钴、钯或金。势垒金属16b覆盖暴露的垫16a并连接到垫16a。
凸块28是例如焊料凸块或包含铜和焊料的铜柱凸块,并连接到势垒金属16b。也就是说,凸块28直接连接到第一输入/输出端子16。因此,存储器控制器15的第一输入/输出端子16实际上用作半导体存储装置7的输入/输出端子。替代地,可不提供势垒金属16b使得凸块28直接连接到垫16a。
在根据第二实施例的电子设备1中,凸块28直接连接到第一输入/输出端子16。因此,凸块28的大小类似于第一输入/输出端子16的大小。因此,在第一输入/输出端子16与凸块28之间的电路径中,避免了由寄生电容增大引起的阻抗减小,且避免了由阻抗失配引起的半导体存储装置7的信号质量退化。
第三实施例
在下文中,将参考图6和7描述第三实施例。图6是示意性地说明根据第三实施例的半导体存储装置7的一部分的横截面图。如图6中所说明,根据第三实施例的半导体存储装置7包含存储器芯片12、导线13、密封树脂14、存储器控制器15和衬底41。
根据第三实施例的存储器控制器15进一步包含多个控制器凸块45、连接凸块46和电源凸块47。控制器凸块45、连接凸块46和电源凸块47是例如半球面焊料凸块,并在Z轴的负方向上从存储器控制器15的下表面15a突出。
控制器凸块45连接到第一输入/输出端子16。连接凸块46连接到第二输入/输出端子17。电源凸块47连接到电源端子18。
衬底41是例如印刷线路板。衬底41包含下表面41a和上表面41b。下表面41a是端子表面的实例。上表面41b是端子表面的实例。
下表面41a是面朝Z轴的负方向的大体上平坦的表面。上表面41b是与下表面41a相对的定位并面朝Z轴的正方向的大体上平坦的表面。上表面41b面朝存储器控制器15的下表面15a。
衬底41进一步包含基座51、多个连接导体52、第一连接端子53、第二连接端子54、连接布线55、电源布线56、第一绝缘层57、第二绝缘层58、多个外部凸块61和电源凸块62。
基座51由绝缘材料形成。基座51包含下表面51a和上表面51b。下表面51a是面朝Z轴的负方向的大体上平坦的表面。上表面51b是面朝Z轴的正方向的大体上平坦的表面。
图7是示意性地说明根据第三实施例的半导体存储装置7的一部分的横截面图。连接导体52由例如铜等导体形成。连接导体52中的每一个包含第一衬垫52a、第二衬垫52b和通孔52c。
第一衬垫52a设置于基座51的下表面51a上。第二衬垫52b设置于基座51的上表面51b上,并面朝第一输入/输出端子16和控制器凸块45。第一衬垫52a和第二衬垫52b中的每一个形成为圆形形状,但可形成为例如四边形形状等另一形状。通孔52c设置于基座51中,并在Z轴方向上穿透基座51。通孔52c连接第一衬垫52a与第二衬垫52b。
第一连接端子53、第二连接端子54和连接布线55由例如铜等导体形成,并设置于基座51的上表面51b上。第一连接端子53面朝第二输入/输出端子17。第二连接端子54设置于在与Z轴的负方向相交的方向上与存储器控制器15间隔开的位置处。连接布线55连接第一连接端子53与第二连接端子54。势垒金属可形成于第一连接端子53的表面上以便改良焊料连接性,且镍/金镀层可形成于第二连接端子54的表面上以便改良导线粘合性。
图6中所说明的电源布线56由例如铜等导体形成,并包含第一电源导体56a、第二电源导体56b和电源通孔56c。在所述实施例中,第一电源导体56a和第二电源导体56b是布线图案,但垫仅可以是垫。
第一电源导体56a设置于基座51的下表面51a上。第二电源导体56b设置于基座51的上表面51b上。电源通孔56c设置于基座51中,并在Z轴方向上穿透基座51。电源通孔56c连接第一电源导体56a与第二电源导体56b。
在电源通孔56c与在与Z轴的负方向相交的方向上与存储器控制器15间隔开的位置之间,第一电源导体56a沿着衬底41的下表面41a延伸。在电源通孔56c与第二电源导体56b在Z轴的负方向上处于存储器控制器15正下方的位置之间,第二电源导体56b沿着衬底41的上表面41b延伸。
第一绝缘层57是例如防焊剂,并设置于基座51的下表面51a上。第一绝缘层57形成衬底41的下表面41a。在第一绝缘层57中,设置多个开口,第一衬垫52a和第一电源导体56a的末端部分从所述开口暴露。因此,第一衬垫52a和第一电源导体56a的末端部分设置于衬底41的下表面41a上。第一电源导体56a的末端部分可处于垫正下方,如同其它连接导体的状况下。
第二绝缘层58是例如防焊剂并设置于基座51的上表面51b上。第二绝缘层58形成衬底41的上表面41b。在第二绝缘层58中,设置多个开口,第二垫52b、第一连接端子53、第二连接端子54和第二电源导体56b的末端部分从所述开口暴露。因此,第二垫52b、第一连接端子53、第二连接端子54和第二电源导体56b的末端部分设置于衬底41的上表面41b上。
通过倒装芯片安装,存储器控制器15安装于衬底41上。控制器凸块45连接到连接导体52的第二垫52b。连接凸块46连接到第一连接端子53。因此,第一连接端子53通过连接凸块46电连接到第二输入/输出端子17。另外,电源凸块47连接到第二电源导体56b的末端部分。因此,电源布线56电连接到电源端子18。
如图7中所说明,连接导体52中的每一个设置于连接导体52在Z轴的负方向上处于连接导体52电连接到的第一输入/输出端子16正下方的位置处。因此,连接导体52设置于连接导体52在Z轴的负方向上处于存储器控制器15正下方的位置处。
外部凸块61是例如半球面焊料凸块并连接到连接导体52的第一衬垫52a。因此,连接导体52将控制器凸块45与外部凸块61彼此连接。外部凸块61通过连接导体52和控制器凸块45电连接到第一输入/输出端子16。
外部凸块61定位于外部凸块61在Z轴的负方向上处于外部凸块61电连接到的第一输入/输出端子16正下方的位置处。因此,外部凸块61定位于外部凸块61在Z轴的负方向上处于存储器控制器15正下方的位置处。外部凸块61在Z轴的负方向上从设置于衬底41的下表面41a上的第一衬垫52a突出。
如图6中所说明,电源凸块62是例如半球面焊料凸块。在与Z轴的负方向相交的方向上,电源凸块62在与存储器控制器15间隔开的位置处连接到电源布线56的第一电源导体56a的末端部分。因此,电源布线56将电源端子18与电源凸块62彼此连接。电源凸块62在Z轴的负方向上从第一电源导体56a的设置于衬底41的下表面41a上的末端部分突出。
通过倒装芯片安装,半导体存储装置7安装于主板5上。外部凸块61连接到设置于主板5中的垫。当半导体存储装置7安装于主板5上时,外部凸块61通过图1的布线9连接到处理器6。另外,电源凸块62连接到电子设备1的电源电路。
衬底41可包含多个其它凸块。凸块包含例如连接到接地垫的凸块或与电路分离来固定半导体存储装置7的凸块。
存储器芯片12堆叠于存储器控制器15的上表面15b上。存储器12可通过粘合层12a接合到另一存储器12或存储器控制器15的上表面15b。存储器控制器15嵌入于粘合层12a中。
导线13将一个存储器12与另一存储器12彼此连接,并将存储器12与设置于衬底41的上表面41b上的第二连接端子54彼此连接。因此,导线13将存储器芯片12与第二连接端子54彼此电连接。
存储器控制器15的第二输入/输出端子17通过连接凸块46、第一连接端子53、连接布线55、第二连接端子54和导线13电连接到存储器芯片12。因此,存储器控制器15向存储器芯片12发射信号并从其接收信号,并可控制存储器芯片12。
密封树脂14密封并覆盖衬底41的上表面41b、存储器控制器15、存储器芯片12和导线13。衬底41的上表面41b、存储器控制器15、存储器芯片12和导线13嵌入于密封树脂14中。
现参考图7,外部凸块61的直径D4小于或等于外部凸块61电连接到的第一输入/输出端子16的直径D2。因此,外部凸块61的横截面积小于或等于外部凸块61电连接到的第一输入/输出端子16的横截面积。直径D4是外部凸块61的垂直于Z轴的负方向的方向上的宽度。
外部凸块61的直径D4小于或等于外部凸块61连接到的连接导体52的直径D5。因此,外部凸块61的横截面积小于或等于外部凸块61连接到的连接导体52的横截面积。
在所述实施例中,连接导体52的第一衬垫52a、第二衬垫52b与通孔52c中的每一个具有相同直径D5。但是,第一衬垫52a、第二衬垫52b与通孔52c可具有不同直径。在此状况下,直径D5是第一衬垫52a、第二衬垫52b和通孔52c的直径当中的最大直径。
如上文所描述,连接导体52和外部凸块61的大小和间距与第一输入/输出端子16的大小和间距大体上匹配。但是,外部凸块61可在与Z轴的负方向相交的方向上比第一输入/输出端子16间隔开更大地间隔开,只要其设置于凸块在Z轴的负方向上处于存储器控制器15正下方的位置处即可。
外部凸块61的直径D4小于或等于图4的通孔9c的直径D3。另外,外部凸块61的直径D4小于或等于布线9的第一部分9a和第二部分9b中的每一个的宽度W。
在根据上文所描述的第三实施例的电子设备1中,外部凸块61在外部凸块61在Z轴的负方向上处于存储器控制器15正下方的位置处从衬底41的下表面41a突出。连接导体52在Z轴的负方向上设置于连接导体52处于存储器控制器15正下方的位置处,并将控制器凸块45与外部凸块61彼此连接。因此,控制器凸块45与外部凸块61之间的电路径比外部凸块61和连接导体52在与Z轴的负方向相交的方向上与存储器控制器15间隔开时更短。另外,外部凸块61容纳于外部凸块61在Z轴的负方向上处于存储器控制器15正下方的位置处,使得外部凸块61的大小受到限制。因此,外部凸块61的大小被设定成比至少一个外部凸块61在与Z轴的负方向相交的方向上与存储器控制器15间隔开时更小。因此,在第一输入/输出端子16与外部凸块61之间的电路径中,避免了由寄生电容增大引起的阻抗减小,且避免了由阻抗失配引起的半导体存储装置7的信号质量退化。
通过倒装芯片安装,存储器控制器15通过控制器凸块45、连接凸块46和电源凸块47安装于衬底41上。因此,接合线或DAF并非必需的,且可使半导体存储装置7变薄。
外部凸块61定位于外部凸块61在Z轴的负方向上处于外部凸块61电连接到的第一输入/输出端子16正下方的位置处。因此,减少外部凸块61与第一输入/输出端子16之间的电路径,且电路径的设计是简单的。
外部凸块61垂直于Z轴的负方向的横截面积小于或等于第一输入/输出端子16的横截面积。因此,在第一输入/输出端子16与外部凸块61之间的电路径中,避免了由外部凸块61的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
外部凸块61的垂直于Z轴的负方向的横截面积小于或等于连接导体52的垂直于Z轴的负方向的横截面积。因此,在第一输入/输出端子16与外部凸块61之间的电路径中,避免了由外部凸块61的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
外部凸块61的垂直于Z轴的负方向的方向上的直径D4小于或等于布线9的宽度W。因此,在第一输入/输出端子16与处理器6之间的电路径中,避免了由外部凸块61的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
外部凸块61的垂直于Z轴的负方向的方向上的直径D4小于或等于通孔9c的直径D3。因此,在第一输入/输出端子16与处理器6之间的电路径中,避免了由外部凸块61的寄生电容增大引起的阻抗减小。因此,避免了半导体存储装置7的由阻抗失配引起的信号质量退化。
根据上述实施例中的至少一个,凸块在第一方向上在凸块处于存储器控制器正下方的位置处从第一表面突出,并电连接到第一输入/输出端子。因此,凸块与第一输入/输出端子之间的电路径比凸块在与第一方向相交的方向上与存储器控制器间隔开时更短。举例来说,凸块直接连接到第一输入/输出端子。另外,凸块容纳于凸块在第一方向上处于存储器控制器正下方的位置处,使得凸块的大小受到限制。因此,凸块的大小被设定成比至少一个凸块在与同一第一方向相交的方向上与存储器控制器间隔开时更小。因此,在第一输入/输出端子与凸块之间的电路径中,避免了由寄生电容增大引起的阻抗减小,且避免了由阻抗失配引起的半导体存储装置的信号质量退化。
另外,第一实施例的图1和图4中所描述的解释还适用于第二和第三实施例。
虽然已描述某些实施例,但这些实施例仅作为实例而呈现,且其并不意欲限制本发明的范围。实际上,本文中所描述的新颖实施例可以多种其它形式体现;此外,可在不脱离本发明的精神的情况下进行本文中所描述的实施例的形式的各种省略、取代和改变。所附权利要求书和其等效物希望涵盖将属于本发明的范围和精神的此类形式或修改。
Claims (20)
1.一种电子设备,其包括:
第一封装,其包含面朝第一方向的第一表面、与所述第一表面相对的第二表面、设置于所述第一表面与所述第二表面之间的第一半导体芯片、设置于所述第一半导体芯片上且面朝所述第一方向的多个第一输入/输出端子、设置于所述第一半导体芯片上且面朝所述第一方向的第二输入/输出端子、电源端子、在与所述第一方向相交的第二方向上与所述第一半导体芯片间隔开的第一层间连接导体、将所述第二输入/输出端子与所述第一层间连接导体彼此连接的第一连接导体、其至少一部分设置于所述第二表面上且连接到所述第一层间连接导体的第二连接导体、电连接到所有所述第一输入/输出端子的多个第一凸块、且每一个所述第一凸块在所述第一方向上处于所述第一半导体芯片正下方的位置处从所述第一表面突出,以及在所述第二方向上与所述第一半导体芯片间隔开的位置处电连接到所述电源端子的电源凸块,其中在所述第一凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的凸块;
第二半导体芯片,其设置于所述第二表面上;
导线,其将所述第二半导体芯片与所述第二连接导体彼此电连接;以及
第二封装,其包含覆盖所述第二表面、所述第二半导体芯片和所述导线的涂层树脂。
2.根据权利要求1所述的电子设备,
其中所述第一凸块中的每一个设置于所述第一凸块在所述第一方向上处于所述第一凸块电连接到的所述第一输入/输出端子正下方的位置处。
3.根据权利要求1所述的电子设备,
其中所述多个第一凸块直接连接到所述多个第一输入/输出端子。
4.根据权利要求3所述的电子设备,
其中所述第一输入/输出端子中的每一个包含垫和所述垫与对应第一凸块之间的势垒金属。
5.根据权利要求1所述的电子设备,
其中所述第一凸块中的每一个的沿着垂直于所述第一方向的平面取得的横截面的最大面积小于或等于所述第一凸块电连接到的所述第一输入/输出端子的沿着垂直于所述第一方向的平面取得的横截面的最大面积。
6.根据权利要求1所述的电子设备,其中所述第一封装包含
模制树脂,其覆盖所述第一半导体芯片,以及
绝缘层,其形成于所述第一半导体芯片的面朝所述第一方向的表面上。
7.根据权利要求1所述的电子设备,其进一步包括:
第三半导体芯片,其控制所述第一半导体芯片;以及
衬底,其包含连接到所述多个第一凸块和所述第三半导体芯片的多个布线,其中所述第二方向上的所述第一凸块的最大宽度小于或等于所述布线的宽度。
8.根据权利要求1所述的电子设备,其进一步包括:
第三半导体芯片,其控制所述第一半导体芯片;以及
衬底,其包含多个层、设置于所述层中且将所述多个第一凸块与所述第三半导体芯片彼此连接的多个布线,以及将所述布线的设置于所述层中的一个中的一部分与所述布线的设置于所述层中的另一个中的一部分彼此连接的第二层间连接导体,
其中所述第二方向上的所述第一凸块的最大宽度小于或等于所述第二方向上的所述第二层间连接导体的最大宽度。
9.根据权利要求1所述的电子设备,其中
所述第一半导体芯片是存储器控制器,
所述第二半导体芯片是存储器芯片,且进一步包括:
多个额外存储器芯片,其堆叠于所述第二半导体芯片上。
10.根据权利要求1所述的电子设备,其中
所述多个第一输入/输出端子是向所述第一封装和所述第二封装外部的装置发射信号并从所述装置接收信号的输入/输出端子,
所述第二输入/输出端子是向所述第二半导体芯片发射信号并从所述第二半导体芯片接收信号的输入/输出端子。
11.一种电子设备,其包括:
第一半导体芯片,其包含面朝第一方向的多个第一输入/输出端子、面朝所述第一方向的第二输入/输出端子、面朝所述第一方向的电源端子,以及连接到所述多个第一输入/输出端子的多个第一凸块;
第一衬底,其包含面朝所述第一方向的第一输入/输出端子表面;与所述第一输入/输出端子表面相对并面朝所述第一半导体芯片的第二输入/输出端子表面;多个外部凸块,所述多个外部凸块自所述第一输入/输出端子表面突出并包含在所述第一方向上处于所述第一半导体芯片正下方的位置处的第二凸块和在与所述第一方向相交的第二方向上与所述第一半导体芯片间隔开的位置处电连接到所述电源端子的电源凸块,其中在所述第二凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的外部凸块;多个连接导体,所述多个连接导体设置于所述连接导体在所述第一方向上处于所述第一半导体芯片正下方的位置处,并将所述多个第一凸块与所述多个外部凸块彼此连接;设置于所述第二输入/输出端子表面上并电连接到所述第二输入/输出端子的第一连接端子;设置于所述第二输入/输出端子表面上的第二连接端子;以及将所述第一连接端子与所述第二连接端子彼此连接的连接布线;
第二半导体芯片,其设置于所述第一半导体芯片上;
导线,其将所述第二半导体芯片与所述第二连接端子彼此电连接;以及
涂层树脂,其覆盖所述第二输入/输出端子表面、所述第一半导体芯片和所述第二半导体芯片。
12.根据权利要求11所述的电子设备,
其中所述第二凸块中的每一个设置于所述第二凸块在所述第一方向上处于所述第二凸块电连接到的所述第一输入/输出端子正下方的位置处。
13.根据权利要求11所述的电子设备,
其中所述第二凸块中的每一个的沿着垂直于所述第一方向的平面取得的横截面的最大面积小于或等于所述第二凸块电连接到的所述第一输入/输出端子的沿着垂直于所述第一方向的平面取得的横截面的最大面积。
14.根据权利要求11所述的电子设备,
其中所述第二凸块中的每一个的沿着垂直于所述第一方向的平面取得的横截面的最大面积小于或等于所述第二凸块电连接到的所述连接导体的沿着垂直于所述第一方向的平面取得的横截面的最大面积。
15.根据权利要求11所述的电子设备,其中
所述第一半导体芯片是存储器控制器,
所述第二半导体芯片是存储器芯片,且进一步包括:
多个额外存储器芯片,其堆叠于所述第二半导体芯片上。
16.根据权利要求11所述的电子设备,其中
所述多个第一输入/输出端子是向所述第一半导体芯片和所述第二半导体芯片外部的装置发射信号并从所述装置接收信号的输入/输出端子,
所述第二输入/输出端子是向所述第二半导体芯片发射信号并从所述第二半导体芯片接收信号的输入/输出端子。
17.根据权利要求11所述的电子设备,其进一步包括:
第三半导体芯片,其控制所述第一半导体芯片;以及
衬底,其包含连接到所述多个第二凸块和所述第三半导体芯片的多个布线,其中所述第二方向上的所述第二凸块的最大宽度小于或等于所述布线的宽度。
18.根据权利要求11所述的电子设备,其进一步包括:
第三半导体芯片,其控制所述第一半导体芯片;以及
衬底,其包含多个层、设置于所述层中且将所述多个第二凸块与所述第三半导体芯片彼此连接的多个布线,以及将所述布线的设置于所述层中的一个中的一部分与所述布线的设置于所述层中的另一个中的一部分彼此连接的第二层间连接导体,
其中所述第二方向上的所述第二凸块的最大宽度小于或等于所述第二方向上的所述第二层间连接导体的最大宽度。
19.一种电子设备,其包括:
第一封装,其包含面朝第一方向的第一表面、与所述第一表面相对的第二表面、设置于所述第一表面与所述第二表面之间的第一半导体芯片、设置于所述第一半导体芯片上且面朝所述第一方向的多个第一输入/输出端子、设置于所述第一半导体芯片上且面朝所述第一方向的第二输入/输出端子、电源端子、在与所述第一方向相交的第二方向上与所述第一半导体芯片间隔开的第一层间连接导体、将所述第二输入/输出端子与所述第一层间连接导体彼此连接的第一连接导体、其至少一部分设置于所述第二表面上且连接到所述第一层间连接导体的第二连接导体、电连接到所有所述第一输入/输出端子的多个第一凸块、且每一个所述第一凸块在所述第一方向上处于所述第一半导体芯片正下方的位置处从所述第一表面突出,以及在所述第二方向上与所述第一半导体芯片间隔开的位置处电连接到所述电源端子的电源凸块,其中在所述第一凸块与所述电源凸块之间不存在不在所述第一方向上处于所述第一半导体芯片正下方的凸块,
模制树脂,其囊封所述第一半导体芯片,以及形成于所述第一半导体芯片的面朝所述第一方向的表面上的绝缘层;
多个第二半导体芯片,其堆叠于所述第二表面上;
导线,其将所述多个第二半导体芯片与所述第二连接导体彼此电连接;
第二封装,其包含覆盖所述第二表面、所述第二半导体芯片和所述导线的涂层树脂;
第三半导体芯片,其控制所述第一半导体芯片;以及
衬底,其包含连接到所述多个第一凸块和所述第三半导体芯片的多个布线,
其中所述第二方向上的所述第一凸块的最大宽度小于或等于所述布线的最大宽度。
20.根据权利要求19所述的电子设备,其中
所述衬底包含多个层、设置于所述层中的多个布线,以及将所述布线的设置于所述层中的一个中的一部分与所述布线的设置于所述层中的另一个中的一部分彼此连接的第二层间连接导体,
所述第一半导体芯片是存储器控制器,
所述第二半导体芯片是存储器芯片,
所述第三半导体芯片是处理器,
所述存储器控制器与所述处理器通过所述第一输入/输出端子彼此通信,且
所述存储器控制器与所述存储器芯片通过所述第二输入/输出端子彼此通信。
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US11069605B2 (en) * | 2019-04-30 | 2021-07-20 | Advanced Semiconductor Engineering, Inc. | Wiring structure having low and high density stacked structures |
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KR20210077290A (ko) * | 2019-12-17 | 2021-06-25 | 에스케이하이닉스 주식회사 | 적층 반도체 칩을 포함하는 반도체 패키지 |
US11538506B2 (en) * | 2020-07-21 | 2022-12-27 | Samsung Electronics Co., Ltd. | Semiconductor device and semiconductor package including the semiconductor device |
US11830849B2 (en) * | 2021-11-04 | 2023-11-28 | Western Digital Technologies, Inc. | Semiconductor device with unbalanced die stackup |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1262800A (zh) * | 1998-02-17 | 2000-08-09 | 株式会社爱德万测试 | Ic插座 |
CN1477923A (zh) * | 2003-08-01 | 2004-02-25 | 威盛电子股份有限公司 | 信号传输结构 |
CN104425468A (zh) * | 2013-09-06 | 2015-03-18 | 株式会社东芝 | 半导体封装 |
CN106373934A (zh) * | 2015-09-04 | 2017-02-01 | Nepes株式会社 | 半导体封装结构及制造方法 |
CN107644871A (zh) * | 2016-07-21 | 2018-01-30 | 三星电子株式会社 | 固态驱动器封装 |
CN108269797A (zh) * | 2016-12-30 | 2018-07-10 | 三星电子株式会社 | 电子装置封装 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI247366B (en) * | 2004-09-29 | 2006-01-11 | Advanced Semiconductor Eng | Stacked package structure, multi-chip package structure and process thereof |
KR20130110937A (ko) * | 2012-03-30 | 2013-10-10 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
JP5918664B2 (ja) | 2012-09-10 | 2016-05-18 | 株式会社東芝 | 積層型半導体装置の製造方法 |
KR102065008B1 (ko) * | 2013-09-27 | 2020-01-10 | 삼성전자주식회사 | 적층형 반도체 패키지 |
TWI520278B (zh) * | 2014-01-15 | 2016-02-01 | 矽品精密工業股份有限公司 | 嵌埋有晶片之封裝結構的製法 |
KR102337876B1 (ko) * | 2014-06-10 | 2021-12-10 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US9761562B2 (en) | 2015-05-06 | 2017-09-12 | Micron Technology, Inc. | Semiconductor device packages including a controller element |
KR20170082677A (ko) | 2016-01-06 | 2017-07-17 | 에스케이하이닉스 주식회사 | 관통 몰드 커넥터를 포함하는 반도체 패키지 및 제조 방법 |
JP6955864B2 (ja) * | 2016-12-26 | 2021-10-27 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
-
2018
- 2018-09-14 JP JP2018173030A patent/JP2020047652A/ja active Pending
-
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- 2019-02-19 TW TW108105416A patent/TWI708349B/zh active
- 2019-02-20 US US16/281,004 patent/US10861812B2/en active Active
- 2019-03-07 CN CN201910170127.0A patent/CN110911380B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1262800A (zh) * | 1998-02-17 | 2000-08-09 | 株式会社爱德万测试 | Ic插座 |
CN1477923A (zh) * | 2003-08-01 | 2004-02-25 | 威盛电子股份有限公司 | 信号传输结构 |
CN104425468A (zh) * | 2013-09-06 | 2015-03-18 | 株式会社东芝 | 半导体封装 |
CN106373934A (zh) * | 2015-09-04 | 2017-02-01 | Nepes株式会社 | 半导体封装结构及制造方法 |
CN107644871A (zh) * | 2016-07-21 | 2018-01-30 | 三星电子株式会社 | 固态驱动器封装 |
CN108269797A (zh) * | 2016-12-30 | 2018-07-10 | 三星电子株式会社 | 电子装置封装 |
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US10861812B2 (en) | 2020-12-08 |
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JP2020047652A (ja) | 2020-03-26 |
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