CN115084120A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN115084120A
CN115084120A CN202110816316.8A CN202110816316A CN115084120A CN 115084120 A CN115084120 A CN 115084120A CN 202110816316 A CN202110816316 A CN 202110816316A CN 115084120 A CN115084120 A CN 115084120A
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China
Prior art keywords
interposer
semiconductor chip
semiconductor device
semiconductor
main surface
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CN202110816316.8A
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English (en)
Inventor
茨木聪一郎
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Kioxia Corp
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Kioxia Corp
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Publication of CN115084120A publication Critical patent/CN115084120A/zh
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一个实施方式的目的在于，提供能够提高被安装的半导体芯片的可靠性的半导体装置。根据一个实施方式，在半导体装置中，第1中介层具有第1主面。第2中介层配置于第1主面。第2中介层在第1中介层的相反侧具有第2主面。第2中介层的材质与第1中介层不同。第1半导体芯片具有第1表面。第1半导体芯片在第1表面与第2主面面对面的状态下经由多个凸点电极被安装于第2主面。第1半导体芯片具有易失性存储器电路。第2半导体芯片经由多个键合引线被安装于配置在第1主面或者第2主面上的多个电极图案。第2中介层在与第1主面垂直的方向上与第1半导体芯片重叠。

Description

半导体装置
关联申请：
本申请以日本专利申请2021-042091号(申请日：2021年3月16日)作为在先申请享受优先权。本申请通过参照该在先申请从而包含在先申请的全部内容。
技术领域
本实施方式涉及半导体装置。
背景技术
有时在中介层(Interposer)的主面经由多个凸点电极安装半导体芯片来构成半导体装置。此时，希望提高被安装的半导体芯片的可靠性。
发明内容
一个实施方式的目的在于，提供能够提高被安装的半导体芯片的可靠性的半导体装置。
根据一个实施方式，提供具有第1中介层、第2中介层、第1半导体芯片和第2半导体芯片的半导体装置。第1中介层具有第1主面。第2中介层配置于第1主面。第2中介层在第1中介层的相反侧具有第2主面。第2中介层的材质与第1中介层不同。第1半导体芯片具有第1表面。第1半导体芯片在第1表面与第2主面面对面的状态下经由多个凸点电极被安装于第2主面。第1半导体芯片具有易失性存储器电路。第2半导体芯片经由多个键合引线被安装于配置在第1主面或者第2主面上的多个电极图案。第2中介层在与第1主面垂直的方向上与第1半导体芯片重叠。
附图说明
图1是表示实施方式所涉及的半导体装置的构成的剖视图。
图2是表示实施方式所涉及的半导体装置的构成的平面图。
图3是表示实施方式所涉及的中介层的构成的剖视图。
图4是表示阿尔法粒子的能量与在硅中的射程之间的相关关系的图。
图5是表示实施方式的第1变形例所涉及的半导体装置的构成的剖视图。
图6是表示实施方式的第2变形例所涉及的半导体装置的构成的剖视图。
图7是表示实施方式的第3变形例所涉及的半导体装置的构成的剖视图。
图8是表示实施方式的第3变形例所涉及的半导体装置的构成的平面图。
图9是表示实施方式的第4变形例所涉及的半导体装置的构成的剖视图。
图10是表示实施方式的第4变形例所涉及的半导体装置的构成的平面图。
图11是表示实施方式的第5变形例所涉及的半导体装置的构成的剖视图。
图12是表示实施方式的第5变形例所涉及的半导体装置的构成的平面图。
图13是表示实施方式的第6变形例所涉及的半导体装置的构成的剖视图。
图14是表示实施方式的第6变形例所涉及的半导体装置的构成的平面图。
附图标记说明
1、1j、1k、1n、1p、1s、1t半导体装置，10、10n、10p、10t、30、30n中介层，20、40、40-1、40-2半导体芯片。
具体实施方式
以下参照附图，详细说明实施方式所涉及的半导体装置。此外，本发明不被这些实施方式限定。
(实施方式)
实施方式所涉及的半导体装置是混载多种半导体芯片的混合类型的半导体装置。例如，随着以智能电话为代表的移动设备的高性能/高功能化以及轻薄小型化的进展，要求兼顾设备中搭载的存储器半导体装置的大容量化和封装的轻薄小型化。与这种要求相应地，在半导体装置中，可以混载相互种类不同的第1半导体芯片和第2半导体芯片。第1半导体芯片例如是存储器控制器，第2半导体芯片例如是闪存等存储器芯片。第2半导体芯片为了取得存储器容量，芯片大小构成得比第1半导体芯片大。第1半导体芯片能够配置的区域可能根据第2半导体芯片的配置而被限定。
例如，在作为混合存储器模组的一个方式的作为代表性的嵌入式存储器的UFS(通用闪存(Universal Flash Storage))中，由外部标准团体规定了外围体的纵横尺寸，封装的设计自由度小。如果是大容量产品，则为了提高安装密度，可以考虑采用将第2半导体芯片以台阶状层叠的构造。在芯片与封装的长边尺寸大致相同的CSP(芯片级封装(ChipScale Package))类型的封装的情况下，为了实现与主机侧的高速信号收发，有时在以台阶状层叠的多个第2半导体芯片的最下级正下方配置第1半导体芯片。进而，为了减小由于第1半导体芯片的主机接口的键合引线的寄生LCR成分引起的负载来缩短电长度，另外，为了应对与第1半导体芯片的高功能化相伴的引脚的增多，考虑以倒装芯片构造来安装第1半导体芯片。
第1半导体芯片在是存储器控制器的情况下，可以搭载易失性存储器电路作为缓存区域等。易失性存储器电路例如是SRAM(静态随机存取存储器(Static Random AccessMemory))。第1半导体芯片由于系统规模变大而存在SRAM变得大容量/低电压的倾向，这些要素与每单位设备的软错误率(FIT)处于相互权衡的关系。
例如，考虑第1半导体芯片被安装于第1中介层的构成。第1中介层从成本等观点出发，可以使用包含辐射源的有机中介层。第1半导体芯片如果以倒装芯片构造被安装于第1中介层，则与以键合引线构造被安装于第1中介层的情况相比，与第1中介层内的辐射源的距离可能变得更近。由此，在被搭载于第1半导体芯片的SRAM中容易引起软错误，位翻转耐受性等软错误耐受性有可能降低。
另外，在对第1半导体芯片采用倒装芯片构造的情况下，由于第1半导体芯片的引脚大量增多，可能会实现低矮凸点而且窄间距的倒装芯片连接。因此，有可能由于第1中介层(例如有机中介层)与第1半导体芯片之间的线膨胀系数不匹配，造成电极的接合部分断裂等，结果连接可靠性即机械的可靠性降低。
另外，如果由于第1半导体芯片的高性能/高功能化而电路密度上升，但芯片面积处于缩小的倾向，则第1半导体芯片中的发热密度处于增高的倾向。因此，有可能由于第1半导体芯片的进一步的温度上升，半导体装置的品质/性能的可靠性即热可靠性降低。
于是，在本实施方式中，在半导体装置中，在第1中介层与第1半导体芯片之间追加第2中介层，将第1半导体芯片倒装芯片地安装至第2中介层。第2中介层可以由放射线的屏蔽能力比第1中介层高、且机械的/热的特性比第1中介层更接近第1半导体芯片的材质形成。由此，在半导体装置中，实现软错误耐受性提高以及机械的/热的可靠性提高。
具体而言，半导体装置1可以如图1及图2所示构成。图1是表示半导体装置1的构成的剖视图。图2是表示半导体装置1的构成的平面图。
半导体装置1具有中介层(第1中介层)10、半导体芯片(第1半导体芯片)20、中介层(第2中介层)30、多个半导体芯片(多个第2半导体芯片)40-1、40-2、密封树脂50、外部电极60及间隔件70。以下，将与中介层10的面积最大的面之中的一个面(表面10a、第1主面)垂直的方向作为Z方向，将与Z方向垂直的平面内相互正交的2个方向作为X方向及Y方向。
中介层10在+Z侧具有面积最大的面(表面10a、第1主面)，在-Z侧具有面积最大的另一面(背面10b、第2主面)。在中介层10的表面10a配置有中介层30，经由中介层30安装有半导体芯片20。另外，在中介层10的表面10a侧，经由粘合层81及间隔件70安装有多个半导体芯片40-1、40-2。
在中介层10的表面10a配置有开口部10a1。在开口部10a1内配置有中介层30。例如，中介层30的背面30b也可以通过粘结剂等被粘合于开口部10a1的底面。中介层30在XY平面图中为大致矩形，在YZ平面图中为大致矩形。
开口部10a1具有与中介层30对应的平面形状。例如，可以通过使用激光或钻头对中介层10的表面10a进行锪孔加工而形成开口部10a1。因此，开口部10a1在XY平面图中，如图2所例示，也可以是由于工艺的因素而在角处具有稍许圆角或倒角而被识别为大致矩形的形状。在图2中，例示了将多个半导体芯片40-1、40-2及密封树脂50去除后的状态的平面构成。开口部10a的X方向宽度对应于中介层30的X方向宽度，具有对中介层30的X方向宽度加上余量而得到的大小。开口部10a的Y方向宽度对应于中介层30的Y方向宽度，具有对中介层30的Y方向宽度加上余量而得到的大小。在从Z方向透视的情况下，开口部10a1在内侧包含中介层30。
开口部10a1具有与中介层30对应的截面形状。开口部10a1在YZ平面图中，如图1所示为大致矩形。开口部10a的Z方向深度对应于中介层30的Z方向厚度。开口部10a的Z方向深度也可以与中介层30的Z方向厚度大致相等。在该情况下，开口部10a内配置的中介层30的表面与中介层10的表面10a也可以是大致同一面。由此，易于将中介层30的Z方向的安装高度抑制得更低，因此能够有助于将半导体装置1整体的安装高度抑制得更低。
此外，开口部10a1的Z方向深度也可以比中介层30的Z方向厚度稍小。在该情况下，与开口部10a1的Z方向深度相应地也易于将中介层30的Z方向的安装高度抑制得更低，因此能够有助于将半导体装置1整体的安装高度抑制得更低。
在中介层10的背面10b安装有外部电极60。在中介层10的表面10a侧安装的半导体芯片20、中介层30及多个半导体芯片40被密封树脂50密封。在中介层10的背面10b侧安装的外部电极60可以由以导电物作为主成分的材料形成，并且其表面露出，可以被从外部电连接。
中介层10例如也可以是印刷线路板等包含有机物的有机中介层。中介层10中在体积上占据较大比例的部分可以由有机物形成。中介层10具有阻焊层11、半固化层12、核心层13、导电层14及通孔电极15。阻焊层11可以由以绝缘物(例如绝缘性的有机类物质)作为主成分的材料形成。阻焊层11的材料可以包含微量的放射性物质。半固化层12可以由以绝缘物(例如塑料等有机类物质)作为主成分的材料形成。半固化层12的材料可以包含微量的放射性物质。核心层13可以由以绝缘物(例如塑料等有机类物质)作为主成分的材料形成。核心层13的材料可以包含微量的放射性物质。导电层14可以由以导电物(例如铜)作为主成分的材料形成。通孔电极15可以由以导电物(例如铜)作为主成分的材料形成。
半导体芯片20例如是控制器芯片。半导体芯片20在-Z侧具有面积最大的面(表面20a、第3主面)，在+Z侧具有面积最大的另一面(背面20b、第4主面)。在半导体装置1是SSD的情况下，半导体芯片20例如是控制器芯片，可以以倒装芯片方式被安装于中介层10。半导体芯片20的表面20a与中介层30的表面30a面对面。半导体芯片20经由多个凸点电极21以面朝下方式(倒装芯片方式)被安装于中介层30的表面30a。即，半导体芯片20在表面20a与中介层30的表面30a面对面的状态下经由多个凸点电极21被安装于中介层30的表面30a。
在半导体芯片20的表面20a配置有多个焊盘电极，多个焊盘电极经由多个凸点电极21而与中介层30内的布线电连接。中介层30内的布线与中介层10中的导电层14及通孔电极15电连接。由此，可以从外部电极60经由导电层14及通孔电极15、中介层30内的布线向半导体芯片20收发规定的信号。
可以与中介层30内的布线电连接的导电层14在中介层10的开口部10a1的底面上具有如图2中以虚线表示的多个电极图案141-1～141-n(n是任意的2以上的整数)。多个电极图案141-1～141-n在XY方向上以2维排列。图2是表示中介层10的构成的平面图。各电极图案141-1～141-n为了可以传送相互不同的信号，可以在开口部10a1的底面上相互被电分离。各电极图案141-1～141-n的配置间距也可以比凸点电极21的配置间距大。
在中介层30内，例如图3所示，设置有用于将凸点电极21与电极图案141连接的布线。图3是表示中介层30的构成的剖视图。中介层30具有基板33、贯通电极31及再布线层32。基板33沿着XY方向以平板状延伸。贯通电极31在Z方向上延伸并从+Z侧向-Z侧贯通基板33。贯通电极31可以由导电物(例如铜等金属)形成。在基板33的-Z侧的面上，配置有再布线层32。贯通电极31中，+Z侧的面与凸点电极21接触而电连接，+Z侧的面经由再布线层32而与电极图案141电连接。再布线层32中，布线部分可以由导电物(例如铜等金属)形成，此外的部分可以由绝缘物(例如氧化硅)形成。电极图案141经由导电层14及通孔电极15而与外部电极60电连接。
此外，用于将中介层30中的凸点电极21与导电层14连接的布线也可以采用引线键合构造来替代贯通电极31及再布线层32。也可以在中介层30的表面30a上设置供凸点电极21连接的电极，引线从该电极向导电层14键合。
在图1所示的半导体芯片20的表面20a侧，搭载有CPU和易失性存储器电路。易失性存储器电路例如是SRAM电路。SRAM电路作为CPU的工作区域而临时存储数据。中介层30的表面30a具有如图2所示的区域FRG1。区域FRG1在半导体芯片20以倒装芯片方式被安装于中介层30时，在从与中介层30的表面30a垂直的方向(Z方向)透视的情况下与SRAM电路重叠。区域FRG1的面积与SRAM电路大致相等(例如，与SRAM电路在数学上基本全等)。区域FRG1被包含在区域FRG2的内侧。区域FRG2在半导体芯片20以倒装芯片方式被安装于中介层30时，在从Z方向透视的情况下与半导体芯片20重叠。区域FRG2的面积与半导体芯片20大致相等(例如，与半导体芯片20在数学上基本全等)。即，区域FRG2是在从Z方向透视的情况下与半导体芯片20重叠的区域，是在从Z方向透视的情况下在内侧包含SRAM电路的区域。中介层30的XY面积对应于半导体芯片20的XY面积，也可以是对半导体芯片20的XY面积加上配置余量的面积而得到的面积。
中介层30的材质与中介层10不同。中介层30可以由放射线的屏蔽能力比中介层10高的材质形成。中介层30可以由机械的/热的特性比中介层10更接近半导体芯片20的材质形成。中介层30的线膨胀系数与半导体芯片20的线膨胀系数之差，比中介层10的线膨胀系数与半导体芯片20的线膨胀系数之差小。中介层30可以由热传导率比中介层10大的材质形成。
例如，中介层30也可以是包含半导体的半导体中介层。中介层30中在体积上占据较大比例的部分可以由半导体形成。中介层30被配置在中介层10的表面10a的开口部10a1内。例如，中介层30覆盖半导体芯片20的表面20a中的区域FRG2(参照图2)。中介层30在从Z方向透视的情况下与SRAM电路重叠。中介层30在从Z方向透视的情况下在内侧包含SRAM电路。在从Z方向透视的情况下，中介层30在区域FRG2中与半导体芯片20重叠。在中介层30中，基板33(参照图3)可以由以半导体(例如硅)作为主成分的材料形成。在中介层10为有机中介层且中介层30为半导体中介层的情况下，中介层30对放射线的屏蔽能力比中介层10高。
例如，阿尔法粒子的能量与在硅中的射程(飞行距离)之间的相关关系如图4所示。图4是表示阿尔法粒子的能量与在硅中的射程之间的相关关系的图。
在从中介层10中包含的放射性物质飞来的放射线(例如α线)的能量为9MeV以下的情况下，阿尔法粒子在硅中的射程为大致58μm。在中介层30由以硅作为主成分的材料形成的情况下，中介层30的Z方向厚度也可以是58μm以上。由此，能够通过中介层30有效地屏蔽从中介层10中包含的放射性物质飞来的放射线(例如α线)。另外，中介层30的Z方向厚度也可以比中介层10的Z方向厚度小。由此，能够将中介层30大致收存于中介层10的表面10a的开口部10a1，能够有效地减小中介层30的安装高度。
在从中介层10中包含的放射性物质飞来的放射线(例如α线)的能量为6MeV以下的情况下，阿尔法粒子在硅中的射程为大致32μm。在中介层30由以硅作为主成分的材料形成的情况下，中介层30的Z方向厚度也可以是32μm以上。由此，能够通过中介层30有效地屏蔽从中介层10中包含的放射性物质飞来的放射线(例如α线)。另外，中介层30的Z方向厚度也可以比中介层10的Z方向厚度小。由此，能够将中介层30大致收存于中介层10的表面10a的开口部10a1，能够有效地减小中介层30的安装高度。
此外，在中介层30中，图3所示的基板33可以设为在电位上浮动的状态。其结果，可以通过中介层30内的布线可靠地进行各凸点电极21及外部电极60间的信号的收发。
另外，图1所示的中介层30的线膨胀系数与半导体芯片20的线膨胀系数之差，比中介层10的线膨胀系数与半导体芯片20的线膨胀系数之差小。例如，在中介层10为有机中介层且中介层30为半导体中介层的情况下，中介层30的机械的/热的特性比中介层10更接近半导体芯片20。中介层30的线膨胀系数比中介层10的线膨胀系数更接近半导体芯片20的线膨胀系数。由此，在半导体装置1被置于高温环境下等时，与半导体芯片20被安装于中介层10的情况相比，能够减小经由凸点电极21作用于中介层30与半导体芯片20之间的应力。由此，能够提高中介层30及半导体芯片20之间的机械的连接可靠性。
另外，中介层30的热传导率比中介层10的热传导率高。例如，在中介层10为有机中介层且中介层30为半导体中介层的情况下，中介层30的热传导率比中介层10的热传导率高。由此，在由于半导体芯片20的高性能/高功能化引起电路密度上升而芯片面积处于缩小的倾向造成发热密度增高的情况下，中介层30能够作为使半导体芯片20的热在XY平面方向上散发并向周边环境中散热的热沉发挥功能。由此，能够抑制半导体芯片20的温度上升，能够提高半导体装置1的品质/可靠性。
多个半导体芯片40例如分别是存储器芯片，对于半导体芯片(控制器芯片)20以间隔件构造被安装。即，在相对于半导体芯片20在XY方向上分离的位置，配置有比半导体芯片20从中介层10的表面10a起的安装高度厚的间隔件70。在间隔件70的+Z侧层叠有多个半导体芯片40。间隔件70的-Z侧的面经由粘合层81被粘合于中介层10的表面10a。半导体芯片40-1的-Z侧的面经由粘合层80-1被粘合于间隔件70的+Z侧的面。半导体芯片40-2的-Z侧的面经由粘合层80-2被粘合于半导体芯片40-1的+Z侧的面。粘合层81、80-1、80-2分别例如也可以是DAF(芯片粘结膜(Die Attach Film))。
多个半导体芯片40可以以引线键合方式被安装于中介层10。此时，中介层10中的可以与多个键合引线41电连接的导电层14在表面(+Z侧的主面)10a上具有如图2所示的多个电极图案142-1～142-2k(k是任意的2以上的整数)。多个半导体芯片40可以经由多个键合引线41被安装于多个电极图案142-1～142-2k。由此，多个半导体芯片40可以通过引线键合方式利用间隔件构造被安装于中介层10。
如上，在实施方式中，在半导体装置1中，在中介层10与半导体芯片20之间追加中介层30，将半导体芯片20倒装芯片安装至中介层30。中介层30可以由放射线的屏蔽能力比中介层10高、且机械的/热的特性比中介层10更接近半导体芯片20的材质形成。由此，能够通过中介层30有效地屏蔽从中介层10中包含的放射性物质飞来的放射线(例如α线)，因此在半导体装置1中能够提高软错误耐受性。另外，在半导体装置1被置于高温环境下等时，能够减小经由凸点电极21作用于中介层30与半导体芯片20之间的应力，因此能够提高中介层30及半导体芯片20之间的机械的连接可靠性。另外，中介层30能够作为使半导体芯片20的热在XY平面方向上散发并向周边环境中散热的热沉发挥功能，因此能够抑制半导体芯片20的温度上升，能够提高半导体装置1的品质，能够提高热的可靠性。
此外，作为实施方式的第1变形例，半导体装置1j也可以如图5所示，采用省略间隔件70而代替于此配置了比半导体芯片20从中介层10的表面10a起的安装高度厚的粘合层80j-1的构造。图5是表示半导体装置1j的构成的剖视图。粘合层80j-1将半导体芯片40-1与中介层10的表面10a粘合，并且覆盖半导体芯片(控制器芯片)20而确保凸点电极21及半导体芯片20的安装高度。由此，不使用间隔件70就能够实现相当于间隔件构造的构造，因此能够减小安装成本。
另外，作为实施方式的第2变形例，半导体装置1k如图6所示，也可以在半导体芯片20及中介层30之间的多个凸点电极21的间隙中填充有底部填充树脂90。图6是表示半导体装置1k的构成的剖视图。底部填充树脂90能够使用混入了二氧化硅作为填料的环氧树脂。此时，填料的平均粒径能够设定为0.5～3μm的范围内。填料的含有量能够设定为60～75wt％的范围内。由此，即使不在半导体芯片20及中介层30之间填充密封树脂50，也能够可靠地对多个凸点电极21间进行绝缘，能够提高作为半导体装置1k的封装的可靠性。
另外，作为实施方式的第3变形例，半导体装置1n也可以如图7及图8所示，中介层30n的面积对应于中介层10n的面积。图7是表示半导体装置1n的构成的剖视图。图8是表示半导体装置1n的构成的平面图。在中介层10n的表面10a，大致跨整面配置有开口部10a1n。开口部10a1n具有与中介层30n对应的平面形状/截面形状，这点与实施方式是同样的。在该情况下，中介层30n在其表面30a具有如图8所示的多个电极图案34-1～34-2k(k是任意的2以上的整数)。多个半导体芯片40(参照图1)可以经由多个键合引线41被安装于多个电极图案34-1～34-2k。多个电极图案34-1～34-2k经由中介层30n内的布线并经由中介层10n的导电层14及通孔电极15而与外部电极60电连接。
中介层30n可以由放射线的屏蔽能力比中介层10n高、且机械的/热的特性比中介层10n更接近半导体芯片20的材质形成，这点与实施方式是同样的。由此，能够跨更大的面积有效地屏蔽从中介层10n中包含的放射性物质飞来的放射线(例如α线)。另外，中介层30n能够确保更大的散热面积，因此能够进一步抑制半导体芯片20的温度上升。
另外，作为实施方式的第4变形例，半导体装置1p也可以如图9及图10所示，中介层30被贴合于中介层10p的表面10a。图9是表示半导体装置1p的构成的剖视图。图10是表示半导体装置1p的构成的平面图。中介层30的XY面积对应于半导体芯片20的XY面积，也可以是对半导体芯片20的XY面积加上配置余量的面积而得到的面积。在中介层10n的表面10a未配置开口部10a1(参照图1、图2)。中介层30可以经由粘合材(未图示)被贴合于中介层10n的表面10a。或者，中介层30在背面30b具有电极的情况下，可以通过该电极与中介层10n的表面10a上的电极被合金接合，从而被贴合于中介层10n的表面10a。由此，能够省略在中介层10p的表面10a形成开口部10a1的加工处理，因此能够减少半导体装置1p的安装成本。
另外，作为实施方式的第5变形例，半导体装置1s也可以如图11及图12所示，中介层30n的面积对应于中介层10p的面积，中介层30n被贴合于中介层10p的表面10a。图11是表示半导体装置1s的构成的剖视图。图12是表示半导体装置1s的构成的平面图。中介层30n也可以具有与第3变形例的中介层30n同样的形状及尺寸。中介层10p也可以具有与第4变形例的中介层30n同样的形状及尺寸。
中介层30n可以由放射线的屏蔽能力比中介层10p高、且机械的/热的特性比中介层10p更接近半导体芯片20的材质形成，这一点与实施方式是同样的。由此，能够跨更大的面积有效地屏蔽从中介层10p中包含的放射性物质飞来的放射线(例如α线)。另外，中介层30n能够确保更大的散热面积，因此能够进一步抑制半导体芯片20的温度上升。另外，能够省略在中介层10p的表面10a形成开口部10a1(参照图1、图2)的加工处理，因此能够减小半导体装置1s的安装成本。
另外，作为实施方式的第6变形例，半导体装置1t也可以如图13及图14所示，安装为并排构造。图13是表示半导体装置1t的构成的剖视图。图14是表示半导体装置1t的构成的平面图。
在相对于半导体芯片20在XY方向上分离的位置，从中介层10t的表面10a在+Z侧层叠有多个半导体芯片40-1、40-2。多个半导体芯片40-1、40-2可以以引线键合方式被安装于中介层10t。此时，中介层10t中的可以与多个键合引线41电连接的导电层14在表面(+Z侧的主面)10a上具有多个电极图案142-1～142-2k(k是任意的2以上的整数)(参照图2)。由此，多个半导体芯片40-1、40-2可以通过引线键合方式以并排构造被安装于中介层10t。
在该情况下，在半导体装置1t中，使中介层30介于中介层10t与半导体芯片20之间。中介层30也可以被贴合于中介层10t的表面10a。例如，中介层30在Z方向上与半导体芯片20重叠。中介层30可以由放射线的屏蔽能力比中介层10t高、且机械的/热的特性比中介层10t更接近半导体芯片20的材质形成，这一点与实施方式是同样的。由此，能够由中介层30有效地屏蔽从中介层10t中包含的放射性物质飞来的放射线(例如α线)。另外，在半导体装置1t被置于高温环境下等时，能够减小经由凸点电极21作用于中介层30与半导体芯片20之间的应力。另外，中介层30能够作为使半导体芯片20的热在XY平面方向上散发并向周边环境中散热的热沉发挥功能。
以上说明了本发明的几个实施方式，但这些实施方式作为例子来提示，其意图不在于对发明的范围进行限定。这些新的实施方式能够以其他各种方式被实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。这些实施方式及其变形包含在发明的范围或主旨中，并包含在专利权利要求书所记载的发明及其等同的范围中。

Claims (12)

1.一种半导体装置，其中，具备：
第1中介层，具有第1主面；
第2中介层，配置于所述第1主面，在与所述第1中介层的相反侧具有第2主面，材质与所述第1中介层不同；
第1半导体芯片，具有第1表面，在所述第1表面与所述第2主面面对面的状态下经由多个凸点电极被安装于所述第2主面，具有易失性存储器电路；以及
第2半导体芯片，经由多个键合引线被安装于在所述第1主面或者所述第2主面上配置的多个电极图案，
所述第2中介层在与所述第1主面垂直的方向上与所述第1半导体芯片重叠。
2.如权利要求1所述的半导体装置，其中，
所述第1中介层包含放射性物质，
所述第2中介层对放射线的屏蔽能力比所述第1中介层高。
3.如权利要求1所述的半导体装置，其中，
所述第2中介层的线膨胀系数与所述第1半导体芯片的线膨胀系数之差，比所述第1中介层的线膨胀系数与所述第1半导体芯片的线膨胀系数之差小。
4.如权利要求1所述的半导体装置，其中，
所述第2中介层的热传导率比所述第1中介层的热传导率高。
5.如权利要求1所述的半导体装置，其中，
所述第1中介层是有机中介层，
所述第2中介层是半导体中介层。
6.如权利要求1所述的半导体装置，其中，
所述第1中介层在所述第1主面具有开口部，
所述第2中介层被配置在所述开口部内。
7.如权利要求1所述的半导体装置，其中，
所述第2中介层被贴合于所述第1主面。
8.如权利要求1所述的半导体装置，其中，
所述第2中介层的面积对应于所述第1半导体芯片的面积。
9.如权利要求1所述的半导体装置，其中，
所述第2中介层的面积对应于所述第1中介层的面积。
10.如权利要求1所述的半导体装置，其中，
所述第2中介层的厚度比所述第1中介层的厚度薄。
11.如权利要求10所述的半导体装置，其中，
所述第2中介层的厚度是58μm以上。
12.如权利要求10所述的半导体装置，其中，
所述第2中介层的厚度是32μm以上。
CN202110816316.8A 2021-03-16 2021-07-20 半导体装置 Pending CN115084120A (zh)

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