TWI698927B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI698927B
TWI698927B TW106128566A TW106128566A TWI698927B TW I698927 B TWI698927 B TW I698927B TW 106128566 A TW106128566 A TW 106128566A TW 106128566 A TW106128566 A TW 106128566A TW I698927 B TWI698927 B TW I698927B
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source
drain contact
dielectric layer
interlayer dielectric
gate
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TW201820457A (zh
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謝佾蒼
趙家忻
夏英庭
邱意為
許立德
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台灣積體電路製造股份有限公司
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Abstract

根據本發明一些實施例，提供一種半導體裝置的製造方法，上述方法包含形成底部源極/汲極接觸栓於底部層間介電層內，且底部源極/汲極接觸栓電性耦接至電晶體的源極/汲極區。上述方法包含形成第一層間介電層於底部源極/汲極接觸栓上以及形成源極/汲極接觸開口於第一層間介電層內，並且源極/汲極接觸開口露出底部源極/汲極接觸栓。上述方法包含形成介電間隙物層，其中介電間隙物層包含延伸至源極/汲極接觸開口的第一部份，以及位於第一層間介電層上的第二部份。上述方法亦包含對介電間隙物層執行非等向性蝕刻，其中介電間隙物層的餘留垂直部份形成源極/汲極接觸間隙物。上述方法更包含填充源極/汲極接觸開口的餘留部份，以形成頂部源極/汲極接觸栓。

Description

半導體裝置及其製造方法
本發明一些實施例係有關於半導體裝置及其製造方法，特別係有關於半導體裝置的內連線結構及其製造方法。
隨著積體電路的尺寸逐漸縮小，每一道形成製程也變為更加困難，並且，以往製程沒有問題的地方也出現了問題。例如，形成鰭式場效電晶體時，金屬閘極與鄰近的源極和汲極區可能會彼此電性短路。金屬閘極的接觸栓亦可能與鄰近的源極和汲極區彼此電性短路。
根據本發明一些實施例，提供一種方法。上述方法包含形成底部源極/汲極接觸栓於底部層間介電層內，其中底部源極/汲極接觸栓電性耦接至電晶體的源極/汲極區。上述方法包含形成第一層間介電層於底部源極/汲極接觸栓上以及形成第一源極/汲極接觸開口於第一層間介電層內，並且第一源極/汲極接觸開口露出底部源極/汲極接觸栓。上述方法包含形成第一介電間隙物層，其中第一介電間隙物層包含延伸至第一源極/汲極接觸開口的第一部份，以及位於第一層間介電層上的第二部份。上述方法亦包含對第一介電間隙物層執行非等 向性蝕刻，其中第一介電間隙物層的餘留垂直部份形成第一源極/汲極接觸間隙物。上述方法更包含填充第一源極/汲極接觸開口的餘留部份，以形成第一源極/汲極接觸栓。
根據本發明一些實施例，提供一種方法。上述方法包含形成第一源極/汲極接觸栓於第一層間介電層內，其中第一源極/汲極接觸栓電性耦接至電晶體的源極/汲極區。上述方法包含形成第二層間介電層於第一層間介電層上及形成第二源極/汲極接觸栓於第二層間介電層內。上述方法包含形成第三層間介電層於第二層間介電層上及蝕刻第二層間介電層及第三層間介電層以形成閘極接觸開口，其中閘極接觸開口露出電晶體的閘極電極。上述方法亦包含形成閘極接觸間隙物於閘極接觸開口內，其中閘極接觸間隙物貫穿第二層間介電層及第三層間介電層。上述方法更包含形成閘極接觸栓於閘極接觸開口內，其中閘極接觸栓被閘極接觸間隙物圍繞。
根據本發明一些實施例，提供一種裝置。上述裝置包含半導體基底及位於該半導體基底上的閘極電極。上述裝置包含位於該閘極電極的一側的源極/汲極區及位於源極/汲極區上的第一層間介電層，其中閘極電極的至少一部份位於第一層間介電層內。上述裝置包含位於第一層間介電層上的第二層間介電層及位於第二層間介電層上的第三層間介電層。上述裝置亦包含閘極接觸間隙物，其貫穿第二層間介電層及第三層間介電層。上述裝置更包含閘極接觸栓，其電性耦接至閘極電極，其中閘極接觸栓被閘極接觸間隙物圍繞。
2:晶圓
20:半導體基底
21:線
22:半導體鰭
26:界面氧化層
28:閘極介電層
30:閘極電極
32:閘極堆疊
34:硬遮罩
36:閘極間隙物
36A:層
36B:層
38:接觸蝕刻停止層
40:層間介電層
42:源極/汲極區
46:犧牲介電層
48:光阻
50:源極/汲極接觸開口
52:源極/汲極矽化物區
54:介電間隙物層
56:接觸間隙物
58:導電材料
60:源極/汲極接觸栓
62:蝕刻停止層
64:介電層
66:開口
68:介電間隙物層
70:接觸間隙物
72:導電材料
74:頂部源極/汲極接觸栓
76:蝕刻停止層
78:介電層
80:微影光罩
80A:底部層
80B:中間層
80C:頂部層
82:閘極接觸開口
84:微影光罩
86:源極/汲極接觸開口
88:介電間隙物層
90:接觸間隙物
92:接觸間隙物
94:導電材料
96:源極/汲極接觸栓
98:閘極接觸栓
102:蝕刻停止層
104:介電層
106:溝槽
108:金屬線
110:金屬線間隙物
112:蝕刻停止層
114:介電層
115:穿孔開口
116:介電層
118:穿孔
120:穿孔間隙物
200:流程圖
202-220:步驟
本揭露的各種樣態最好的理解方式為閱讀以下說明書的詳說明並配合所附圖式。應該注意的是，本揭露的各種不同特徵部件並未依據工業標準作業的尺寸而繪製。事實上，為使說明書能清楚敘述，各種不同特徵部件的尺寸可以任意放大或縮小。
第1至25圖係根據一些實施例，形成電晶體及位於其上的內連線結構之中間階段的剖面圖；第26圖係根據一些實施例，形成電晶體及位於其上的內連線結構之流程圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與 另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如”在...之下”、”下方”、”下部”、”上方”、”上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。例如，若翻轉圖式中的裝置，描述為位於其他元件或特徵部件”下方”或”在...之下”的元件，將定位為位於其他元件或特徵部件”上方”。因此，範例的用語”下方”可涵蓋上方及下方的方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
根據各種不同示例的實施例，提供了電晶體及位於其上的內連線結構，以及其形成方法。在一些實施例，繪示形成電晶體及位於其上的內連線結構的中間階段。一些實施例的一些變形例將詳述如下。在各種不同的實施例及圖式中，使用相似的標號來表示相似的元件。
第1至25圖係根據一些實施例，形成電晶體及位於其上的內連線結構之中間階段的剖面圖。第1至25圖所示的步驟也簡要地反映於第26圖所示的製程流程200。所繪示的實施例以形成一鰭式場效電晶體(Fin Field-Effect Transistor,FinFET)作為示例。可以理解的是，本發明一些實施例所示的結構及其形成方法可輕易地應用於平面電晶體及個別的接觸栓。
參閱第1圖，形成一起始結構於半導體基底20上，此結構為半導體晶圓2的一部份。根據本發明一些實施例，半導體基底20形成於矽結晶上。半導體基底20也可包含其他常用 的材料，例如碳、鍺、鎵、硼、砷、氮、銦、磷及/或類似的材料。半導體基底20也可為複合半導體基底，其包含III-V族複合半導體或矽鍺。
根據本發明一些實施例，此起始結構包含形成於半導體鰭22上的FinFET的一部份，其凸出於位於半導體鰭22兩側的淺溝槽隔離(Shallow Trench Isolation,STI)區(未繪示)的上表面。線21係用來表示STI區的上表面的水平，且半導體鰭22比線21高。
閘極堆疊32形成在半導體鰭22上，且具有部份延伸於半導體鰭22的上表面及側壁。根據本發明一些實施例，閘極堆疊32為替代閘極堆疊，其藉由形成虛置閘極堆疊(未繪示)，並以替代閘極堆疊取代虛置閘極堆疊來形成。閘極堆疊32可包含界面氧化層26，其接觸半導體鰭22的上表面及側壁，並包含閘極介電層28於界面氧化層26上，及閘極電極30於閘極介電層28上。硬遮罩34形成於閘極電極30上，以在後續多個製程中保護閘極堆疊32。硬遮罩34也可被視為閘極堆疊的一部份。界面氧化層26可藉由將半導體鰭22的表面層熱氧化而形成。閘極介電層28可由氧化矽、氮化矽、高介電常數介電材料(例如氧化鉿、氧化鑭、氧化鋁)、上述組合或上述多重層形成。閘極電極30可為金屬閘極，其包含例如鈷、鋁、氮化鈦、氮化鉭、鎢、氮化鎢、碳化鉭、氮化鉭或類似材料，且可包含多層不同的材料。取決於個別電晶體為P型金屬氧化物半導體(P-type Metal-Oxide-Semiconductor,PMOS)電晶體或N型金屬氧化物半導體(N-type Metal-Oxide-Semiconductor,NMOS)電 晶體，可選擇適合的閘極電極30材料，使個別的金屬氧化物半導體電晶體具有適合的功函數。
閘極間隙物36形成於閘極堆疊32和硬遮罩34的側壁上。根據本發明一些實施例，閘極間隙物36包含多重層，例如，層36A及層36B。雖然未繪示於圖式中，閘極間隙物36可包含更多層。閘極間隙物36的材料包含氧化矽、氮化矽、氮氧化矽、矽碳氮氧化物及/或類似材料。層36A及層36B可包含彼此不同的元素，例如，其中一者由氧化矽形成，另一者由氮化矽形成。或者，層36A及層36B包含相同元素(例如，矽及氮)但具有不同的組成(具有不同的比例)。在一些實施例，閘極間隙物36可與半導體鰭22的上表面及側壁接觸。
形成接觸蝕刻停止層(Contact Etch Stop Layer,CESL)38以覆蓋半導體基底20，且延伸於閘極間隙物36的側壁上。根據本發明一些實施例，接觸蝕刻停止層38由氮化矽、碳化矽或其他介電材料形成。層間介電層(Inter-Layer Dielectric,ILD)40形成於接觸蝕刻停止層38及閘極堆疊32上。由於ILD 40是多重ILD的最底層，因此在此將ILD 40稱為ILD0。ILD0 40可由氧化物形成，例如磷酸矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、硼摻雜磷酸矽酸鹽玻璃(Boron-doped Phospho-Silicate Glass,BPSG)、四乙氧基矽烷(Tetra Ethyl Ortho Silicate,TEOS)或類似材料。形成方法可包含，例如化學氣相沉積(Chemical Vapor Deposition,CVD)、可流動式化學氣相沉積(Flowable Chemical Vapor Deposition,FCVD)、旋轉塗佈或類似方法。可對硬遮罩層34、 閘極間隙物36、接觸蝕刻停止層38及ILD0 40執行平坦化，例如為化學機械研磨(Chemical Mechanical Polish,CMP)，使其彼此互為共平面。
形成源極及汲極區(在此之後稱為源極/汲極區)42，且至少源極/汲極區42的底部延伸至半導體基底20。根據本發明一些實施例，取決於個別電晶體為P型電晶體或N型電晶體，源極/汲極區42包含P型或N型摻雜質。當個別的電晶體為NMOS電晶體，源極/汲極區42可包含磷化矽，當個別的電晶體為PMOS電晶體，源極/汲極區42可包含矽鍺。形成源極/汲極區42可包含蝕刻半導體鰭22，以形成凹陷，並且在凹陷內磊晶成長源極/汲極區42。當欲形成P型電晶體時，可在磊晶區42內摻雜P型摻雜質，例如為硼或銦。當欲形成N型電晶體時，可在磊晶區42內摻雜N型摻雜質例如磷。執行磊晶及/或磊晶後植入時，P型或N型摻雜質可為原位(in-situ)摻雜。
第2-6圖繪示底部源極/汲極接觸栓的形成。根據本發明一些實施例，如第2圖所示，形成犧牲介電層46，其次形成光阻48的圖案。在本發明其他實施例，省略犧牲介電層46的形成。圖案化的光阻48可為單層層光阻，或為三層(其包含兩層光阻及一層介於兩層光阻間的無機層)。接下來，蝕刻犧牲介電層46、ILD0 40及接觸蝕刻停止層38以形成源極/汲極接觸開口50。之後形成源極/汲極矽化物區52，例如可藉由自我對準金屬矽化物製程來形成。之後移除光阻48。
可以理解的是，源極/汲極接觸開口50可藉由單一微影製程形成，或藉由兩個圖案化製程，其包含兩個微影製程， 其中使用第一微影光罩(未繪示)圖案化閘極堆疊32(又稱為替代閘極堆疊)左側的源極/汲極接觸開口50，使用第二微影光罩(未繪示)圖案化閘極堆疊32(又稱為替代閘極堆疊)右側的源極/汲極接觸開口50。
參閱第3圖，沉積介電間隙物層54。介電間隙物層54可由介電材料形成，例如SiN、SiCN、SiC、AlON、HfOx等。可使用共形沉積(conformal deposition)形成介電間隙物層54，例如原子層沉積(Atomic Layer Deposition,ALD)、化學氣相沉積(Chemical Vapor Deposition,CVD)或相似方法。因此，介電間隙物層54延伸至源極/汲極接觸開口50內，且介電間隙物層54的垂直部份的厚度大抵上與水平部份的厚度相等。
參閱第4圖，執行非等向性蝕刻以移除介電間隙物層54的水平部份，留下介電間隙物層54的垂直部份於源極/汲極接觸開口50內。在之後說明書的敘述中，將餘留的垂直部份稱為接觸間隙物56。個別的步驟以第26圖所示的製程流程圖的步驟202為代表。在晶圓2的上視圖，接觸間隙物56形成圍繞各個源極/汲極接觸開口50的環。接觸間隙物56的頂部的內側可為錐形，且可彎曲，其為具有向源極/汲極接觸開口50彎曲的內側。內側的底部可大抵上為筆直的。
接下來，如第5圖所示，將導電材料58填充至源極/汲極接觸開口50。導電材料的上表面比犧牲介電層46的上表面高。第6圖繪示平坦化製程，其中導電材料58中位於ILD0 40上的部份被移除。若有犧牲介電層46，則亦於平坦化製程中移除。導電材料58的餘留部份為源極/汲極接觸栓60。個別的 步驟以以第26圖所示的製程流程圖的步驟204為代表。根據本發明一些實施例，每一個源極/汲極接觸栓60包含導電阻障層，其由鈦、氮化鈦、鉭或氮化鉭金屬，例如鎢、鋁、銅或類似金屬於擴散阻障層上來形成。在本發明其他實施例，源極/汲極接觸栓60由同質材料的單一層形成，例如鎢或合金。在一些實施例，源極/汲極接觸栓60的上表面可與ILD0 40及硬遮罩34的上表面共平面。
第7-12圖繪示頂部源極/汲極接觸栓的形成。參閱第7圖，形成蝕刻停止層62後，形成ILD 64。在此說明書中，將ILD 64選擇性地稱為ILD1。蝕刻停止層62可由碳化矽、氮氧化矽、矽氮碳化物、上述組合或上述的複合層。蝕刻停止層62可由沉積方法形成，例如CVD、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)、ALD或類似的方法。ILD1 64包含的材料可選自於PSG、BSG、BPSG、氟摻雜磷玻璃(Fluorine-doped Silicon Glass,FSG)、TEOS或其他非孔洞低介電常數介電材料。ILD1 64可藉由旋轉塗佈、FCVD或類似方法形成，或者，使用其他沉積方法，例如CVD、PECVD、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition,LPCVD)或類似的方法形成。
第8圖繪示藉由蝕刻，形成開口66。接下來，參閱第9圖，藉由沉積形成大抵上為共形的介電間隙物層68，例如其水平部份與垂直部份的厚度差異小於10%。沉積可藉由ALD、CVD或類似方法形成。介電間隙物層68可由介電材料形成，其選自於SiN、SiON、SiCN、SiC、SiOCN、AlON、AlN、 HfOx、上述組合及/或上述多重層。
第10圖繪示以非等向性蝕刻來移除介電間隙物層68的水平部份，如第10圖所示，藉此形成接觸間隙物70。個別的步驟以第26圖所示的製程流程圖的步驟206為代表。由於將介電間隙物層68非等向性蝕刻(第9圖)，餘留的開口66可具有頂部寬度W1及底部寬度W2，其中W1/W2的比例可藉於約1.0至約2.0的範圍間。接觸間隙物70的內側的頂部可為錐形且可彎曲，其為具有向開口66彎曲的內側。接觸間隙物70的底部可具有大抵上為筆直且朝向開口66的邊緣。一樣地，在晶圓2的上視圖，接觸間隙物70形成圍繞各個接觸開口66的環。
接下來，如第11圖所示，將導電材料72填充至接觸開口66，然後執行平坦化製程(例如CMP)，其中導電材料72中位於ILD1 64之上的部份被移除。如第12圖所示，平坦化後，留下導電材料72的餘留部份，且將其稱為頂部源極/汲極接觸栓74。根據本發明一些實施例，在平坦化時，移除接觸間隙物70的錐狀頂部，且餘留的接觸間隙物70具有大抵上筆直且與頂部源極/汲極接觸栓74接觸的內側。個別的步驟以第26圖所示的製程流程圖的步驟208為代表。
在本發明其他實施例，平坦化後，接觸間隙物70的錐狀頂部具有餘留的部分(未繪示)，且餘留的接觸間隙物70的內側具有彎曲的頂部(如第12圖所示)，並且與頂部源極/汲極接觸栓74接觸。根據本發明一些實施例，頂部源極/汲極接觸栓74的材料與源極/汲極接觸栓60相似。例如，頂部源極/汲極接觸栓74可包含導電阻障層及金屬，例如鎢、鋁、銅或類似材 料於擴散阻障層上來形成。
第13-20圖繪示閘極接觸栓和額外的源極/汲極接觸栓之形成。根據本發明一些實施例，如第13圖所示，根據本發明一些實施例，形成蝕刻停止層76後，形成介電層78，在本說明書中，可將介電層78稱為ILD2 78。在本發明其他實施例，蝕刻停止層76並未形成，且介電層78與ILD1 64接觸。因此，以虛線來繪示蝕刻停止層76，代表可形成或可不形成蝕刻停止層76。根據本發明一些實施例，蝕刻停止層76及介電層78的材料個別選自於與蝕刻停止層62及層間介電層64的材料之相同的群組。在本發明其他實施例，介電層78由低介電常數介電材料形成，其可由含碳低介電常數介電材料、氫矽酸鹽(Hydrogen SilsesQuioxane,HSQ)、甲基矽酸鹽(MethylSilsesQuioxane,MSQ)或類似方法材料形成。
參閱第14圖，使用已圖案化的微影光罩80執行黃光微影製程來蝕刻介電層78、蝕刻停止層76、層間介電層64及蝕刻停止層62，以形成閘極接觸開口82。微影光罩80可包含由光阻形成的底部層80A、由無機材料形成的中間層80B及由另一個光阻形成的頂部層80C。之後移除硬遮罩34(第13圖)露出的部分，使得閘極接觸開口82延伸至位於閘極間隙物36之間的空間。個別的步驟以第26圖所示的製程流程圖的步驟210為代表。根據本發明一些實施例，閘極接觸開口82的形成包含一非等向性蝕刻。閘極間隙物36的側壁可由閘極接觸開口82露出。可選擇蝕刻劑，使其不蝕刻掉閘極間隙物36，因此露出的閘極間隙物36並未被蝕刻。在本發明其他實施例，閘極接觸開口82 比硬遮罩34窄，因此硬遮罩34的某些邊緣部份(未繪示)餘留在閘極接觸開口82的一側或兩側。雖然第14圖繪示了中間層80B及頂部層80C，事實上，形成閘極接觸開口82時，可消耗掉中間層80B及頂部層80C。移除餘留的微影光罩80後，結果晶圓2如第15圖所示。
參閱第16圖，形成另一個圖案化的微影光罩84，其延伸至閘極接觸開口82(第15圖)。個別的步驟以第26圖所示的製程流程圖的步驟212為代表。圖案化的微影光罩84可作為蝕刻遮罩來更進一步地蝕刻掉介電層78及蝕刻停止層76，藉此形成源極/汲極接觸開口86。源極/汲極接觸開口86露出接觸栓74及接觸間隙物70。相似地，形成源極/汲極接觸開口86時，可消耗掉微影光罩84的中間層及頂部層。接下來，移除餘留的微影光罩84，結果晶圓2如第17圖所示。
第18圖繪示形成介電間隙物層88，其延伸至閘極接觸開口82及源極/汲極接觸開口86。形成介電間隙物層88的方法和材料可個別與形成介電間隙物層68(第9圖)的方法和材料選自於相同的群組。例如，形成介電間隙物層88的材料包含SiN、SiON、SiCN、SiC、SiOCN、AlON、AlN及HfOx，且不限於此。介電間隙物層88亦可為共形或大抵上為共形。此外，介電間隙物層88延伸至閘極接觸開口82及源極/汲極接觸開口86兩者。
接下來，如第19圖所示，執行非等向性蝕刻，並且介電間隙物層88的餘留部份形成了接觸間隙物90及接觸間隙物92。個別的步驟以第26圖所示的製程流程圖的步驟214為 代表。接下來，沉積導電材料94以填入餘留的閘極接觸開口82及源極/汲極接觸開口86(第18圖)。如第20圖所示，之後執行平坦化製程，並且餘留的導電材料94形成了源極/汲極接觸栓96及閘極接觸栓98。個別的步驟以第26圖所示的製程流程圖的步驟216為代表。如第15-19圖所示，源極/汲極接觸栓96及閘極接觸栓98的形成個別包含利用雙重圖案化製程來形成閘極接觸開口82及源極/汲極接觸開口86(第17圖)，藉此使閘極接觸開口82與源極/汲極接觸開口86能緊密相鄰，而不引發鄰近效應(proximity effect)。另一方面，閘極接觸開口82與源極/汲極接觸開口86被同時填入以減少製造成本。
第20圖亦繪示源極/汲極接觸栓96及閘極接觸栓98的寬度，以及相鄰的源極/汲極接觸栓96與閘極接觸栓98之間的距離(空間)。源極/汲極接觸栓96具有寬度W3，且閘極接觸栓98具有寬度W3’。相鄰的源極/汲極接觸栓96及閘極接觸栓98之間的距離為S1。根據本發明一些實施例，S1/W3的比例及S2/W3’的比例藉於約1.0至約2.0的範圍間。
第21-25圖繪示底部金屬層(在此之後稱為第一金屬層或M1)的形成以及藉由單鑲嵌製程形成位於其上的穿孔。參閱第21圖，形成蝕刻停止層102及介電層104。根據本發明一些實施例，形成蝕刻停止層102的材料與形成蝕刻停止層76的材料選自於同一個群組，且介電層104可由低介電常數介電材料(介電常數小於3.8介電)形成。例如，低介電常數介電層104可由含碳的低介電常數介電材料、HSQ、MSQ或類似材料來形成。
第22圖繪示形成溝槽106，其中形成溝槽106包含蝕刻低介電常數介電層104及蝕刻停止層102，藉此露出源極/汲極接觸栓96及閘極接觸栓98。接下來，如第23圖所示，形成金屬線108及金屬線間隙物110。個別的步驟以第26圖所示的製程流程圖的步驟218為代表。此形成製程可個別與接觸間隙物70及頂部源極/汲極接觸栓74的形成相似，並且上述形成製程在此不再重複敘述。形成金屬線間隙物110的介電材料與形成接觸間隙物70的材料可選自於同一個群組。金屬線108可包含導電擴散阻障層及位於導電擴散阻障層上的含銅之金屬材料。
接下來，經由鑲嵌製程形成穿孔於金屬線108上。參閱第23圖，形成蝕刻停止層112及介電層114。根據本發明一些實施例，形成蝕刻停止層112的材料與形成蝕刻停止層76及蝕刻停止層102的材料選自於同一個群組，且介電層114可由低介電常數介電材料形成，其材料可與低介電常數介電層104的材料相似。第24圖繪示形成穿孔開口115及介電層116，介電層116為共形層或大抵上為共形層，其藉由使用ALD、CVD或類似方法形成。介電層116延伸至穿孔開口115。
第25圖繪示形成穿孔118及穿孔間隙物120。個別的步驟以第26圖所示的製程流程圖的步驟220為代表。上述形成製程可個別與接觸間隙物70及頂部源極/汲極接觸栓74相似，並且形成製程的細節在此不再重複敘述。穿孔間隙物120可由介電材料形成，其材料與形成接觸間隙物70的材料選自於同一個群組。穿孔118可包含導電擴散阻障層與個別形成於導電擴散阻障層上的含銅之金屬材料。接下來的製程，可重複形 成金屬線108、金屬線間隙物110、穿孔118及穿孔間隙物120的製程，以形成位於其上方的金屬線(例如M2、M3、M4至Mtop)及穿孔。位於上方的金屬線及穿孔可藉由單鑲嵌製程(如第21-25圖所示)或雙鑲嵌製程形成，其在將穿孔及金屬線個別填入穿孔開口及溝槽前，沉積並非等向性蝕刻介電層。
本發明一些實施例具有一些有益的部件。如果發生了重疊量偏移(overlay shift)，藉由形成接觸間隙物、金屬線間隙物及/或穿孔間隙物，可使其具有額外的介電間隙物來防止下方導電部件至上方導電部件的電性短路。因此提升了製程寬裕度。
根據本發明一些實施例，提供一種方法。上述方法包含形成底部源極/汲極接觸栓於底部層間介電層內，其中底部源極/汲極接觸栓電性耦接至電晶體的源極/汲極區。上述方法包含形成第一層間介電層於底部源極/汲極接觸栓上以及形成第一源極/汲極接觸開口於第一層間介電層內，並且第一源極/汲極接觸開口露出底部源極/汲極接觸栓。上述方法包含形成第一介電間隙物層，其中第一介電間隙物層包含延伸至第一源極/汲極接觸開口的第一部份，以及位於第一層間介電層上的第二部份。上述方法亦包含對第一介電間隙物層執行非等向性蝕刻，其中第一介電間隙物層的餘留垂直部份形成第一源極/汲極接觸間隙物。上述方法更包含填充第一源極/汲極接觸開口的餘留部份，以形成第一源極/汲極接觸栓。
根據本發明一些實施例，提供一種方法。上述方法包含形成第一源極/汲極接觸栓於第一層間介電層內，其中 第一源極/汲極接觸栓電性耦接至電晶體的源極/汲極區。上述方法包含形成第二層間介電層於第一層間介電層上及形成第二源極/汲極接觸栓於第二層間介電層內。上述方法包含形成第三層間介電層於第二層間介電層上及蝕刻第二層間介電層及第三層間介電層以形成閘極接觸開口，其中閘極接觸開口露出電晶體的閘極電極。上述方法亦包含形成閘極接觸間隙物於閘極接觸開口內，其中閘極接觸間隙物貫穿第二層間介電層及第三層間介電層。上述方法更包含形成閘極接觸栓於閘極接觸開口內，其中閘極接觸栓被閘極接觸間隙物圍繞。
根據本發明一些實施例，提供一種裝置。上述裝置包含半導體基底及位於該半導體基底上的閘極電極。上述裝置包含位於該閘極電極的一側的源極/汲極區及位於源極/汲極區上的第一層間介電層，其中閘極電極的至少一部份位於第一層間介電層內。上述裝置包含位於第一層間介電層上的第二層間介電層及位於第二層間介電層上的第三層間介電層。上述裝置亦包含閘極接觸間隙物，其貫穿第二層間介電層及第三層間介電層。上述裝置更包含閘極接觸栓，其電性耦接至閘極電極，其中閘極接觸栓被閘極接觸間隙物圍繞。
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解本揭示的概念。所屬技術領域中具有通常知識者能夠理解，其可利用本發明揭示內容作為基礎，以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解，不脫離本揭示之精神和範圍的等效 構造可在不脫離本揭示之精神和範圍內作各種之更動、替代與潤飾。
2‧‧‧晶圓
20‧‧‧半導體基底
21‧‧‧線
22‧‧‧半導體鰭
26‧‧‧界面氧化層
28‧‧‧閘極介電層
30‧‧‧閘極電極
32‧‧‧閘極堆疊
36‧‧‧閘極間隙物
36A‧‧‧層
36B‧‧‧層
38‧‧‧接觸蝕刻停止層
40‧‧‧層間介電層
42‧‧‧源極/汲極區
52‧‧‧源極/汲極矽化物區
56‧‧‧接觸間隙物
60‧‧‧源極/汲極接觸栓
62‧‧‧蝕刻停止層
64‧‧‧介電層
70‧‧‧接觸間隙物
74‧‧‧頂部源極/汲極接觸栓
76‧‧‧蝕刻停止層
78‧‧‧介電層
90‧‧‧接觸間隙物
92‧‧‧接觸間隙物
96‧‧‧源極/汲極接觸栓
98‧‧‧閘極接觸栓
102‧‧‧蝕刻停止層
104‧‧‧介電層
108‧‧‧金屬線
110‧‧‧金屬線間隙物
112‧‧‧蝕刻停止層
114‧‧‧介電層
118‧‧‧穿孔
120‧‧‧穿孔間隙物

Claims (13)

  1. 一種半導體裝置的製造方法，包括：形成一第一層間介電層於一電晶體的一源極/汲極區上；形成一第一源極/汲極接觸開口於該第一層間介電層內；形成一第一源極/汲極接觸間隙物於該第一源極/汲極接觸開口內；填充該第一源極/汲極接觸開口的一餘留部份，以形成一第一源極/汲極接觸栓，該第一源極/汲極接觸栓電性耦接至該源極/汲極區；形成一第二層間介電質於該第一層間介電質上；形成一第二源極/汲極接觸栓於該第二層間介電質內，其中該第二源極/汲極接觸栓位於該第一源極/汲極接觸栓之上且接觸該第一源極/汲極接觸栓；形成一第三層間介電質於該第二層間介電質上；蝕刻該第二層間介電質和該第三層間介電質以形成一閘極接觸開口，其中該閘極接觸開口露出該電晶體的一閘極電極；蝕刻該第三層間介電質，其中形成一第二源極/汲極接觸開口以露出該第二源極/汲極接觸栓；同時形成一閘極接觸間隙物和一源極/汲極接觸間隙物分別延伸至該閘極接觸開口和該第二源極/汲極接觸開口內；以及同時填充該閘極接觸開口和該第二源極/汲極接觸開口的剩餘部分以分別形成一閘極接觸栓和一第三源極/汲極接觸 栓。
  2. 如申請專利範圍第1項所述之方法，更包括：形成一第一蝕刻停止層於該電晶體的一閘極間隙物及該第一源極/汲極接觸栓上，並且與其接觸，其中該第二層間介電層位於該第一蝕刻停止層上，並且與其接觸。
  3. 如申請專利範圍第2項所述之方法，其中該閘極接觸間隙物的邊界接觸該閘極間隙物的邊界以形成一垂直界面。
  4. 如申請專利範圍第1項所述之方法，更包括：以一圖案化的光阻填充該閘極接觸開口；使用該圖案化的光阻作為蝕刻遮罩以蝕刻該第三層間介電質，其中形成該第二源極/汲極接觸開口以露出該第二源極/汲極接觸栓；以及在形成該閘極接觸栓和該第三源極/汲極接觸栓之前，移除該圖案化的光阻。
  5. 如申請專利範圍第1項所述之方法，更包括：形成一第一低介電常數介電層於該第一層間介電層上；形成一金屬線於該第一低介電常數介電層內，其中該金屬線電性耦接至該源極/汲極區；以及形成圍繞該金屬線的一介電金屬線間隙物。
  6. 如申請專利範圍第5項所述之方法，更包括：形成一第二低介電常數介電層於該第一低介電常數介電層上；形成一金屬穿孔於該第二低介電常數介電層內，其中該金屬穿孔電性耦接至該源極/汲極區；以及 形成圍繞該金屬穿孔的一介電穿孔間隙物。
  7. 如申請專利範圍第1項所述之方法，更包括：形成一犧牲層於該電晶體的一閘極堆疊上；蝕刻該犧牲層及該第一層間介電層，以形成該第一源極/汲極接觸開口延伸至該犧牲層中，其中形成該第一源極/汲極接觸間隙物和該第一源極/汲極接觸栓於該第一源極/汲極接觸開口中且延伸至該犧牲層中；以及執行一平坦化製程以移除位於該底部層間介電層上的該犧牲層及位於該犧牲層中的該第一源極/汲極接觸間隙物的一部份和該第一源極/汲極接觸栓的一部份。
  8. 一種半導體裝置的製造方法，包括：形成一第一源極/汲極接觸栓於一第一層間介電層內，其中該第一源極/汲極接觸栓電性耦接至一電晶體的一源極/汲極區；形成一第二層間介電層於該第一層間介電層上；形成一第二源極/汲極接觸栓於該第二層間介電層內；形成一第三層間介電層於該第二層間介電層上；蝕刻該第二層間介電層及該第三層間介電層以形成一閘極接觸開口，其中該閘極接觸開口露出該電晶體的一閘極電極；以一微影光罩填充該閘極接觸開口；使用該微影光罩作為蝕刻遮罩蝕刻該第三層間介電層，以形成一源極/汲極接觸開口；從該閘極接觸開口中移除該微影光罩；以及 形成一閘極接觸栓於該閘極接觸開口內，其中該閘極接觸栓被該閘極接觸間隙物圍繞。
  9. 如申請專利範圍第8項所述之方法，更包括：該源極/汲極接觸開口露出該第二源極/汲極接觸栓；形成一源極/汲極接觸間隙物於該源極/汲極接觸開口內；以及形成一第三源極/汲極接觸栓於該源極/汲極接觸開口內，其中該第三源極/汲極接觸栓被該源極/汲極接觸間隙物圍繞。
  10. 如申請專利範圍第8項所述之方法，其中該形成該閘極接觸間隙物包括：沉積延伸至該閘極接觸開口，並且貫穿該第二層間介電層及該第三層間介電層的一介電間隙物層；以及對該介電間隙物層執行一非等向性蝕刻，其中該介電間隙物層的一餘留部份形成該閘極接觸間隙物。
  11. 一種半導體裝置，包括：一半導體基底；一閘極電極，位於該半導體基底上；一源極/汲極區，位於該閘極電極的一側；一第一層間介電層，位於該源極/汲極區上，其中該閘極電極的至少一部份位於該第一層間介電層內；一第二層間介電層，位於該第一層間介電層上；一第三層間介電層，位於該第二層間介電層上；一閘極接觸間隙物，貫穿該第二層間介電層及該第三層間介電層，且該閘極接觸間隙物包括一介電材料； 複數個閘極間隙物，位於該閘極電極的兩側，其中該閘極接觸間隙物的邊界接觸該些閘極間隙物的邊界以形成一垂直界面；以及一閘極接觸栓，電性耦接至該閘極電極，其中該閘極接觸栓被該閘極接觸間隙物圍繞。
  12. 如申請專利範圍第11項所述之半導體裝置，更包括：一第一源極/汲極接觸栓，位於該第一層間介電層內；一第二源極/汲極接觸栓，位於該第二層間介電層內，且在該第一源極/汲極接觸栓與該第二源極/汲極接觸栓之間具有一可區別的界面；以及一源極/汲極接觸間隙物，位於該第二層間介電層內，且圍繞該第二源極/汲極接觸栓。
  13. 如申請專利範圍第11項所述之半導體裝置，更包括：一低介電常數介電層，位於該第三層間介電層上；一金屬線，位於該低介電常數介電層內，其中該金屬線電性耦接至該源極/汲極區；以及一介電金屬線間隙物，圍繞該金屬線。
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