TWI792234B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI792234B
TWI792234B TW110110198A TW110110198A TWI792234B TW I792234 B TWI792234 B TW I792234B TW 110110198 A TW110110198 A TW 110110198A TW 110110198 A TW110110198 A TW 110110198A TW I792234 B TWI792234 B TW I792234B
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Taiwan
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source
contact
sidewall
dielectric layer
gate structure
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TW110110198A
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TW202205396A (zh
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游力蓁
黃麟淯
莊正吉
林佑明
王志豪
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台灣積體電路製造股份有限公司
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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Abstract

半導體結構包含形成於半導體基底上方的金屬閘極結構、形成金屬閘極結構的第一側壁上的第一閘極間隙壁、形成於與第一側壁相對的金屬閘極結構的第二側壁上的第二閘極間隙壁，其中第二閘極間隙壁比第一閘極間隙壁更短；設置與金屬閘極結構相鄰的源極/汲極接點，其中源極/汲極接點的側壁由第二閘極間隙壁定義；以及被配置為將金屬閘極結構電性連接至源極/汲極接點的接點部件。

Description

半導體結構及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體結構及其形成方法。
積體電路(integrated circuit，IC)產業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸(即製造過程中所產生的最小的組件或線路)縮小。此元件尺寸微縮化的製程提供增加生產效率與降低相關費用的益處。此元件尺寸微縮化也增加了加工和製造積體電路的複雜性。
舉例來說，在記憶體裝置(例如靜態隨機存取記憶體(static random-access memory，SRAM)裝置)中，隨著部件尺寸不斷縮小，對接接點(butted contact)和互連部件的製造變得更具挑戰性。在較小的長度尺寸下，可改變對接接點的配置，以改善金屬閘極結構與相鄰源極/汲極接點之間的連接。此外，在對接接點上方形成互連部件可受益於擴大的接觸面積，以降低接觸電阻並改善裝置密度。至少基於這些原因，期望改善對接接點和互連部件的製造。
在一些實施例中，提供半導體結構，半導體結構包含金屬閘極結構，設置於半導體基底上方；第一閘極間隙壁，設置於金屬閘極結構的第一側壁上；第二閘極間隙壁，設置於與第一側壁相對的金屬閘極結構的第二側壁上，其中第二閘極間隙壁比第一閘極間隙壁更短；源極/汲極接點，設置與金屬閘極結構相鄰，其中源極/汲極接點的側壁由第二閘極間隙壁定義；以及接點部件，將金屬閘極結構電性連接至源極/汲極接點。
在一些其他實施例中，提供半導體結構，半導體結構包含金屬閘極結構，設置於半導體基底上方；源極/汲極部件，設置與金屬閘極結構相鄰；源極/汲極接點，設置於源極/汲極部件上方；以及導電部件，接觸金屬閘極結構和源極/汲極接點，其中導電部件的底部埋置於金屬閘極結構的側壁與源極/汲極接點的側壁之間。
在另外一些實施例中，提供半導體結構的形成方法，此方法包含形成半導體裝置，半導體裝置包含設置於半導體層上方的金屬閘極結構、設置於金屬閘極結構的側壁上的閘極間隙壁及設置於半導體層中與金屬閘極結構相鄰的源極/汲極部件；在源極/汲極部件上方形成源極/汲極接點，其中閘極間隙壁將源極/汲極接點與金屬閘極結構隔開；在金屬閘極結構和源極/汲極接點上方形成層間介電層；形成開口，以暴露出金屬閘極結構、源極/汲極接點和閘極間隙壁；移除暴露於開口中的閘極間隙壁的頂部；在閘極間隙壁的剩下部分上方形成金屬層；以及將金屬層平坦化，以形成接點部件，使得接點部件將金屬閘極結構電性耦接至源極/汲極接點。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，為了方便描述本發明實施例的一部件與另一部件的關係，可使用空間相關用語，例如“下部”、“上部”、“水平”、“垂直”、“在…之上”、“上方”、“在…之下”、“下方”、“上”、“下”、“頂部”、“底部”等及前述的衍生用語(例如“水平地”、“向下地”、“向上地”等)。空間相關用語用以涵蓋包含部件的裝置的不同方位。
再者，當用“大約”、“近似”及類似術語描述數字或數字範圍時，此術語目的在涵蓋在所描述的數字的合理範圍，合理範圍包含例如所描述數字的+/-10％之內，或本發明所屬技術領域中具通常知識者可理解的其他數值。舉例來說，術語“約5nm”涵蓋了4.5nm至5.5nm的尺寸範圍。再者，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
本發明實施例一般為有關於半導體裝置，且特別為有關於場效電晶體(field-effect transistors，FETs)(例如平面場效電晶體)、三維鰭式場效電晶體(fin-like FETs，FinFETs)、全繞式閘極(gate-all-around，GAA)場效電晶體或前述之組合。本發明一些實施例可針對積體電路中的記憶體裝置，例如靜態隨機存取記憶體裝置。
在場效電晶體製造中，對接接點被配置來將金屬閘極結構(例如高介電常數金屬閘極(high-k metal gate，HKMG)結構)電性耦接至源極/汲極(source/drain，S/D)接點。為了確保裝置效能，將在對接接點上方的後續形成的互連部件(例如導線)設計為與對接接點隔離，以避免兩部件之間的電性短路，從平面俯視圖來看，這可能限制互連部件的一個或多個尺寸。雖然製造對接接點和互連部件的現有方法一般來說已經足夠，但是這些方法並非在所有方面完全令人滿意。在一範例中，需要縮對接接點的尺寸，以避免短路可能損壞金屬閘極結構與源極/汲極接點之間的連接。在另一範例中，在小的長度尺寸下，容納對接接點與形成於對接接點上方的互連部件之間的隔開距離可變得具有挑戰性。在另一範例中，具有縮小尺寸的互連部件可能不經意地增加了這些部件的接觸電阻，且不必要地限制了裝置的效能。
第1圖顯示依據本發明實施例各方面之形成半導體裝置200的方法100。方法100僅為範例，且不意圖將本發明實施例限制於請求項明確顯示的內容之外。可在方法100之前、期間及之後提供額外的操作，且對於此方法的其他實施例，可取代、消除或移動所描述的一些操作。以下結合沿第2A-17B圖描述方法100，第2A-17B圖顯示在方法100的中間步驟期間，半導體裝置200的一部分，其中第2A圖為半導體裝置200的三維透視圖，第2B、17A和17B圖為第2A圖中顯示的半導體裝置200的平面俯視圖，第3-12B圖為沿第2A、2B、17A及/或17B圖顯示的虛線LL’截取的半導體裝置200的剖面示意圖，且第13A-16G圖為第2A、2B、17A及/或17B圖顯示的虛線MM’截取的半導體裝置200的剖面示意圖。
半導體裝置200可為在積體電路或積體電路的一部分加工期間的中間裝置，積體電路可包括靜態隨機存取記憶體(SRAM)及/或邏輯電路、被動組件(電阻、電容和電感)、主動組件(例如p型場效電晶體(p-type FETs，PFETs)、n型場效電晶體(n-type FETs，NFETs)、鰭式場效電晶體、全繞式閘極場效電晶體、金屬氧化物半導體場效電晶體(metal-oxide-semiconductor FETs，MOSFETs)、互補式金屬氧化物半導體(complementary MOS，CMOS)電晶體、雙極性電晶體、高壓電晶體、高頻電晶體及/或其他記憶單元)。本發明實施例不限定於任何特定數量的裝置或裝置區，也不限定於任何特定的裝置配置。舉例來說，雖然顯示的半導體裝置200為三維鰭式場效電晶體裝置，但是本揭露也可提供用於製造平面場效電晶體裝置的實施例。
在操作102，請參照第2A、2B和3圖，方法100提供半導體裝置200，半導體裝置200包含基底202，基底202具有設置於其上方的三維主動區(之後也被稱為鰭204)。半導體裝置200更包含設置於鰭204上方的高介電常數金屬閘極(HKMG)結構210、設置於高介電常數金屬閘極結構210的側壁上的閘極間隙壁212、設置於每個鰭204中或每個鰭204上方的源極/汲極部件214、設置於基底202上方將半導體裝置200的各種組件隔開的隔離結構208以及設置於隔離結構208和源極/汲極部件214上方的層間介電(interlayer dielectric，ILD)層218。應當注意的是，雖然第2A圖的三維透視圖中顯示兩個高介電常數金屬閘極結構210，但是半導體裝置200中可存在額外的高介電常數金屬閘極結構210，如第2B-17B圖所示。
基底202可包含元素(單一元素)半導體(例如矽、鍺及/或其他合適的材料)、化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦及/或其他合適的材料)、合金半導體(例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP)及/或其他合適的材料。基底202可為具有一致組成的單一層材料。或鍺，基底202可包含具有適用於積體電路裝置製造的相似或不同組成的多個材料層。在一範例中，基底202可為絕緣層上覆矽(silicon-on-insulator，SOI)基底，絕緣層上覆矽基底具有形成於氧化矽層上的矽層。在另一範例中，基底202可包含導電層、半導體層、介電層、其他層或前述之組合。
在基底202包含場效電晶體的一些實施例中，各種摻雜區可形成於基底202中或基底202上。取決於設計需求，摻雜區可摻雜n型摻雜物(例如磷、砷)及/或p型摻雜物(例如硼或BF2 )。摻雜區可直接形成於基底202上、p型井結構中、n型井結構中、雙井結構中或使用凸起結構。摻雜區可透過佈植摻雜物原子、原位摻雜磊晶成長、其他合適的技術或前述之組合形成。
請參照第2A、2B和3圖，鰭204可適用於形成p型或n型鰭式場效電晶體。鰭204可透過使用合適的製程(包含光微影和蝕刻製程)製造。光微影製程可包含在基底202上方形成光阻層(阻劑)、將光阻在圖案下曝光、進行曝光後烘烤製程以及將光阻顯影，以形成包含光阻的遮罩元件(未顯示)。接著，使用遮罩元件以在基底202中蝕刻凹口，在基底202上留下鰭204。蝕刻製程包含乾蝕刻製程、濕蝕刻製程、反應性離子蝕刻(reactive ion etching，RIE)、其他合適的製程或前述之組合。
用於形成鰭204的許多其他方法的實施例可能為合適的。舉例來說，鰭204可透過使用雙重圖案化或多重圖案化製程來圖案化。一般來說，雙重圖案化或多重圖案化製程結合了光微影和自對準製程，以創造具有較小間距的圖案，舉例來說，此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說，在一實施例中，犧牲層形成於基底上方並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著，移除犧牲層，且可接著使用剩下的間隔物或心軸將鰭204圖案化。
隔離結構208可包含氧化矽、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluoride-doped silicate glass，FSG)、低介電常數介電材料、其他合適的材料或前述之組合。隔離結構208可包含淺溝槽隔離(shallow trench isolation，STI)部件。在一實施例中，隔離結構208透過在形成鰭204期間在基底202中蝕刻溝槽來形成。接著，透過沉積製程以上述的隔離材料填充溝槽，接著進行化學機械平坦化/研磨(chemical mechanical planarization/polishing，CMP)製程。可使用其他隔離結構208例如場氧化物、矽局部氧化(local oxidation of silicon，LOCOS)及/或其他合適的結構作為隔離結構208。或者，隔離結構208可包含多層結構，例如具有一個或多個熱氧化襯墊層。隔離結構208可透過任何合適的方法沉積，例如化學氣相沉積(chemical vapor deposition，CVD)、可流動化學氣相沉積(flowable CVD，FCVD)、旋塗玻璃(spin-on-glass，SOG)、其他合適的方法或前述之組合。
請參照第2A圖，半導體裝置200包含設置於鰭204上方且與高介電常數金屬閘極結構210相鄰的源極/汲極部件214。源極/汲極部件214可透過任何合適的技術形成，例如蝕刻製程以及之後的一個或多個磊晶製程。在一範例中，進行一個或多個蝕刻製程，以移除鰭204的一部分，以分別在鰭204中形成凹口(未顯示)。可使用氫氟酸(HF)溶液及/或其他合適的溶液進行清潔製程，以清潔凹口。之後，進行一個或多個磊晶成長製程，以在凹口中成長磊晶部件。每個源極/汲極部件214可適用於p型鰭式場效電晶體裝置(例如p型磊晶材料)或n型鰭式場效電晶體裝置(例如n型磊晶材料)。p型磊晶材料可包含摻雜p型摻雜物的矽鍺的一個或多個磊晶層(epi SiGe)，p型摻雜物例如硼、鎵、銦及/或其他p型摻雜物。n型磊晶材料可包含摻雜n型摻雜物的矽的一個或多個磊晶層(epi Si)，n型摻雜物例如砷、磷及/或其他n型摻雜物。
請參照第2A、2B和3圖，半導體裝置200更包含設置於鰭204的一部分上方的至少一個高介電常數金屬閘極結構210，使得每個高介電常數金屬閘極結構210設置於每個鰭204中的源極/汲極部件214之間。高介電常數金屬閘極結構210可包含設置於鰭204上方的高介電常數介電層(即具有介電常數大於氧化矽的介電常數，未顯示)以及設置於高介電常數介電層上方的金屬閘極電極(未顯示)。雖然位在圖式中顯示，但是金屬閘極電極可更包含至少一個功函數金屬層以及設置於功函數金屬層上方的塊狀導電層。功函數金屬層可為p型或n型功函數金屬層。範例的功函數材料包含TiN、TaN、ZrSi2 、MoSi2 、TaSi2 、NiSi2 、Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Ru、Mo、Al、WN、Mn、Zr、其他合適的功函數材料或前述之組合。塊狀導電層可包含Cu、W、Ru、Al、Co、其他合適的材料或前述之組合。高介電常數金屬閘極結構210可更包含其他層(未顯示)，例如設置於鰭204與高介電常數介電層之間的界面層、硬遮罩層、蓋層、阻障層、晶種層、其他合適層或前述之組合。高介電常數金屬閘極結構210的各種層可透過任何合適的方法沉積，例如化學氧化、熱氧化、原子層沉積(atomic layer deposition，ALD)、化學氣相沉積、物理氣相沉積(physical vapor deposition，PVD)、電鍍、其他合適的方法或前述之組合。可進行研磨製程(例如化學機械研磨)，以移除高介電常數金屬閘極結構210的頂表面上的多餘材料，以將半導體裝置200平坦化。
半導體裝置200更包含設置於每個高介電常數金屬閘極結構210的側壁上的閘極間隙壁212。閘極間隙壁212可為單一層結構或多層結構。閘極間隙壁212可包含氧化鋁、氮氧化鋁、氧化鉿、氧化鈦、氧化鋯鋁、氧化鋅、氧化鉭、氧化鑭、氧化釔、氮碳氧化矽、氮碳化鉭、氮化矽、氮化鋯、氮碳化矽、氧化矽、碳氧化矽、矽化鉿、矽、矽化鋯、其他合適的材料或前述之組合。應當注意的是，閘極間隙壁212的組成與周圍介電組件的組成不同，使得在後續蝕刻製程期間，閘極間隙壁212與周圍介電組件之間具有蝕刻選擇性。可透過先在半導體裝置200上方毯覆式沉積間隙壁材料，接著進行非等向性蝕刻製程移除間隙壁材料的一部分，以在高介電常數金屬閘極結構210的側壁上形成閘極間隙壁212。
在一些實施例中，高介電常數金屬閘極結構210在製造半導體裝置200的其他組件(例如源極/汲極部件214)之後形成。此製程一般被稱為閘極取代製程，閘極取代製程包含形成虛設閘極結構(未顯示)作為每個高介電常數金屬閘極結構210的佔位物，形成與虛設閘極結構相鄰的源極/汲極部件214，在虛設閘極結構和源極/汲極部件214上方形成層間介電層218，透過例如化學機械研磨將層間介電層218平坦化，以暴露出虛設閘極結構的頂表面，移除層間介電層218中的虛設閘極結構，以形成暴露出鰭204的通道區的閘極溝槽(未顯示)，以及在閘極溝槽中形成高介電常數金屬閘極結構210，以完成閘極取代製程。在一些實施例中，層間介電層218包含介電材料，例如四乙氧基矽烷(tetraethoxysilane，TEOS)、氧化矽、摻雜的氧化矽(例如硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、氟摻雜矽酸鹽玻璃(fluoride-doped silicate glass，FSG)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼摻雜矽酸鹽玻璃(boron doped silicon glass，BSG))其他合適的介電材料或前述之組合。層間介電層218可包含多層結構，這些結構具有多個介電材料，且可透過沉積製程形成，例如化學氣相沉積、可流動化學氣相沉積、旋塗玻璃、其他合適的方法或前述之組合。
請參照第4和5圖，方法100的操作104，在高介電常數金屬閘極結構210上方形成介電層232。請參照第4圖，方法100先移除高介電常數金屬閘極結構210的一部分，以形成溝槽230。在一些實施例中，方法100進行蝕刻製程(例如乾蝕刻製程)，以形成溝槽230。蝕刻製程相對於層間介電層218選擇性移除高介電常數金屬閘極結構210，因此不蝕刻層間介電層218或僅最小程度蝕刻層間介電層218。請參照第5圖，方法100接著在溝槽230中形成介電層232。在目前的實施例中，方法100透過合適的方法沉積介電材料，例如化學氣相沉積、可流動化學氣相沉積、原子層沉積、物理氣相沉積、其他合適的方法或前述之組合。介電層232可包含氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氮化鋯鋁、氧化鉿、其他合適的材料或前述之組合。之後，使用合適的方法(例如化學機械研磨)將半導體裝置200的頂表面平坦化，以暴露出層間介電層218的頂表面。在一些實施例中，如第5圖所示，化學機械研磨製程使得介電層232的頂表面與層間介電層218的頂表面和閘極間隙壁212大致共平面。在一些實施例中，介電層232和之後形成的介電層242為選擇性的，且可在半導體裝置200中省略。
請參照第6和7圖，方法100的操作104，在源極/汲極部件214上方形成源極/汲極接點220。請參照第6圖，方法100移除層間介電層218設置於源極/汲極部件214上方的部分，以形成溝槽234。方法100可使用任何合適的蝕刻製程(例如乾蝕刻製程、濕蝕刻製程、反應性離子蝕刻等)來形成溝槽234。在一些實施例中，蝕刻製程為使用一個或多個電漿的乾蝕刻製程，電漿例如C4 F6 、氧氣、氫氣、其他合適的氣體或前述之組合。請參照第7圖，方法100接著在溝槽234中以及介電層232的一部分上方沉積導電材料。導電材料可包含Co、W、Ru、Cu、Ta、Ti、Mo、Ni、其他合適的材料或前述之組合。導電材料可透過任何合適的方法沉積，例如化學氣相沉積、物理氣相沉積、原子層沉積、電鍍、其他合適的方法或前述之組合。在一些實施例中，在沉積導電材料之前，在溝槽234中形成阻障層(未顯示)。阻障層可包含TiN、TaN、其他合適的材料或前述之組合，且可透過例如原子層沉積製程來沉積。之後，請參照第7圖，方法100使用合適的方法(例如化學機械研磨)將導電材料平坦化，以在源極/汲極部件214上方形成源極/汲極接點220。在一些實施例中，導電材料形成於介電層232上方的部分透過化學機械研磨製程移除，使得源極/汲極接點220的頂表面與介電層232的頂表面大致共平面。
請參照第8和9圖，方法100在介電層232和高介電常數金屬閘極結構210上方形成介電層242。在一些實施例中，請參照第8圖，方法100先移除源極/汲極接點220的一部分，以形成溝槽240，溝槽240設置於閘極間隙壁212之間。方法100可使用任何合適的蝕刻製程(例如乾蝕刻製程、濕蝕刻製程、反應性離子蝕刻等)來形成溝槽240。在本發明實施例中，蝕刻製程為使用酸的混合物作為蝕刻劑的濕蝕刻製程，例如硫酸(H2 SO4 )。在一些實施例中，濕蝕刻製程透過蝕刻製程的持續時間來控制。請參照第9圖，方法100接著使用任何合適的方法，例如化學氣相沉積、可流動化學氣相沉積、原子層沉積、物理氣相沉積、其他合適的方法或前述之組合，在溝槽240中和介電層232的一部分上方沉積介電層242。介電層242可包含氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氮化鋯鋁、氧化鉿、其他合適的材料或前述之組合。應當注意的是，介電層242的組成與介電層232的組成不同，使得當以下將詳細討論的後續蝕刻製程時，介電層之間具有蝕刻選擇性。之後，請參照第9圖，方法100將半導體裝置200的頂表面平坦化，以暴露出介電層232和閘極間隙壁212，使得介電層242的頂表面與介電層232的頂表面大致共平面。
請參照第10圖，方法100的操作106，在半導體裝置200上方形成蝕刻停止層246，且之後在蝕刻停止層246上方形成層間介電層250(也可被稱為金屬間介電(intermetal dielectric，IMD)層)。蝕刻停止層246可包含氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氮化鋯鋁、氧化鉿、其他合適的材料或前述之組合。方法100透過使用任何合適的方法沉積蝕刻停止層246，例如化學氣相沉積、原子層沉積、其他合適的方法或前述之組合。層間介電層250可相似於層間介電層218，且可透過以上參考層間介電層218的相似方式形成。之後，方法100可繼續，以形成在層間介電層250上方的互連結構，互連結構包含垂直互連部件(之後被稱為導通孔)，垂直互連部件被配置來將高介電常數金屬閘極結構210和源極/汲極接點220與額外的互連部件互連，額外的互連部件例如水平互連部件(之後被稱為導線)及/或被配置來連接相同電晶體的高介電常數金屬閘極結構210和源極/汲極接點220的對接接點(butted contact，BCT)。
請參照第1圖，包含操作108-114的路徑A一般描述形成用於將高介電常數金屬閘極結構210和源極/汲極接點220互連的導通孔，且包含操作116-124的路徑B一般描述形成連接相同電晶體(例如記憶體裝置)的高介電常數金屬閘極結構210和源極/汲極接點220的對接接點。在本發明實施例中，將參考半導體裝置200沿線LL’的剖面示意圖討論路徑A，且將參考半導體裝置200沿線MM’的剖面示意圖討論路徑B，分別顯示於第2A、2B、17A及/或17B圖。
關於路徑A並參照第11A-11D圖，方法100的操作108，將半導體裝置200的一部分圖案化，以暴露出在溝槽270中高介電常數金屬閘極結構210中的一者和在溝槽272中源極/汲極接點220中的一者。在一些實施例中，如圖所示，暴露的高介電常數金屬閘極結構210和源極/汲極接點220屬於個別的電晶體。請參照第11A和11B圖，方法100先透過使用一系列圖案化和蝕刻製程來形成溝槽270。舉例來說，請參照第11A圖，方法100先透過將遮罩元件264A暴露於通過圖案化光阻的輻射源(例如極紫外光(extreme ultraviolet，EUV)源)，之後將曝光的遮罩元件264A顯影以形成包含對應於溝槽270的開口的圖案化的遮罩元件264A，以在層間介電層250上方形成圖案化的遮罩元件264A。在一些實施例中，圖案化的遮罩元件264A包含設置於一個或多個材料層上方的光阻層(未顯示)。在此一範例中，圖案化的遮罩元件264A可為三層結構，三層結構包含設置於中間層上方的光阻層，中間層設置於抗反射底部層上方。此外，雖然未顯示，但是可在圖案化的遮罩元件264A與層間介電層250之間形成一個或多個遮罩層，以適應任何後續的蝕刻製程。請參照第11B圖，使用圖案化的遮罩元件264A作為蝕刻遮罩，方法100接著移除層間介電層250、蝕刻停止層246和介電層232的一部分，以暴露出溝槽270中的高介電常數金屬閘極結構210。方法100可在一個或多個蝕刻製程中移除層間介電層250、蝕刻停止層246和介電層232的一部分，蝕刻製程例如乾蝕刻製程及/或反應性離子蝕刻製程。之後，透過合適的方法(例如光阻剝離及/或電漿灰化)從半導體裝置200移除圖案化的遮罩元件264A。
請參照第11C和11D圖，方法100在一系列相似於以上參考形成溝槽270所討論的圖案化和蝕刻製程中形成溝槽272，以暴露出源極/汲極接點220。舉例來說，方法100先形成圖案化的遮罩元件264B，以暴露出層間介電層250、蝕刻停止層246和設置於源極/汲極接點220上方的介電層242的一部分，且遮罩元件264B填充溝槽270。之後，使用圖案化的遮罩元件264B作為蝕刻遮罩，移除層間介電層250、蝕刻停止層246和介電層242的這些部分，以暴露出源極/汲極接點220。應當注意的是，就選擇用以蝕刻介電層242的合適蝕刻劑而言，形成溝槽272的製程可不同於形成溝槽270的製程，因為介電層242的組成不同於介電層232的組成。之後，透過上述的合適方法從半導體裝置200移除圖案化的遮罩元件264B，以暴露出高介電常數金屬閘極結構210和源極/汲極接點220。
請參照第11E圖，方法100的操作110，在溝槽270和272中以及層間介電層250的一部分上方沉積導電材料280。導電材料280可包含Co、W、Ru、Cu、Ta、Ti、Mo、Ni、其他合適的材料或前述之組合。導電材料280可透過任何合適的方法沉積，例如化學氣相沉積、物理氣相沉積、電鍍、其他合適的方法或前述之組合。在一些實施例中，在沉積導電材料280之前，在溝槽270和272中形成阻障層(未顯示)。阻障層可包含TiN、TaN、其他合適的材料或前述之組合，且可透過例如原子層沉積製程來沉積。之後，請參照第11F圖，方法100的操作112，移除導電材料280形成於層間介電層250上方的部分，以在高介電常數金屬閘極結構210上方形成導通孔282A，並在源極/汲極接點220上方形成導通孔284A。在本發明實施例中，方法100沿第11E圖的線AA’進行一個或多個化學機械研磨製程，以將半導體裝置200的頂部平坦化。因此，如第11F圖所示，可定義導通孔282A和284A具有高度H1。
請參照第11G圖，方法100的操作114，之後在半導體裝置200上方形成互連部件290。互連部件290為水平互連部件(例如導線)，依據各種設計需求，互連部件290被配置為導通孔282A及/或導通孔284A提供路徑選擇。如此一來，互連部件290將導通孔282A及/或導通孔284A電性耦接至一個或多個後續形成的互連部件。互連部件290可包含Co、W、Ru、Cu、Ta、Ti、Mo、Ni、其他合適的材料或前述之組合，且可透過任何合適的製程形成，例如鑲嵌製程或一系列沉積(例如電鍍)和圖案化製程。在一範例實施例中，透過先以合適的方法(例如電鍍)在層間介電層250上方沉積導電層，之後使用圖案化遮罩元件將導電層圖案化，以形成互連部件290。在一些實施例中，在形成互連部件290之前，在半導體裝置200上方形成阻障層(未顯示)。阻障層可包含TiN、TaN、其他合適的材料或前述之組合，且可透過例如原子層沉積製程來沉積。
在一些實施例中，請參照第11E圖，方法100的操作112，可選地沿線BB’將半導體裝置200平坦化，以在高介電常數金屬閘極結構210上方形成導通孔282B，並在源極/汲極接點220上方形成導通孔284B，如第12A圖所示，之後從半導體裝置200移除層間介電層250和蝕刻停止層246。在這點上，導通孔282B和284B的高度H2小於導通孔282A和284A的高度H1(請參照第11F圖)。此高度(或厚度)的縮減使得導通孔282B和284B分別比導通孔282A和284A具有更小的接觸電阻。之後，請參照第12B圖，方法100的操作114，在導通孔282B和284B上方形成互連部件290的製程相似於上述參考第11G圖的製程。
現在關於路徑B並參照第13A-13C圖，方法100的操作116，將半導體裝置200的一部分圖案化，以暴露出在溝槽274中的高介電常數金屬閘極結構210中的一者和相鄰的源極/汲極接點220。方法100在透過使用相似於以上參考操作108討論的一系列圖案化和蝕刻製程來形成溝槽274。舉例來說，請參照第13A圖，方法100形成包含對應於溝槽274的開口的圖案化的遮罩元件266A。圖案化的遮罩元件266A在組成上可相似於圖案化的遮罩元件264A，且可在相似於以上參考操作108討論的一系列微影製程中形成。請參照第13B圖，方法100接著使用圖案化的遮罩元件266A作為蝕刻遮罩，移除暴露於溝槽274中的層間介電層250、蝕刻停止層246和介電層232的一部分。方法100可在一個或多個蝕刻製程中移除層間介電層250、蝕刻停止層246和介電層232的一部分，蝕刻製程例如乾蝕刻製程及/或反應性離子蝕刻製程。之後，透過合適的方法(例如光阻剝離及/或電漿灰化)從半導體裝置200移除圖案化的遮罩元件266A。
之後，請參照第13C圖，方法100繼續至將半導體裝置200的一部分圖案化，以暴露出設置與高介電常數金屬閘極結構210相鄰的源極/汲極接點220以及設置於高介電常數金屬閘極結構210與源極/汲極接點220之間的閘極間隙壁212。為此，方法100在半導體裝置200上方使用具有開口276的圖案化的遮罩元件266B。在一些範例中，雖然未顯示，但是形成圖案化的遮罩元件266B可完全填充溝槽274。圖案化的遮罩元件266B在組成上可相似於圖案化的遮罩元件264A，且可在相似於以上參考操作108討論的一系列微影製程中形成。在本發明實施例中，開口276由寬度W定義，寬度W至少與從源極/汲極接點220的側壁至閘極間隙壁212的側壁的寬度W1相同，但不超過從源極/汲極接點220的側壁至高介電常數金屬閘極結構210的側壁的寬度W2，開口276部分暴露出高介電常數金屬閘極結構210。
請參照第13D圖，使用圖案化的遮罩元件266B作為蝕刻遮罩，方法100的操作118，移除暴露於開口276中的閘極間隙壁212、層間介電層250、蝕刻停止層246和介電層242的一部分。在本發明實施例中，方法100在一個或多個蝕刻製程中移除閘極間隙壁212、層間介電層250、蝕刻停止層246和介電層242的暴露部分，蝕刻製程例如乾蝕刻製程、濕蝕刻製程及/或反應性離子蝕刻製程。換句話說，在進行操作118之後，設置於高介電常數金屬閘極結構210的其中一者的側壁上的閘極間隙壁212A(即設置於高介電常數金屬閘極結構210與源極/汲極接點220之間且暴露於開口276中)比設置於高介電常數金屬閘極結構210的另外一者的側壁上的閘極間隙壁212B(即並非暴露於開口276中)更短。在本發明實施例中，方法100在操作118進行使用含氟蝕刻劑(例如CF4 、SF6 、CH2 F2 、CHF3 、C2 F6 、其他含氟蝕刻劑或前述之組合)、H2 、O2 、其他合適的蝕刻劑或前述之組合的乾蝕刻製程。應當注意的是，在操作118中用於一個或多個蝕刻製程的蝕刻劑不移除或大致不移除高介電常數金屬閘極結構210和源極/汲極接點220的一部分。之後，請參照第13D圖，透過合適的方法(例如光阻剝離及/或電漿灰化)從半導體裝置200移除圖案化的遮罩元件264B，進而擴大開口276以暴露出高介電常數金屬閘極結構210和源極/汲極接點220。
接著，請參照第13E圖，方法100的操作120，在開口276中和層間介電層250的一部分上方沉積導電材料286。導電材料286可包含Co、W、Ru、Cu、Ta、Ti、Mo、Ni、其他合適的材料或前述之組合。在一些實施例中，導電材料286大致與導電材料280相同。導電材料286可透過任何合適的方法沉積，例如化學氣相沉積、物理氣相沉積、電鍍、其他合適的方法或前述之組合。在一些實施例中，導電材料286以與導電材料280大致相同的製程沉積。在一些實施例中，在沉積導電材料286之前，在開口276中形成阻障層(未顯示)。阻障層可包含TiN、TaN、其他合適的材料或前述之組合，且可透過例如原子層沉積製程來沉積。之後，請參照第13F圖，方法100的操作122，將半導體裝置200的頂表面平坦化，以形成與高介電常數金屬閘極結構210和相鄰的源極/汲極接點220電性耦接的對接接點288A。在本發明實施例中，方法100沿第13E圖所示的線AA’進行一個或多個化學機械研磨製程，以從層間介電層250的頂表面移除多餘的導電材料286。因此，對接接點288A可透過第13F圖中的高度H3定義。
請參照第13G圖，之後，方法100的操作124，在半導體裝置200上方形成介電層292。由於對接接點288A(一般作為對接接點)將閘極(例如高介電常數金屬閘極結構210)連接至相鄰的源極/汲極接點(例如源極/汲極接點220)，因此介電層292被配置為將對接接點288A與形成於對接接點288A上方的互連部件(例如導線)隔開，以避免對接接點288A與對接接點288A上方的互連部件之間的電性短路。在一些範例中，介電層292可為介電硬遮罩，且可包含任何合適的介電材料，例如氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氮化鋯鋁、氧化鉿、其他合適的材料或前述之組合。
在一些實施例中，請再參照第13E圖，方法100的操作122，可選地沿線BB’將半導體裝置200平坦化，以形成第14A圖所示的對接接點288B，之後從半導體裝置200移除層間介電層250和蝕刻停止層246。在這點上，對接接點288B的高度H4小於第13F圖所示的對接接點288A的高度H3，使得對接接點288B具有比對接接點288A更小的接觸電阻。然而，如果操作118不移除閘極間隙壁212的頂部，如虛線輪廓所示，則沿線BB’將半導體裝置200平坦化將實際上將對接接點288B隔開為不再連接的兩個部分，進而降低對接接點288B的功能性。因此，相對於高介電常數金屬閘極結構210和源極/汲極接點220移除閘極間隙壁212的頂部允許縮減對接接點的高度，以實現較小的接觸電阻。之後，請參照第14B圖，方法100的操作124，在對接接點288B上方形成互連部件292的製程相似於上述參考第13G圖的製程。
在一些實施例中，請參照第15A圖，方法100的操作118更移除閘極間隙壁212A的一部分，以在開口276中形成開口294，使得閘極間隙壁212A的頂表面在源極/汲極接點220的頂表面之下，且高介電常數金屬閘極結構210暴露於開口276中。換句話說，開口294從開口276向下延伸至高介電常數金屬閘極結構210的頂表面和源極/汲極接點220的頂表面之下。在本發明實施例中，方法100移除閘極間隙壁212A的一部分，而不移除或大致不移除高介電常數金屬閘極結構210和源極/汲極接點220。在一些實施例中，方法100在一個或多個蝕刻製程中移除閘極間隙壁212A的一部分，蝕刻製程例如乾蝕刻製程、濕蝕刻製程及/或反應性離子蝕刻製程。在一些實施例中，閘極間隙壁212A的移除量可透過蝕刻製程的持續時間及/或在蝕刻製程期間應用的蝕刻劑的壓力來控制。在本發明實施例中，剩下的閘極間隙壁212的高度H5不限於特定值，只要剩下的閘極間隙壁212的頂表面在高介電常數金屬閘極結構210和源極/汲極接點220之下即可。在此一範例中，高度H5可為0，即可從半導體裝置200完全移除暴露於開口276中的閘極間隙壁212。之後，透過合適的方法(例如光阻剝離及/或電漿灰化)從半導體裝置200移除圖案化的遮罩元件266B。
在一些實施例中，用於移除暴露於開口276中的層間介電層250、蝕刻停止層246和介電層242的相同的蝕刻劑可用於形成開口294。換句話說，開口294可透過增加用於形成開口276的一個或多個蝕刻製程的持續時間來形成。在其他實施例中，在形成開口276之後，使用不同的蝕刻劑及/或不同的蝕刻製程來形成開口294，只要此蝕刻劑不蝕刻或大致不蝕刻高介電常數金屬閘極結構210和源極/汲極接點220的一部分。
之後，請參照第15B圖，方法100以與相似於以上參考第13E圖討論的製程，在開口276和294中沉積導電材料286。在本發明實施例中，隨著導電材料286填充開口294，導電材料286延伸以接觸高介電常數金屬閘極結構210和源極/汲極接點220的側壁。之後，請參照第15C圖，方法 100將半導體裝置200的頂表面平坦化，以形成將高介電常數金屬閘極結構210電性耦接至源極/汲極接點220的對接接點288C。在本發明實施例中，對接接點288C的底部延伸以接觸高介電常數金屬閘極結構210和源極/汲極接點220的側壁。在完全移除閘極間隙壁212以形成開口294的實施例中，導電材料286的底部延伸以接觸鰭204。換句話說，本發明實施例提供以包括對接接點288C的導電材料取代閘極間隙壁212的至少一部分的方法。相較於第13G圖所示的對接接點288A，對接接點288C的底部提供了在高介電常數金屬閘極結構210與源極/汲極接點220之間的額外接觸，以改善裝置效能。
可沿第15B圖所示的虛線CC’(即沿層間介電層250的頂表面)將半導體裝置200平坦化，以得到第15C圖所示的結構。之後，方法100以與相似於以上參考第13G圖討論的製程，在對接接點288C上方形成介電層292。替代第15C圖所示的實施例，請參照第15D圖，可沿第15B圖所示的虛線DD’(即沿介電層232(或介電層242)的頂表面)將半導體裝置200平坦化，進而移除蝕刻停止層246，以在操作122形成對接接點288D，之後，操作124在對接接點288D上方形成介電層292。相似於與對接接點288A和對接接點288B的比較，有著縮減高度的對接接點288D具有比對接接點288C更小的接觸電阻。
在一些實施例中，請參照第16A圖，在進行操作122之後，方法100移除對接接點288A的一部分，以形成溝槽279，使得對接接點288A的剩下部分的頂表面在層間介電層250的頂表面之下。為此，方法100可在半導體裝置200上方形成圖案化的遮罩元件268，圖案化的遮罩元件268包含對應於溝槽279的開口。圖案化的遮罩元件268在組成上可相似於圖案化的遮罩元件264A，且可在相似於以上參考操作108討論的一系列微影製程中形成。接著，方法100使用圖案化的遮罩元件268作為蝕刻遮罩來移除對接接點288A的一部分，以形成溝槽279。方法100可使用任何合適的蝕刻製程，例如乾蝕刻製程、濕蝕刻製程、反應性離子蝕刻製程或前述之組合，以形成溝槽279。舉例來說，蝕刻製程可為乾蝕刻製程或使用含氯氣體(例如Cl2 、CHCl3 、CCl4 及/或BCl3 )作為蝕刻劑的反應性離子蝕刻製程。之後，透過合適的方法(例如光阻剝離及/或電漿灰化)從半導體裝置200移除圖案化的遮罩元件268。在僅進行路徑B的一些範例中，由於層間介電層250與對接接點288A之間的組成差異的緣故，相對於層間介電層250，方法100在蝕刻製程中可選擇性移除對接接點288A的頂部，而不需要使用圖案化的遮罩元件268。換句話說，方法100以自對準方式形成溝槽279。
請參照第16B圖，方法100在溝槽279中沉積介電層296，之後在一個或多個化學機械研磨製程中將介電層296平坦化，使得介電層296的頂表面與層間介電層250的頂表面大致共平面。介電層296可包含氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋯、氮化鋯、氮化鋯鋁、氧化鉿、其他合適的材料或前述之組合。在一些實施例中，介電層296的組成與相鄰的介電組件(包含層間介電層250 )的組成不同。之後，請參照第16C圖，方法100以與相似於以上參考操作114討論的製程，在半導體裝置200上方形成互連部件290。
如第16C、16D、16E和16F圖所示，介電層296可形成於任何合適的實施例上方，這些實施例分別對應於以上參考第13G、14B、15C和15D圖討論的對接接點的各種配置。應當注意的是，沒有介電層296的存在的情況下，互連部件290必須透過介電層292與對接接點288(例如對接接點288A、288B、288C和288D)電性隔離。換句話說，相較於顯示第13G、14B、15C或15D圖的半導體裝置200的平面俯視圖的第17A圖，在顯示第16C、16D、16E或16F圖的半導體裝置200的平面俯視圖的第17B圖中，介電層296的存在允許互連部件290從寬度T1擴展至寬度T2，進而降低互連部件290的接觸電阻。在這方面，介電層296實際上“掩埋”對接接點(例如對接接點288A)，因此，相對於可形成於對接接點上方的各類型組件，介電層296允許更大的設計彈性，而不會引起短路問題。在一些實施例中，比較第16C圖和第16G圖，第16G圖在層間介電層296上方形成介電層292而非互連部件290。當然，雖然未顯示，但是在半導體裝置200的其他配置中，介電層292也可形成於互連部件290的位置，如第16D、16E及/或16F圖所示。
在本發明實施例中，可同時進行或依序進行路徑A或路徑B，本發明實施例並不要求特定的順序。舉例來說，可透過相同系列的圖案化製程(例如在曝光期間使用相同的光遮罩)形成溝槽270和272、開口276及/或溝槽279，透過相同的沉積製程填充相同的導電材料(例如導電材料280或導電材料286)，及/或透過相同的化學機械研磨製程沿以上討論的線AA’(即層間介電層250的頂表面)或線BB’(即介電層232和242的頂表面)平坦化。
雖然未意圖限制，但是本發明的一個或多個實施例可對半導體裝置及其形成方法提供許多優點。舉例來說，本發明實施例提供對接接點的改善結構及其製造方法，對接接點被配置來將閘極結構電性耦接至源極/汲極接點。在一些實施例中，此方法包含移除閘極間隙壁設置於閘極結構與源極/汲極接點之間的至少一部分，以得到對接接點、閘極結構與源極/汲極接點之間的較佳接觸。在一些實施例中，蝕刻閘極間隙壁，使得對接接點的底部延伸以接觸閘極結構和源極/汲極接點的側壁，進而進一步擴大對接接點、閘極結構與源極/汲極接點之間的接觸面積。透過化學機械研磨製程移除閘極間隙壁的至少一部分而不影響對接接點的功能性，可使對接接點的高度縮減，進而降低對接接點的接觸電阻。此外，本發明實施例也提供回蝕刻對接接點的一部分，並在對接接點上方形成介電層，以將對接接點與後續形成於對接接點上方的導電組件電性隔離。此介電層的存在允許互連部件(例如導線)直接形成於對接接點上方，進而擴大互連部件的寬度，並降低互連部件的接觸電阻。
在一方面，本發明實施例提供半導體結構，半導體結構包含形成於半導體基底上方的金屬閘極結構(MG)、形成金屬閘極結構的第一側壁上的第一閘極間隙壁、形成於與第一側壁相對的金屬閘極結構的第二側壁上的第二閘極間隙壁，其中第二閘極間隙壁比第一閘極間隙壁更短；設置與金屬閘極結構相鄰的源極/汲極接點(MD)，其中源極/汲極接點的側壁由第二閘極間隙壁定義；以及被配置為將金屬閘極結構電性連接至源極/汲極接點的接點部件。
在一些其他實施例中，其中第二閘極間隙壁的頂表面在源極/汲極接點的頂表面或金屬閘極結構的頂表面之下。
在一些其他實施例中，其中第二閘極間隙壁的頂表面與源極/汲極接點的頂表面或金屬閘極結構的頂表面大致共平面。
在一些其他實施例中，其中接點部件的側壁與第一閘極間隙壁對齊。
在一些其他實施例中，上述半導體結構更包含層間介電層，設置於金屬閘極結構上方，其中接點部件的頂部設置於層間介電層中。
在一些其他實施例中，上述半導體結構更包含導電層，設置於層間介電層上方；以及介電層，設置於層間介電層中，其中介電層的側壁與接點部件的側壁連續。
在另一方面，本發明實施例提供半導體結構，半導體結構包含形成於半導體基底上方的金屬閘極結構、形成與金屬閘極結構相鄰的源極/汲極部件、接觸源極/汲極部件的源極/汲極接點以及被配置以接觸金屬閘極結構和源極/汲極接點的導電部件，其中導電部件的底部埋置於金屬閘極結構的側壁與源極/汲極接點的側壁之間。
在一些其他實施例中，其中導電部件的底部接觸半導體基底。
在一些其他實施例中，上述半導體結構更包含閘極間隙壁，設置於金屬閘極結構的側壁與源極/汲極接點的側壁之間，使得導電部件的底部接觸閘極間隙壁的頂表面。
在一些其他實施例中，其中導電部件為第一導電部件，半導體結構更包含第二導電部件，其中第二導電部件透過介電層與第一導電部件隔開，且其中介電層的側壁與第一導電部件的側壁連續。
在一些其他實施例中，上述半導體結構更包含層間介電層，設置於金屬閘極結構與第二導電部件之間，其中介電層的側壁由層間介電層定義。
在一些其他實施例中，上述半導體結構更包含層間介電層，設置於金屬閘極結構上方；以及介電層，設置於層間介電層上方，其中導電部件延伸通過層間介電層以接觸介電層。
在另一方面，本發明實施例提供方法，此方法包含形成半導體裝置，半導體裝置具有形成於半導體層上方的金屬閘極結構、形成於金屬閘極結構的側壁上的閘極間隙壁及形成於半導體層中與金屬閘極結構相鄰的源極/汲極部件。此方法更包含在源極/汲極部件上方形成源極/汲極接點，其中閘極間隙壁將源極/汲極接點與金屬閘極結構隔開，在金屬閘極結構和源極/汲極接點上方形成層間介電層，以及形成開口，以暴露出金屬閘極結構、源極/汲極接點和閘極間隙壁。之後，此方法包含移除暴露於開口中的閘極間隙壁的頂部，在閘極間隙壁的剩下部分上方形成金屬層，以及將金屬層平坦化，以形成接點部件，使得接點部件電性耦接至金屬閘極結構和源極/汲極接點。
在一些其他實施例中，其中移除閘極間隙壁的頂部使得閘極間隙壁的剩下部分的頂表面與金屬閘極結構的頂表面和源極/汲極接點的頂表面大致共平面。
在一些其他實施例中，其中移除閘極間隙壁的頂部使得閘極間隙壁的剩下部分的頂表面在金屬閘極結構的頂表面和源極/汲極接點的頂表面之下。
在一些其他實施例中，其中形成金屬層使得金屬層的底部延伸以接觸金屬閘極結構的側壁和源極/汲極接點的側壁。
在一些其他實施例中，其中將金屬層平坦化的步驟包含從層間介電層的頂表面移除金屬層的一部分。
在一些其他實施例中，上述方法更包含在將金屬層平坦化之後:移除接點部件的頂部，以形成溝槽；在溝槽中形成介電層；以及在介電層上方形成導電層，使得介電層將導電層與接點部件的剩下部分隔開。
在一些其他實施例中，其中將金屬層平坦化的步驟包含移除層間介電層。
在一些其他實施例中，上述方法更包含在將金屬層平坦化之後:移除接點部件的頂部，以形成溝槽；在溝槽中形成介電層；以及在介電層上方形成導電層，使得介電層將導電層與接點部件的剩下部分隔開。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100:方法 102,104,106,108,110,112,114,116,118,120,122,124,126:操作 200:半導體裝置 202:基底 204:鰭 208:隔離結構 210:高介電常數金屬閘極結構 212,212A,212B:閘極間隙壁 214:源極/汲極部件 218,250:層間介電層 220:源極/汲極接點 230,234,240,270,272,274,279:溝槽 232,242,292,296:介電層 246:蝕刻停止層 264A,266A,266B,268:遮罩元件 276,294:開口 280,286:導電材料 282A,282B,284A,284B:導通孔 288,288A,288B,288C,288D:對接接點 290:互連部件 A,B:路徑 H1,H2,H3,H4,H5:高度 T1,T2,W,W1,W2:寬度
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。 第1圖顯示依據本發明實施例各方面之半導體裝置的製造方法的流程圖。 第2A圖為依據本發明實施例各方面之半導體裝置的三維透視圖。 第2B圖為依據本發明實施例各方面之半導體裝置的平面俯視圖。 第3、4、5、6、7、8、9、10、11A、11B、11C、11D、11E、11F、11G、12A和12B圖為依據本發明實施例各方面，在第1圖的方法的實施例的中間步驟期間，沿第2A及/或2B圖的線LL’的半導體裝置的剖面示意圖。 第13A、13B、13C、13D、13E、13F、13G、14A、14B、15A、15B、15C、15D、16A、16B、16C、16D、16E、16F和16G圖為依據本發明實施例各方面，在第1圖的方法的實施例的中間步驟期間，沿第2A及/或2B圖的線MM’的半導體裝置的剖面示意圖。 第17A圖為依據本發明實施例各方面之第13G、14B、15C及/或15D圖的半導體裝置的平面俯視圖。 第17B圖為依據本發明實施例各方面之第16C、16D、16E及/或16F圖的半導體裝置的平面俯視圖。
200:半導體裝置
202:基底
204:鰭
210:高介電常數金屬閘極結構
212,212A,212B:閘極間隙壁
214:源極/汲極部件
246:蝕刻停止層
250:層間介電層
220:源極/汲極接點
232,242,292:介電層
288A:對接接點

Claims (13)

  1. 一種半導體結構，包括：一金屬閘極結構，設置於一半導體基底上方；一第一閘極間隙壁，設置於該金屬閘極結構的一第一側壁上；一第二閘極間隙壁，設置於與該第一側壁相對的該金屬閘極結構的一第二側壁上，其中該第二閘極間隙壁比該第一閘極間隙壁更短；一源極/汲極接點，設置與該金屬閘極結構相鄰，其中該源極/汲極接點的側壁由該第二閘極間隙壁定義；以及一接點部件，將該金屬閘極結構電性連接至該源極/汲極接點，其中該接點部件的一底部位於該金屬閘極結構的側壁與該源極/汲極接點的側壁之間，且該接點部件直接接觸該金屬閘極結構的側壁和該源極/汲極接點的側壁。
  2. 如請求項1之半導體結構，其中該第二閘極間隙壁的頂表面在該源極/汲極接點的頂表面或該金屬閘極結構的頂表面之下。
  3. 如請求項1或2之半導體結構，其中該接點部件的側壁與該第一閘極間隙壁對齊。
  4. 如請求項1或2之半導體結構，更包括一層間介電層，設置於該金屬閘極結構上方，其中該接點部件的頂部設置於該層間介電層中。
  5. 如請求項4之半導體結構，更包括：一導電層，設置於該層間介電層上方；以及一介電層，設置於該層間介電層中，其中該介電層的側壁與該接點部件的側壁連續。
  6. 一種半導體結構，包括： 一金屬閘極結構，設置於一半導體基底上方；一源極/汲極部件，設置與該金屬閘極結構相鄰；一源極/汲極接點，設置於該源極/汲極部件上方；以及一導電部件，接觸該金屬閘極結構和該源極/汲極接點，其中該導電部件的一底部位於該金屬閘極結構的側壁與該源極/汲極接點的側壁之間，且該導電部件直接接觸該金屬閘極結構的側壁和該源極/汲極接點的側壁。
  7. 如請求項6之半導體結構，更包括：一閘極間隙壁，設置於該金屬閘極結構的側壁與該源極/汲極接點的側壁之間，使得該導電部件的該底部接觸該閘極間隙壁的頂表面。
  8. 如請求項6或7之半導體結構，其中該導電部件為一第一導電部件，該半導體結構更包括一第二導電部件，其中該第二導電部件透過一介電層與該第一導電部件隔開，且其中該介電層的側壁與該第一導電部件的側壁連續。
  9. 一種半導體結構的形成方法，包括：形成一半導體裝置，該半導體裝置包含設置於一半導體層上方的一金屬閘極結構、設置於該金屬閘極結構的側壁上的一閘極間隙壁及設置於該半導體層中與該金屬閘極結構相鄰的一源極/汲極部件；在該源極/汲極部件上方形成一源極/汲極接點，其中該閘極間隙壁將該源極/汲極接點與該金屬閘極結構隔開；在該金屬閘極結構和該源極/汲極接點上方形成一層間介電層；形成一開口，以暴露出該金屬閘極結構、該源極/汲極接點和該閘極間隙壁；移除暴露於該開口中的該閘極間隙壁的一頂部；在該閘極間隙壁的一剩下部分上方形成一金屬層；以及 將該金屬層平坦化，以形成一接點部件，使得該接點部件將該金屬閘極結構電性耦接至該源極/汲極接點，其中該接點部件的一底部位於該金屬閘極結構的側壁與該源極/汲極接點的側壁之間，且該接點部件直接接觸該金屬閘極結構的側壁和該源極/汲極接點的側壁。
  10. 如請求項9之半導體結構的形成方法，其中將該金屬層平坦化的步驟包含從該層間介電層的頂表面移除該金屬層的一部分。
  11. 如請求項10之半導體結構的形成方法，更包括在將該金屬層平坦化之後：移除該接點部件的頂部，以形成一溝槽；在該溝槽中形成一介電層；以及在該介電層上方形成一導電層，使得該介電層將該導電層與該接點部件的剩下部分隔開。
  12. 如請求項9之半導體結構的形成方法，其中將該金屬層平坦化的步驟包含移除該層間介電層。
  13. 如請求項12之半導體結構的形成方法，更包括在將該金屬層平坦化之後：移除該接點部件的頂部，以形成一溝槽；在該溝槽中形成一介電層；以及在該介電層上方形成一導電層，使得該介電層將該導電層與該接點部件的剩下部分隔開。
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