TWI677951B - 表面聲波濾波器封裝結構及其製作方法 - Google Patents

表面聲波濾波器封裝結構及其製作方法 Download PDF

Info

Publication number
TWI677951B
TWI677951B TW107139798A TW107139798A TWI677951B TW I677951 B TWI677951 B TW I677951B TW 107139798 A TW107139798 A TW 107139798A TW 107139798 A TW107139798 A TW 107139798A TW I677951 B TWI677951 B TW I677951B
Authority
TW
Taiwan
Prior art keywords
layer
patterned conductive
conductive layer
dielectric
dielectric substrate
Prior art date
Application number
TW107139798A
Other languages
English (en)
Other versions
TW202018895A (zh
Inventor
許詩濱
Shih Ping Hsu
許哲瑋
Che Wei Hsu
Original Assignee
恆勁科技股份有限公司
Phoenix Pioneer Technology Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 恆勁科技股份有限公司, Phoenix Pioneer Technology Co., Ltd. filed Critical 恆勁科技股份有限公司
Priority to TW107139798A priority Critical patent/TWI677951B/zh
Priority to US16/676,569 priority patent/US11387806B2/en
Application granted granted Critical
Publication of TWI677951B publication Critical patent/TWI677951B/zh
Publication of TW202018895A publication Critical patent/TW202018895A/zh
Priority to US17/833,086 priority patent/US11757426B2/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1064Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1092Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H03H3/10Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/02535Details of surface acoustic wave devices
    • H03H9/02818Means for compensation or elimination of undesirable effects
    • H03H9/02834Means for compensation or elimination of undesirable effects of temperature influence
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/02535Details of surface acoustic wave devices
    • H03H9/02992Details of bus bars, contact pads or other electrical connections for finger electrodes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/058Holders; Supports for surface acoustic wave devices
    • H03H9/059Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1064Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1071Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/125Driving means, e.g. electrodes, coils
    • H03H9/145Driving means, e.g. electrodes, coils for networks using surface acoustic waves
    • H03H9/14538Formation
    • H03H9/14541Multilayer finger or busbar electrode
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/25Constructional features of resonators using surface acoustic waves
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46Filters
    • H03H9/64Filters using surface acoustic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11312Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/276Manufacturing methods by patterning a pre-deposited material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29017Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2902Disposition
    • H01L2224/29026Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/29027Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the layer connector being offset with respect to the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83439Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

一種表面聲波濾波器封裝結構,其包括一介電基板,具有一介電層、一第一圖案化導電層、一第二圖案化導電層及一導電連接層,其中導電連接層係設於介電層內,並且電性連接分設於介電層二側之第一圖案化導電層及第二圖案化導電層,且第二圖案化導電層至少具有一指叉電極部;一晶片,係以主動面面對於指叉電極部而設置;一高分子密封框體,係設置於晶片與介電基板之間,並圍設於晶片周緣,以與晶片及介電基板共同形成一密閉腔體;模封層係設置於介電基板之上,並且覆蓋晶片及高分子密封框體。本發明復提供表面聲波濾波器封裝結構之製法。

Description

表面聲波濾波器封裝結構及其製作方法
本發明是有關於一種半導體封裝件及其製作方法,且特別是有關於一種表面聲波濾波器封裝結構及其製作方法。
表面聲波濾波器(Surface Acoustic Wave filter,SAW filter)是通訊系統中常見的零組件,其運作原理為將接收的電氣信號在壓電材料中轉化為機械波,由於機械波通過壓電材料傳播時發生延時,再藉由輸出電極將延時的機械波轉換成電能信號。透過將延時輸出信號組合重現的結果,即可達到過濾不必要的訊號及雜訊、提昇收訊品質的目標。
同時,由於表面聲波濾波器設計靈活性大、類比/數位相容、群延遲時間偏差和頻率選擇性優良(可選頻率範圍為10MHz~3GHz)、輸入輸出阻抗誤差小、傳輸損耗小、抗電磁干擾(EMI)性能好、可靠性、製作的器件體小量輕,其體積、重量分別是傳統的陶瓷介質濾波器的1/40和1/30左右,且能實現多種複雜的功能。
不過在現行各種可攜式裝置中,為縮小表面聲波濾波器的體積,通常採取三種改進方法:第一是優化元件性能,以實現在縮小的體積設計下,仍可具有良好的功效;第二是改進元件的封裝形式,捨棄傳統圓形金屬殼封裝,改以扁平金屬封裝或LCCC(無引線陶瓷晶片載體)表面貼裝;第三則是將不同功能的表面聲波濾波器封裝在一起構成組合型元件,以減小PCB面積。
第1圖繪示的是習知的一種晶圓級封裝(WLCSP)的表面聲波濾波器封裝結構之截面示意圖。如第1圖所示,習知的表 面聲波濾波器封裝結構包含上晶片15及下晶片11,其中導電電路12及表面聲波過濾電路13設置於下晶片11。上晶片15以及下晶片11之間夾設一膠框14以形成一空間101,此空間為真空共振腔體,所述的表面聲波過濾電路13即位於真空的空間101內。凸塊(bump)18則藉由底層金屬薄膜(under bump metallurgy,UBM)17以及電鍍金屬薄膜16以電性連接於上晶片15的外側表面。電鍍金屬薄膜16是自上晶片15之外側表面延伸包覆膠框14、導電電路12乃至於下晶片11與導電電路12之連接處,藉以電性連接凸塊18、上晶片15及下晶片11。
然而,習知的晶圓級封裝的表面聲波濾波器封裝結構在電性連接的設計上,乃係先接置結合上晶片15至下晶片11後,再透過電鍍製程以於封裝結構外部形成電鍍金屬薄膜16,如此不但無法簡化製作流程,又容易讓晶片在相關製程受到汙染或損壞,導至在製程的良率控制、成本控制上,均無法獲得改善。故如何開發一種得以解決上述習知技術各種缺點之製程,以薄化產品及確保濾波效能,並降低製造成本,實為目前亟欲解決之課題之一。
因此,本發明之目的係提供一種表面聲波濾波器封裝結構及其製作方法,以大尺寸板面封裝(panel level packaging)製程製作表面聲波濾波器封裝結構,其可以薄化封裝結構及確保濾波效能,並降低製造成本。
為達上述目的,本發明提供一種表面聲波濾波器封裝結構,其包括一介電基板、一晶片、一高分子密封框體以及一模封層。介電基板具有一介電層、一第一圖案化導電層、一第二圖案化導電層及一導電連接層。第一圖案化導電層係設置於介電基板之第一側的介電層內。第二圖案化導電層係設置於介電基板之第二側的介電層上,並至少區分為一導電電路部、一導電電極部及一指叉電極部。導電連接層係設置於介電層內,並且電性連接於第一圖案化導電層及第二圖案化導電層。晶片具有一主動 面,且晶片之主動面係面向於介電基板之第二側,並使主動面對應於第二圖案化導電層之指叉電極部而設置。高分子密封框體,係設置於該晶片與該介電基板之間,並圍設於晶片周緣,以與晶片及介電基板共同形成一密閉腔體。模封層係設置於介電基板之上,並且覆蓋晶片及高分子密封框體。
於本發明之一實施例中,表面聲波濾波器封裝結構更包括一圖案化保護層,其係設置於介電基板之介電基板之第一側,並暴露出部分之第一圖案化導電層。
於本發明之一實施例中,其中高分子密封框體與晶片於一投影方向係具有一封閉重疊區域。
於本發明之一實施例中,其中高分子密封框體係被模封層完全包覆。在其他實施例中,高分子密封框體的側邊係外露於模封層。
於本發明之一實施例中,其中晶片之主動面設置有至少一電性連接墊,其係藉由一導電元件而與第二圖案化導電層之導電電極部電性連接。
於本發明之一實施例中,其中導電元件係為一導電凸塊、一錫球或一導電膠。
於本發明之一實施例中,其中導電連接層具有至少一導電柱及/或一導電盲孔。
於本發明之一實施例中,其中模封層之材質係為鑄模化合物。
於本發明之一實施例中,其中第一圖案化導電層之一表面係暴露出於介電基板之第一側之介電層之表面。
於本發明之一實施例中,第二圖案化導電層之表面係突出於介電基板之第二側之介電層之表面。在其他實施例中,第二圖案化導電層之表面上係再覆蓋有一介電層,並且暴露出該第二圖案化導電層之一表面。
另外,為達上述目的,本發明提供一種表面聲波濾波器封裝結構之製作方法,其包括下列步驟。步驟一係形成一具 有相對之一第一側及一第二側之介電基板於一承載板上,該介電基板包括有一第一圖案化導電層、一介電層、一導電連接層、以及一第二圖案化導電層。步驟二係形成複數個高分子密封框體於該介電基板之第二側上,各該高分子密封框體係具有一開口以暴露部分之介電基板之第二側。步驟三係將複數個晶片設置於對應之各該高分子密封框體上,其中各該晶片之一主動面係面向該介電基板之第二側,並且對應於各該高分子密封框體之開口,以令對應之高分子密封框體、晶片與介電基板共同形成一密閉腔體。步驟四係形成一模封層覆蓋該等晶片及該等高分子密封框體。步驟五係移除承載板。
於本發明之一實施例中,其中形成介電基板之步驟係包括下列步驟。首先,於承載板之一表面形成一第一圖案化導電層;而後,於承載板上形成一介電層,並且覆蓋第一圖案化導電層;而後,於介電層形成複數開口,以暴露部分之第一圖案化導電層;而後,形成一導電連接層於該等開口,以及形成一第二圖案化導電層於介電層及導電連接層上。
於本發明之一實施例中,其中,於形成第二圖案化導電層後,還可包括形成另一介電層於該介電基板之第二側的介電層上,並且暴露出該第二圖案化導電層之一表面。
於本發明之一實施例中,其中於移除承載板之後更包括形成一圖案化保護層於該介電基板之該第一側,並且暴露出部分之第一圖案化導電層。
於本發明之一實施例中,於移除該承載板之前或之後,更包括根據各該晶片及各該高分子密封框體之區域切割,以形成複數個單一封裝結構。
11‧‧‧下晶片
12‧‧‧導電電路
13‧‧‧表面聲波過濾電路
14‧‧‧膠框
15‧‧‧上晶片
16‧‧‧電鍍金屬薄膜
17‧‧‧底層金屬薄膜
18‧‧‧凸塊
101‧‧‧空間
200、400、400-1、400-2、400a、400b‧‧‧表面聲波濾波器封裝結構
201、401-1、401-2‧‧‧腔體
21、41‧‧‧介電基板
211、411‧‧‧第一側
212、412‧‧‧第二側
23、43‧‧‧第一圖案化導電層
25、45、45a‧‧‧介電層
27、47‧‧‧導電連接層
29、49‧‧‧第二圖案化導電層
291、491‧‧‧導電電路部
292、492‧‧‧導電電極部
293、493‧‧‧指叉電極部
31、51-1、51-2‧‧‧高分子密封框體
33、53-1、53-2‧‧‧晶片
331、531-1、531-2‧‧‧主動面
332、532‧‧‧電性連接墊
35、55‧‧‧導電元件
37、57‧‧‧模封層
39、59‧‧‧圖案化保護層
40‧‧‧承載板
451、511、511a、591‧‧‧開口
51‧‧‧高分子密封層
OV1‧‧‧封閉重疊區域
第1圖係顯示習知表面聲波濾波器封裝結構之剖視示意圖。
第2圖係顯示依據本發明較佳實施例之表面聲波濾波器封裝結構的剖視示意圖。
第3A圖至第3J圖係顯示本發明較佳實施例之表面聲波濾波器封裝結構的製作方法的結構示意圖。
第4圖係顯示表面聲波濾波器封裝結構的俯視圖。
第5圖係顯示在表面聲波濾波器封裝結構的製作方法之另一實施例中,令第二圖案化導電層之表面係齊平於介電基板之介電層之表面的結構示意圖。
第6圖係顯示依據本發明另一實施例之表面聲波濾波器封裝結構的剖視示意圖。
第7圖係顯示在表面聲波濾波器封裝結構的製作方法之又一實施例中,高分子密封框體的側邊包覆於模封層的實施態樣的結構示意圖。
第8圖係顯示依據本發明又一實施例之表面聲波濾波器封裝結構的剖視示意圖。
關於本發明之優點與精神可以藉由以下發明詳述及所附圖式得到進一步的瞭解。本發明較佳實施例之製造及使用係詳細說明如下。必須瞭解的是本發明提供了許多可應用的創新概念,在特定的背景技術之下可以做廣泛的實施。此特定的實施例僅以特定的方式表示,以製造及使用本發明,但並非限制本發明的範圍。
請參照第2圖所示,依據本發明較佳實施例之表面聲波濾波器封裝結構200係包括一介電基板21、一晶片33、一高分子密封框體31、一模封層37以及一圖案化保護層39。
介電基板21具有一介電層25、一第一圖案化導電層23、一第二圖案化導電層29及一導電連接層27。另外,介電基板21還具有相對設置之一第一側211及一第二側212。
介電層25之材質可以為高填料含量介電材(high filler content dielectric material),例如為鑄模化合物(molding compound),其係以酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)或矽基樹脂(Silicone-Based Resin)為 主要基質,其佔鑄模化合物之整體比例約為8wt.%~12wt.%,並摻雜佔整體比例約70wt.%~90wt.%的填充劑而形成。其中,填充劑可以包括二氧化矽及氧化鋁,以達到增加機械強度、降低線性熱膨脹係數、增加熱傳導、增加阻水及減少溢膠的功效。
第一圖案化導電層23係設置於介電基板21之第一側211的介電層25內,且第一圖案化導電層23之部分表面係暴露於介電層25的表面。第一圖案化導電層23可包括導電金屬材料,例如銅、銀、鎳或其組成之合金。
第二圖案化導電層29係設置於介電基板21之第二側212之介電層25之表面,並依據其作用或連接關係的不同而至少區分為一導電電路部291、一導電電極部292及一指叉電極部293。與第一圖案化導電層23相同,第二圖案化導電層29可包括導電金屬材料,例如銅、銀、鎳或其組成之合金。
導電連接層27係設置於介電層25之內,並且電性連接於第一圖案化導電層23及第二圖案化導電層29。導電連接層27可以是導電柱(conductive pillar)或是導電盲孔(conductive blind hole)。導電連接層27之材料可相同或不同於第一圖案化導電層23及第二圖案化導電層29之導電金屬材料,例如為銅。
晶片33具有一主動面331,且晶片33之主動面331係面向於介電基板21之第二側212,並使主動面331對應於第二圖案化導電層29之指叉電極部293而設置。在本實施例中,晶片33係為表面聲波晶片(SAW chip)。另外,晶片33之主動面331還設置有複數個電性連接墊332,而晶片33則係藉由電性連接墊332透過導電元件35而與第二圖案化導電層29之導電電極部292電性連接。其中,導電元件35可以係為導電凸塊、錫球或導電膠,如是導電凸塊,其可以是包括金凸塊(gold bump)、共晶錫鉛凸塊(eutectic solder bump)或高鉛錫鉛凸塊(high lead solder bump)。
高分子密封框體31係設置於晶片33與介電基板21之間,並圍設於晶片33周緣,以與晶片33及介電基板21共同形成一密閉腔體201。高分子密封框體31之功效係為了使得腔體201保持 密封(氣密)的狀態,因此其材質可為具有彈性或可壓縮性的高分子材料。要說明的是,於此所謂的彈性或可壓縮性,非指富有彈性的材料,而是指具有低彈性係數的材料,其可包括以橡膠或樹脂為基底之材料。
模封層37係設置於介電基板21之上,並且覆蓋晶片33及高分子密封框體31。與介電層25相同,模封層37之材質也可以為高填料含量介電材,例如為鑄模化合物。
圖案化保護層39係設置於介電基板21之第一側211之介電層25上,並且覆蓋介電層25之表面及部分的第一圖案化導電層23。其中,暴露於圖案化保護層39的第一圖案化導電層23可作為與外部組件(例如電路板)電性連接的電性連接墊(或稱焊墊)之用。
接著,請參照第3A圖至第3J圖所示,依據本發明較佳實施例之表面聲波濾波器封裝結構400的製作方法係包括步驟S01至步驟S11。
如第3A圖所示,步驟S01係提供一承載板40,並於承載板40之表面上形成一第一圖案化導電層43。承載板40可包括金屬板或絕緣板。若承載板40採用金屬板,其材質可為銅。另一方面,若承載板40採用絕緣板,則其材質可為陶瓷、環氧樹脂(epoxy resin)、聚乙醯胺(polyimide)、氰脂(cyanate ester)、碳纖維(carbon fiber)或玻璃纖維(glass fiber)與環氧樹脂所混合之材質所構成。第一圖案化導電層43可包括導電金屬材料,例如銅、銀、鎳或其組成之合金。第一圖案化導電層43可配合額外之光阻層(圖中未顯示)執行曝光顯影工序,並執行電鍍工序,以將第一圖案化導電層43形成於承載板40上。
如第3B圖所示,步驟S02係於承載板40之表面上形成一介電層45,並且覆蓋第一圖案化導電層43。而後,係於介電層45採用雷射鑽孔(laser)技術形成複數個開口451,以暴露出部分第一圖案化導電層43。
如第3C圖所示,步驟S03係形成一導電連接層47於如 圖3B所示的該些開口451中,以及形成一第二圖案化導電層49於介電層45及導電連接層47上。與第一圖案化導電層43類似地,導電連接層47及第二圖案化導電層49亦可配合額外之光阻層(圖中未顯示)執行曝光顯影工序,並執行電鍍工序,以將導電連接層47形成於開口451中,以及將第二圖案化導電層49形成於介電層45及導電連接層47上。於此,第二圖案化導電層49係可區分為導電電路部491、導電電極部492及指叉電極部493。
為了便於後續的敘述,於此要說明的是,上述所形成的第一圖案化導電層43、介電層45、導電連接層47以及第二圖案化導電層49係可稱之為介電基板41,其具有相對之第一側411及第二側412。其中,介電基板41與承載板40接觸的一側係為第一側411。另外,經由上述製程所製作的介電基板41係為超薄基板,其厚度不大於100微米。
接著,如第3D圖所示,步驟S04係形成一高分子密封層(polymer layer)51於介電基板41之第二側412上,換言之,高分子密封層51係形成於介電層45及第二圖案化導電層49上。
接著,如第3E圖所示,步驟S05係於高分子密封層51以咬蝕技術形成複數個開口511以暴露出部分的第二圖案化導電層49,進而形成複數個高分子密封框體51-1、51-2。
而後,如第3F圖所示,步驟S06係將複數個晶片53-1、53-2設置於對應之各該高分子密封框體51-1、51-2上。其中,晶片53-1、53-2之主動面531-1、531-2係面向介電基板41之第二側412。在本實施例中,晶片53-1、53-2之主動面531-1、531-2還設置有電性連接墊532,其係分別對應於第二圖案化導電層49之導電電極部492設置,並藉由對應的導電元件55而令其產生電性連接。其中,導電元件55可以係為導電凸塊、錫球或導電膠,其可藉由印刷製程或點膠製程而形成。
據此,高分子密封框體51-1、51-2、晶片53-1、53-2與介電基板41之間係共同形成一密閉腔體401-1、401-2,並且第二圖案化導電層49之指叉電極部493係位於密閉腔體401-1、401-2內。
於此,要特別說明的是,於傳統之晶圓型式(wafer type)之製程中,僅能對於形成於單一晶圓內之晶片同時進行封裝製程,其較為耗時且具有製程上之諸多限制。相較於傳統之晶圓型式之封裝製程,本發明採用大尺寸板面型式(panel level type)之封裝製程;亦即承載板40之面積為單一晶圓面積之複數倍。據此,本發明之大尺寸承載板40能夠對於切割自複數個晶圓之全部晶片同時進行封裝製程,而能有效節省製造時程。
接著,如第3G圖所示,步驟S07係以鑄模製程形成一模封層57,以覆蓋晶片53-1、53-2及高分子密封框體51-1、51-2。在本實施例中,模封層57之材質係與介電層45之材質相同或不同,其包括高填料含量介電材(high filler content dielectric material),例如為鑄模化合物(molding compound),其係以酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)或矽基樹脂(Silicone-Based Resin)為主要基質,其佔鑄模化合物之整體比例約為8wt.%~12wt.%,並摻雜佔整體比例約70wt.%~90wt.%的填充劑而形成。其中,填充劑可以包括二氧化矽及氧化鋁,以達到增加機械強度、降低線性熱膨脹係數、增加熱傳導、增加阻水及減少溢膠的功效。
接著,如第3H圖所示,步驟S08係移除承載板40。
接著,如第3I圖所示,步驟S09係形成一圖案化保護層59於介電基板41之第一側411,以完成表面聲波濾波器封裝結構400的製作。換言之,圖案化保護層59係形成於介電層45及第一圖案化導電層43上。其中,圖案化保護層59之開口591係可藉由雷射鑽孔技術完成。
最後,如第3J圖所示,步驟S10係將如第3I圖所示的封裝結構400切割成各個獨立的表面聲波濾波器封裝結構400-1、400-2。
承上所述,請參照第4圖所示並搭配上述,以表面聲波濾波器封裝結構400-1為例,本發明之表面聲波濾波器封裝結構400-1之高分子密封框體51-1與晶片53-1於一正投影方向(例如俯 視)具有一封閉重疊區域OV1。封閉重疊區域OV1的作用在於,在形成上述模封層57的過程中,模封層57的原料不會溢到密閉腔體401-1中,而破壞了腔體結構。
請再參照第2圖,在前述的實施例中可以觀察到,第一圖案化導電層23之表面係齊平於介電基板21之第一側211的介電層25之表面;第二圖案化導電層29之表面係突出於介電基板21之第二側212的介電層25之表面。在其他實施例中,第一圖案化導電層之表面係可突出於介電基板之第一側之介電層之表面,而第二圖案化導電層之表面係可齊平於介電基板之第二側之介電層之表面。
以下,請再參照第5圖及第6圖所示,以簡單說明第二圖案化導電層之表面齊平於介電基板之第二側之介電層之表面的實施態樣。
如第5圖所示,其係接續於前述實施例之第3C圖所述之步驟S03之後執行,於此,係在形成第二圖案化導電層49之後,再形成另一介電層45a於介電層45及第二圖案化導電層49上。而後,再以研磨工序減薄介電層45a之厚度,並且暴露出第二圖案化導電層49之表面,使其與介電層45a之表面齊平。而在此步驟之後,則繼續執行步驟S04,其後續步驟則不再多加贅述。
據此所製成的表面聲波濾波器封裝結構係如第6圖所示,表面聲波濾波器封裝結構400a之第二圖案化導電層49之表面係齊平於介電基板41之第二側412之介電層45a之表面。進一步而言,第二圖案化導電層49之表面、介電層45a之表面以及高分子密封框體51-1之表面,實質上係同一平面。
再者,在前述的實施例中可以觀察到,切割後的表面聲波濾波器封裝結構之高分子密封框體的側邊係外露於模封層。在其他實施例中,高分子密封框體的側邊亦可包覆於模封層中,以避免晶片與高分子密封框體之接合處劣化而延著產生龜裂分離之情事。
以下請再參照第7圖及第8圖所示,以簡單說明高分 子密封框體的側邊包覆於模封層的實施態樣。
如第7圖所示,其係接續於前述實施例之第3D圖所述之步驟S04之後執行。於此,係於高分子密封層51以咬蝕技術形成複數個開口511以及開口511a以暴露出部分的第二圖案化導電層49。而在此之後,則接續執行上述步驟S06至步驟S10,以形成如第8圖所示之表面聲波濾波器封裝結構400b,其高分子密封框體51-1之側邊係包覆於模封層57中。
綜上所述,茲將本發明之表面聲波濾波器封裝結構及其製作方法達成的功能特徵臚列如下:
01.藉由大尺寸板面製程,可以對複數個晶圓的晶片同時批量進行製程,以提高生產效率,因此相較於習知的WLCSP技術,本發明的批次產量可以是習知技術的倍數,而可大幅提升製程效率並有效降低成本。
02.本發明使用高分子材料作為高分子密封框體,搭配模封層包覆晶片,可以提昇整體的結構剛性,以及密封性,因而可應用於較差的工作環境,改善可靠度及效能。
03.本發明其中接置結合晶片33之後,隨即藉由模封層37將晶片33包覆封裝,故能確保晶片33於後續製程不會受到汙染或損壞,因此可以有效提昇整體生產良率。
04.藉由薄型化的介電基板21、41取代傳統表面聲波濾波器封裝結構之下晶片11,能確實有效薄型化表面聲波濾波器封裝結構,藉以完全滿足彈性化的應用環境需求。
以上所述僅為舉例性,而非為限制性者。任何未脫離本發明之精神與範疇,而對其進行之等效修改或變更,均應包括於後附之申請專利範圍中。

Claims (14)

  1. 一種表面聲波濾波器封裝結構,包含:一介電基板,具有一介電層、一第一圖案化導電層、一第二圖案化導電層及一導電連接層,該介電層具有相對之一第一側及一第二側,該第一圖案化導電層設置於該介電層內,且該第一圖案化導電層之一表面自該介電層之該第一側暴露出來,該第二圖案化導電層設置於該介電層之該第二側之上,並至少區分為一導電電路部、一導電電極部及一指叉電極部,該導電連接層係設置於該介電層內,並且電性連接於該第一圖案化導電層及該第二圖案化導電層;一晶片,具有一主動面,該晶片係以該主動面面向於該介電基板之該第二側,且該主動面係對應於該第二圖案化導電層之該指叉電極部設置;一高分子密封框體,係設置於該晶片與該介電基板之間,並圍設於該晶片周緣,以與該晶片及該介電基板共同形成一密閉腔體;以及一模封層,設置於該介電基板之上,並且覆蓋該晶片及該高分子密封框體。
  2. 如申請專利範圍第1項所述之封裝結構,更包含:一圖案化保護層,設置於該介電基板之該介電層之該第一側,並暴露出部分之該第一圖案化導電層。
  3. 如申請專利範圍第1項所述之封裝結構,其中該高分子密封框體與該晶片於一投影方向係具有一封閉重疊區域。
  4. 如申請專利範圍第1項所述之封裝結構,其中該高分子密封框體係被該模封層完全包覆。
  5. 如申請專利範圍第1項所述之封裝結構,其中該高分子密封框體的側邊更外露於該模封層。
  6. 如申請專利範圍第1項所述之封裝結構,其中該晶片之該主動面設置有至少一電性連接墊,其係藉由一導電元件而與該第二圖案化導電層之該導電電極部電性連接。
  7. 如申請專利範圍第6項所述之封裝結構,其中該導電元件係為一導電凸塊、一錫球或一導電膠。
  8. 如申請專利範圍第1項所述之封裝結構,其中該導電連接層具有至少一導電柱及/或一導電盲孔。
  9. 如申請專利範圍第1項所述之封裝結構,其中該模封層之材質係為鑄模化合物。
  10. 如申請專利範圍第1項所述之封裝結構,其中該第二圖案化導電層係設於該介電層內,且該第二圖案化導電層之一表面係暴露於該介電層之該第二側之表面。
  11. 一種表面聲波濾波器封裝結構之製作方法,包含:於一承載板之一表面形成一第一圖案化導電層;於該承載板上形成一介電層,並且覆蓋該第一圖案化導電層;於該介電層形成複數開口,以暴露部分之該第一圖案化導電層;形成一導電連接層於該等開口;形成一第二圖案化導電層於該介電層及該導電連接層上,且該第二圖案化導電層並至少區分為一導電電路部、一導電電極部及一指叉電極部,其中該第一圖案化導電層、該介電層、該導電連接層以及該第二圖案化導電層組成一介電基板,該介電基板具有相對之一第一側及一第二側;形成複數個高分子密封框體於該介電基板之該第二側上,各該高分子密封框體係具有一開口以暴露該介電基板;將複數個晶片設置於對應之各該高分子密封框體上,其中各該晶片之一主動面係面向該介電基板之該第二側,並且對應於各該高分子密封框體之該開口,以令對應之該高分子密封框體、該晶片與該介電基板共同形成一密閉腔體;形成一模封層覆蓋該等晶片及該等高分子密封框體;以及移除該承載板。
  12. 如申請專利範圍第11項所述之製作方法,其中,於形成該第二圖案化導電層後,更包含:形成另一介電層於該介電層與該第二圖案化導電層上,並且暴露出該第二圖案化導電層之一表面。
  13. 如申請專利範圍第11項所述之製作方法,於移除承載板之後,更包含:形成一圖案化保護層於該介電基板之該第一側,並暴露出部分之該第一圖案化導電層。
  14. 如申請專利範圍第11項所述之製作方法,於移除該承載板之前或之後,更包含:根據各該晶片及各該高分子密封框體之區域切割,以形成複數個單一封裝結構。
TW107139798A 2018-11-09 2018-11-09 表面聲波濾波器封裝結構及其製作方法 TWI677951B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW107139798A TWI677951B (zh) 2018-11-09 2018-11-09 表面聲波濾波器封裝結構及其製作方法
US16/676,569 US11387806B2 (en) 2018-11-09 2019-11-07 Surface acoustic wave filter package structure and method of manufacturing the same
US17/833,086 US11757426B2 (en) 2018-11-09 2022-06-06 Manufacturing method for surface acoustic wave filter package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107139798A TWI677951B (zh) 2018-11-09 2018-11-09 表面聲波濾波器封裝結構及其製作方法

Publications (2)

Publication Number Publication Date
TWI677951B true TWI677951B (zh) 2019-11-21
TW202018895A TW202018895A (zh) 2020-05-16

Family

ID=69188963

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107139798A TWI677951B (zh) 2018-11-09 2018-11-09 表面聲波濾波器封裝結構及其製作方法

Country Status (2)

Country Link
US (2) US11387806B2 (zh)
TW (1) TWI677951B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI736344B (zh) * 2020-01-14 2021-08-11 力成科技股份有限公司 成批具背沉積式遮蔽層之半導體封裝結構及其製法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450580B2 (en) * 2019-12-24 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
JP7443168B2 (ja) 2020-06-26 2024-03-05 NDK SAW devices株式会社 弾性表面波デバイス
CN111786647B (zh) 2020-08-07 2021-06-15 展讯通信(上海)有限公司 晶圆级声表面波滤波器与封装方法
US20230084360A1 (en) * 2021-09-10 2023-03-16 Innolux Corporation Electronic device and manufacturing method thereof
CN115000025B (zh) * 2022-04-18 2023-10-27 锐石创芯(重庆)科技有限公司 一种芯片封装结构
CN115000024B (zh) * 2022-04-18 2023-09-08 锐石创芯(重庆)科技有限公司 一种芯片封装结构及方法
US20230387880A1 (en) * 2022-05-26 2023-11-30 Win Semiconductors Corp. Electronic structure and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339365B1 (en) * 1998-12-29 2002-01-15 Kabushiki Kaisha Toshiba Surface acoustic wave device comprising first and second chips face down bonded to a common package ground
US20040080385A1 (en) * 2002-08-29 2004-04-29 Yuichi Takamine Surface acoustic wave apparatus and communication apparatus
TW200605285A (en) * 2004-07-16 2006-02-01 Ji-Yan Shen Molding compound package with a surface acoustic wave chip
TW200616109A (en) * 2004-11-08 2006-05-16 Ycl Electronics Co Ltd Surface acoustic wave filter packaged device and its packaging method
US20070138907A1 (en) * 2005-12-16 2007-06-21 Epson Toyocom Corporation Surface acoustic wave element and surface acoustic wave device using the same
WO2018164209A1 (ja) * 2017-03-09 2018-09-13 株式会社村田製作所 弾性波装置、弾性波装置パッケージ、高周波フロントエンド回路及び通信装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6461036B2 (ja) * 2016-04-06 2019-01-30 太陽誘電株式会社 弾性波デバイス
JP6454299B2 (ja) * 2016-05-13 2019-01-16 太陽誘電株式会社 弾性波デバイス

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339365B1 (en) * 1998-12-29 2002-01-15 Kabushiki Kaisha Toshiba Surface acoustic wave device comprising first and second chips face down bonded to a common package ground
US20040080385A1 (en) * 2002-08-29 2004-04-29 Yuichi Takamine Surface acoustic wave apparatus and communication apparatus
TW200605285A (en) * 2004-07-16 2006-02-01 Ji-Yan Shen Molding compound package with a surface acoustic wave chip
TW200616109A (en) * 2004-11-08 2006-05-16 Ycl Electronics Co Ltd Surface acoustic wave filter packaged device and its packaging method
US20070138907A1 (en) * 2005-12-16 2007-06-21 Epson Toyocom Corporation Surface acoustic wave element and surface acoustic wave device using the same
WO2018164209A1 (ja) * 2017-03-09 2018-09-13 株式会社村田製作所 弾性波装置、弾性波装置パッケージ、高周波フロントエンド回路及び通信装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI736344B (zh) * 2020-01-14 2021-08-11 力成科技股份有限公司 成批具背沉積式遮蔽層之半導體封裝結構及其製法

Also Published As

Publication number Publication date
TW202018895A (zh) 2020-05-16
US20220302896A1 (en) 2022-09-22
US20200153409A1 (en) 2020-05-14
US11387806B2 (en) 2022-07-12
US11757426B2 (en) 2023-09-12

Similar Documents

Publication Publication Date Title
TWI677951B (zh) 表面聲波濾波器封裝結構及其製作方法
JP3925809B2 (ja) 半導体装置およびその製造方法
TWI527175B (zh) 半導體封裝件、基板及其製造方法
KR20080076854A (ko) 다수의 칩을 구비한 반도체 디바이스 패키지 및 제조 방법
TWI643275B (zh) 電子結構製程
CN110571201B (zh) 一种高散热扇出型三维异构双面塑封结构及其制备方法
CN114499448A (zh) 基于倒装对位键合的扇出型滤波器封装结构及其制作方法
CN111181520B (zh) 一种表面声波滤波器封装结构及其制作方法
TW202201576A (zh) 半導體封裝及其製造方法
TW201705426A (zh) 樹脂密封型半導體裝置及其製造方法
JPH10256417A (ja) 半導体パッケージの製造方法
JPH11186439A (ja) 半導体パッケージ用基板及びその製造方法
WO2021114140A1 (zh) 滤波芯片封装方法及封装结构
CN210575902U (zh) 一种高散热扇出型三维异构双面塑封结构
JP2007123941A (ja) 半導体装置の製造方法
TW202119471A (zh) 晶片封裝結構及其製作方法
US20220037223A1 (en) Electronic package structure and fabrication method thereof
US12125760B2 (en) Method for fabricating electronic package structure
TWI680547B (zh) 半導體封裝結構及其製作方法
JP2013251743A (ja) 弾性表面波デバイスとその製造方法
JPH1116947A (ja) 半導体パッケージ及びその製造方法
KR100328835B1 (ko) 팬아웃 타입 μ-BGA용 기판 및 팬아웃 타입 μ-BGA 제조 방법
KR100393100B1 (ko) 반도체패키지 및 그 제조 방법
CN116666314A (zh) 半导体封装结构及其制造方法
CN112908942A (zh) 晶片尺寸封装结构及其制作方法