TWI669746B - 閘極切割整合及相關裝置 - Google Patents

閘極切割整合及相關裝置 Download PDF

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TWI669746B
TWI669746B TW106129966A TW106129966A TWI669746B TW I669746 B TWI669746 B TW I669746B TW 106129966 A TW106129966 A TW 106129966A TW 106129966 A TW106129966 A TW 106129966A TW I669746 B TWI669746 B TW I669746B
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gate electrode
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慧峰 李
拉爾特斯 柯洛米克斯
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美商格芯（美國）集成電路科技有限公司
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Abstract

所提供的是一種用於在RMG處理期間形成閘極切口之方法及所產生的裝置。具體實施例包括形成位在基板上方之Si鰭；形成位在該基板及該Si鰭之已凹陷、曝露上部分上方的STI層；形成垂直於該Si鰭、由STI區所分開、位在該Si鰭之該上部分上且位在該Si鰭之間該STI層上的多晶矽虛設閘極電極；形成位在該多晶矽虛設閘極電極上方之硬罩；穿過該硬罩與多晶矽虛設閘極電極進行蝕刻而在一些該Si鰭之間形成凹穴；使該凹穴之側邊上受曝露之多晶矽及留在該凹穴其中一或多者之底端處之任何殘餘多晶矽氧化；以SiN填充該凹穴；移除該多晶矽虛設閘極電極；以及形成RMG。

Description

閘極切割整合及相關裝置
本揭露係關於半導體製作。特別的是，本揭露係關於14奈米(nm)技術節點及更先進的技術節點中半導體裝置製作方面之取代金屬閘極(RMG)。
在目前的半導體處理中，隨著閘極尺寸持續更小，關鍵尺寸CD更加難以控制。關鍵尺寸通常是在微影之後藉由相隔氧化物沉積來控制。若間隔物厚度太厚，閘極切割反應性離子蝕刻(RIE)可能無法清除多晶矽虛設閘極電極。藉由閘極切割RIE所產生之凹穴之底端與轉角處的多晶矽殘餘物受包括閘極開口尺寸、閘極外形及閘極高度在內的因子所影響。這些因子之可變性將導致多晶矽殘餘物，造成尖部對尖部電氣短路。
因此，需要能夠有效改良閘極關鍵尺寸、有效移除殘餘物而減少尖部對尖部短路及有效改善裝置可靠度之方法以及所產生的裝置。
本揭露之一態樣係將閘極切口間隔物厚度縮減4nm或以上，導致關鍵尺寸加寬8nm或以上。另一 態樣包括因關鍵尺寸更寬，而使閘極切割RIE後之多晶矽殘餘物減少。藉由RIE留在閘極開口之底端或轉角處的任何殘餘多晶矽係轉換成氧化物，該氧化物使潛在尖部對尖部短路消除。
本揭露之附加態樣及其它特徵將會在以下說明中提出，並且對於審查以下內容之所屬技術領域中具有通常知識者部分將會顯而易見，或可經由實踐本揭露來學習。可如隨附申請專利範圍中特別指出的內容來實現並且獲得本揭露的優點。
根據本揭露，一些技術功效可藉由一種方法來部分達成，該方法包括形成位在基板上方之矽(Si)鰭；形成位在該基板及該Si鰭之已凹陷、曝露上部分上方的淺溝槽隔離(STI)層；形成垂直於該Si鰭、由STI區所分開、位在該Si鰭之該上部分上且位在該Si鰭之間該STI層上的多晶矽虛設閘極電極；形成位在該多晶矽虛設閘極電極上方之硬罩；穿過該硬罩與多晶矽虛設閘極電極進行蝕刻而在一些該Si鰭之間形成凹穴；使該凹穴之側邊上受曝露之多晶矽及留在該凹穴其中一或多者之底端處之任何殘餘多晶矽氧化；以氮化矽(SiN)填充該凹穴；移除該多晶矽虛設閘極電極；以及在藉由移除該多晶矽虛設閘極電極所形成之空間中形成RMG。
本揭露之態樣包括在形成該多晶矽虛設閘極電極前，先形成位在該Si鰭之該上部分上方的閘極氧化物襯墊。其它態樣包括藉由RIE穿過該硬罩與多晶矽虛設 閘極電極進行蝕刻。某些態樣包括利用以SiN填充該凹穴而在該硬罩上方並行地形成SiN層。某些態樣包括藉由原子層沉積(ALD)形成該SiN層並且以SiN填充該凹穴。又進一步態樣包括在該硬罩上方所形成之該SiN層上方形成二氧化矽(SiO2)層。其它態樣包括藉由高密度電漿(HDP)沉積來形成該SiO2層。某些態樣包括平坦化該SiO2層及該硬罩與SiN層之一部分。另一態樣包括藉由化學機械研磨(CMP)來平坦化該SiO2層及該硬罩與SiN層之該部分。進一步態樣包括蝕刻該硬罩與SiN層，使該多晶矽虛設閘極電極之上表面曝露。附加態樣包括在移除該多晶矽虛設閘極電極之後，於該基板上方形成氧化物；以及在清理之後，移除該氧化物。又其它態樣包括在形成該RMG前，先在該Si鰭上方沉積高k介電質。本揭露之另一態樣係一種方法，該方法包括形成位在基板上方之Si鰭；在該Si鰭上方形成多晶矽虛設閘極電極；藉由穿過該多晶矽虛設閘極電極進行蝕刻來形成閘極切口，而在一些該鰭片之間形成凹穴；使該凹穴之側邊上受曝露之多晶矽及留在該凹穴其中一或多者之底端處之任何殘餘多晶矽氧化；以氮化物填充該凹穴；移除該多晶矽虛設閘極電極；以及在藉由移除該多晶矽虛設閘極電極所形成之空間中形成RMG。
本揭露之態樣包括在形成該多晶矽虛設閘極電極前，先形成位在該Si鰭之上部分上方的閘極氧化物襯墊。其它態樣包括形成位在該多晶矽虛設閘極電極上方之硬罩。某些態樣包括藉由RIE穿過該硬罩與多晶矽虛設 閘極電極進行蝕刻。某些態樣包括在形成該RMG前，先在該Si鰭上方沉積高k介電質。
本揭露之又另一態樣包括一種方法，其形成位在基板上方之Si鰭；形成位在該基板及該Si鰭之已凹陷、曝露上部分上方的STI層；形成垂直於該Si鰭、由STI區所分開、位在該Si鰭之該上部分上且位在該Si鰭之間該STI層上的多晶矽虛設閘極電極；形成位在該多晶矽虛設閘極電極上方之硬罩；藉由穿過該硬罩與多晶矽虛設閘極電極進行蝕刻來形成閘極切口，而在一些該Si鰭之間形成凹穴；使該凹穴之側邊上受曝露之多晶矽及留在該凹穴其中一或多者之底端處之任何殘餘多晶矽氧化；利用以SiN填充該凹穴而在該硬罩上方並行地形成SiN層；在該硬罩上方所形成之該SiN層上方形成SiO2層；平坦化該SiO2層及該硬罩與SiN層之一部分；蝕刻該硬罩與SiN，使該多晶矽層之上表面曝露；移除該多晶矽虛設閘極電極；以及在藉由移除該多晶矽虛設閘極電極所形成之空間中形成RMG。
本揭露之態樣包括在形成該多晶矽虛設閘極電極前，先形成位在該Si鰭之該上部分上方的閘極氧化物襯墊。其它態樣包括藉由RIE穿過該硬罩與多晶矽虛設閘極電極進行蝕刻；以及藉由ALD形成該SiN層並且以SiN填充該凹穴。
本揭露之附加態樣及技術功效經由以下詳細說明對於所屬技術領域中具有通常知識者將會輕易地變 為顯而易見，其中本揭露之具體實施例單純地藉由經深思用以實行本揭露之最佳模式的說明來描述。如將會瞭解的是，本揭露能夠是其它及不同的具體實施例，而且其數項細節能夠在各種明顯方面進行修改，全都不會脫離本揭露。因此，圖式及說明本質上要視為說明性，而不是作為限制。
101‧‧‧Si基板
103‧‧‧Si鰭
105‧‧‧STI層
107‧‧‧多晶矽虛設閘極電極
109‧‧‧硬罩
111‧‧‧凹穴
113‧‧‧殘餘量
115‧‧‧閘極氧化物襯墊
201‧‧‧氧化物、氧化區
301‧‧‧SiN層
303‧‧‧SiO2層
701‧‧‧氧化物
801‧‧‧RMG
803‧‧‧高k介電層
本揭露是在隨附圖式的附圖中舉例來說明，但非作為限制，圖中相似的參考元件符號係指類似的元件，並且其中：第1至8圖根據一例示性具體實施例，沿著閘極在截面圖中示意性繪示半導體製作程序。
在底下的說明中，為了解釋的目的，提出許多特定細節以便透徹理解例示性具體實施例。然而，應顯而易知的是，沒有這些特定細節或利用均等配置也可實踐例示性具體實施例。在其它實例中，眾所周知的結構及裝置是以方塊圖形式來展示，為的是要避免不必要地混淆例示性具體實施例。另外，除非另有所指，本說明書及申請專利範圍中用來表達成分、反應條件等等之量、比率、及數值特性的所有數字都要了解為在所有實例中是以「約」一語來修飾。
本揭露因應並解決閘極切割RIE所帶來之多晶矽殘餘物造成尖部對尖部電氣短路之目前問題。根據 本揭露之具體實施例，閘極切口間隔物厚度得以縮減，其加寬關鍵尺寸以允許更有效率的閘極切割RIE、以及使多晶矽殘餘物減到最少。
單純地藉由所思最佳模式的描述，還有其它態樣、特徵、以及技術功效經由下文的詳細說明對於所屬技術領域中具有通常知識者將顯而易知，其中表示並且說明的是較佳具體實施例。本揭露能夠是其它及不同的具體實施例，而且其數項細節能夠在各種明顯方面進行修改。因此，圖式及說明本質上要視為說明性，而不是作為限制。
言及第1圖，所示為沿著閘極之截面圖。提供Si基板101，並且在基板101上方形成Si鰭103。在基板101及Si鰭103之已凹陷、曝露上部分上方形成STI層105。形成垂直於Si鰭103、由STI區(為便於說明而未展示)所分開、位在Si鰭103之上部分上且位在該等Si鰭103之間STI層105上的多晶矽虛設閘極電極107。硬罩109係形成於多晶矽虛設閘極電極107上方，並且在閘極切口之位置上方圖型化有開口。如第1圖所示，一蝕刻步驟穿過硬罩109切割多晶矽虛設閘極電極107，在閘極切口位置處一些Si鰭103之間形成凹穴111。該蝕刻步驟可包括RIE。該RIE產生在閘極電極中作用為間斷部位之凹穴。雖然第1圖展示Si鰭103之對立側邊上所形成之凹穴，該等凹穴仍可沿著閘極電極在其它位置處形成。
如第1圖所示，多晶矽虛設閘極電極107 之殘餘量113可留在STI層105上方一或多個凹穴111之底端與轉角處。雖然多晶矽虛設閘極電極107之殘餘量113係繪示於第1圖之兩凹穴111中，多晶矽虛設閘極電極107之一或多個凹穴111中不存在殘餘量113處仍可有示例。在形成多晶矽虛設閘極電極107前，先在Si鰭103之上部分上方沉積閘極氧化物襯墊115以使閘極電極與鰭片絕緣。
言及第2圖，進行熱氧化步驟以使凹穴111之一個側邊上所曝露之多晶矽以及留在一或多個凹穴111之底端處之多晶矽虛設閘極電極107之任何殘餘量113氧化。氧化區201因氧化步驟而形成。在第3圖中，利用以SiN填充凹穴111而在硬罩109上方並行地沉積SiN層301。SiN層301可藉由ALD來沉積。在硬罩109上方所形成之SiN層301上方沉積SiO2層303。SiO2層303係藉由HDP沉積來形成。
如第4圖所示，平坦化SiO2層303、SiN層301以及硬罩109之上部分。該平坦化可藉由CMP來進行。言及第5圖，進行硬罩109與SiN層301之氮化物回蝕，使多晶矽虛設閘極電極107之上表面曝露。言及第6圖，移除多晶矽虛設閘極電極107以使STI層105及Si鰭103(受閘極氧化物襯墊115包覆)顯露。
如第7圖所示，在移除多晶矽虛設閘極電極107之後，於基板101上方沉積氧化物701。進行清理步驟以移除任何殘餘物，並且隨後移除氧化物701。控制 該清理以防止氧化物701穿過至下面層件進行蝕刻。虛設閘極切割後所形成之氧化物201厚度變為更薄。
言及第8圖，在藉由移除多晶矽虛設閘極電極107所形成之空間中形成RMG 801。形成RMG 801前，先在Si鰭103上方沉積高k介電層803。接著使用習知的處理步驟進行附加RMG製造。
本揭露之具體實施例可達到數種技術功效，包括改善閘極關鍵尺寸並使多晶矽殘餘物減到最少，藉此有效改善裝置可靠度並且減少尖部對尖部電氣短路。本揭露在各種工業應用之任一者中享有產業利用性，例如，微處理器、智慧型手機、行動電話、蜂巢式手機、機上盒、DVD錄影機與播放器、車輛導航、印表機與週邊裝置、網路與電信設備、遊戲系統以及數位照相機。因此，本揭露在各種類型之高度整合型半導體裝置之任一者中享有產業利用性，尤其是對於先進技術節點而言，諸如14nm技術節點及更先進的技術節點。
在前述說明中，本揭露為參照其具體例示性具體實施例作說明。然而，明顯的是，可對其實施各種修改和變更而不脫離本揭露較廣之精神與範疇，如申請專利範圍所提。本說明書及圖式從而要視為說明性而非作為限制。了解的是，本揭露能夠使用各種其它組合及具體實施例，並且如本文中所表達，能夠在本發明概念的範疇內作任何變更或修改。

Claims (12)

  1. 一種製作半導體裝置之方法，包含：形成位在基板上方之矽(Si)鰭；形成位在該基板及該Si鰭之已凹陷、曝露上部分上方的淺溝槽隔離(STI)層；形成垂直於該Si鰭、由STI區所分開、位在該Si鰭之該上部分上且位在該Si鰭之間該STI層上的多晶矽虛設閘極電極；形成位在該多晶矽虛設閘極電極上方之硬罩；穿過該硬罩與多晶矽虛設閘極電極進行蝕刻而在一些該Si鰭之間形成凹穴；使該凹穴之側邊上受曝露之多晶矽及留在該凹穴其中一或多者之底端處之任何殘餘多晶矽氧化；以氮化矽(SiN)填充該凹穴；利用以SiN填充該凹穴而在該硬罩上方並行地形成SiN層；在該硬罩上方所形成之該SiN層上方形成二氧化矽(SiO2)層；平坦化該SiO2層及該硬罩與SiN層之一部分；移除該多晶矽虛設閘極電極；以及在藉由移除該多晶矽虛設閘極電極所形成之空間中形成取代金屬閘極電極(RMG)。
  2. 如申請專利範圍第1項所述之方法，更包含：在形成該多晶矽虛設閘極電極前，先形成位在該 Si鰭之該上部分上方的閘極氧化物襯墊。
  3. 如申請專利範圍第1項所述之方法，包含藉由反應性離子蝕刻(RIE)穿過該硬罩與多晶矽虛設閘極電極進行蝕刻。
  4. 如申請專利範圍第1項所述之方法，包含：藉由原子層沉積(ALD)形成該SiN層並且以SiN填充該凹穴。
  5. 如申請專利範圍第1項所述之方法，包含藉由高密度電漿(HDP)沉積來形成該SiO2層。
  6. 如申請專利範圍第1項所述之方法，包含藉由化學機械研磨(CMP)來平坦化該SiO2層及該硬罩與SiN層之該部分。
  7. 如申請專利範圍第1項所述之方法，更包含：蝕刻該硬罩與SiN層，使該多晶矽虛設閘極電極之上表面曝露。
  8. 如申請專利範圍第7項所述之方法，更包含：在移除該多晶矽虛設閘極電極之後，於該基板上方形成氧化物；以及在清理之後，移除該氧化物。
  9. 如申請專利範圍第8項所述之方法，更包含：在形成該RMG前，先在該Si鰭上方沉積高k介電質。
  10. 一種製作半導體裝置之方法，包含：形成位在基板上方之矽(Si)鰭； 形成位在該基板及該Si鰭之已凹陷、曝露上部分上方的淺溝槽隔離(STI)層；形成垂直於該Si鰭、由STI區所分開、位在該Si鰭之該上部分上且位在該Si鰭之間該STI層上的多晶矽虛設閘極電極；形成位在該多晶矽虛設閘極電極上方之硬罩；藉由穿過該硬罩與多晶矽虛設閘極電極進行蝕刻來形成閘極切口，而在一些該Si鰭之間形成凹穴；使該凹穴之側邊上受曝露之多晶矽及留在該凹穴其中一或多者之底端處之任何殘餘多晶矽氧化；利用以SiN填充該凹穴而在該硬罩上方並行地形成氮化矽(SiN)層；在該硬罩上方所形成之該SiN層上方形成二氧化矽(SiO2)層；平坦化該SiO2層及該硬罩與SiN層之一部分；蝕刻該硬罩與SiN，使該多晶矽層之上表面曝露；移除該多晶矽虛設閘極電極；以及在藉由移除該多晶矽虛設閘極電極所形成之空間中形成取代金屬閘極電極(RMG)。
  11. 如申請專利範圍第10項所述之方法，更包含：在形成該多晶矽虛設閘極電極前，先形成位在該Si鰭之該上部分上方的閘極氧化物襯墊。
  12. 如申請專利範圍第10項所述之方法，包含：藉由反應性離子蝕刻(RIE)穿過該硬罩與多晶矽虛 設閘極電極進行蝕刻；以及藉由原子層沉積(ALD)形成該SiN層並且以SiN填充該凹穴。
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