TWI661509B - 晶片封裝方法及晶片封裝結構 - Google Patents

晶片封裝方法及晶片封裝結構 Download PDF

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TWI661509B
TWI661509B TW105139343A TW105139343A TWI661509B TW I661509 B TWI661509 B TW I661509B TW 105139343 A TW105139343 A TW 105139343A TW 105139343 A TW105139343 A TW 105139343A TW I661509 B TWI661509 B TW I661509B
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譚小春
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大陸商矽力杰半導體技術（杭州）有限公司
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Abstract

本申請提供了一種晶片封裝方法及晶片封裝結構，所述封裝方法包括：在載體表面的第一區域上形成焊線管腳，並在晶片的非有源面形成絕緣層，然後將晶片透過所述絕緣層粘貼到載體表面的第二區域，在進行引線鍵合和塑封工藝後，將載體與塑封體相剝離，使得絕緣層和焊線管腳裸露在塑封體的表面。這種封裝方法形成的封裝結構在貼裝到PCB板上時，可保證晶片的非有源面與PCB之間的絕緣性，保證了封裝結構的電氣特性。此外，所述封裝方法，無需使用預先製作好的引線框架，而是在封裝的過程中形成焊線管腳，有利於提高封裝設計的靈活性。

Description

晶片封裝方法及晶片封裝結構
本發明涉及晶片封裝技術領域，尤其涉及一種晶片封裝方法及晶片封裝結構。
早期的晶片封裝為雙列直插式DI封裝，這種封裝佈線和操作較為方便。但是，DIP封裝的封裝效率很低，且封裝產品的面積較大，不利於提高記憶體條的容量，同時還會影響記憶體頻率、傳輸速率和電器性能的提升。
為了減少晶片的封裝面積，表面貼裝技術(SMT封裝)成為目前電子組裝行業裏比較受歡迎的封裝技術，而在SMT封裝中，QFN封裝(方形扁平無引腳封裝)成為主流。現有的QFN封裝的方法通常是將半導體裸晶片的非有源面透過導電銀膠安裝在引線框架的中間焊盤上，然後再進行引線鍵合和塑封，使引線框架的引腳和中間焊盤均裸露在塑封體的表面。中間焊盤裸露在外，可增加晶片的散熱性能。
然而，有些小功率器件對散熱性能的要求並不高，但是對於其非有源面與PCB板直接的絕緣性要求非常，以防止漏電，影響了晶片的性能。對於這一類晶片的封裝，常規的這種QFN封裝方式已經不在適應。此外這種常規的QFN封裝中，需要使用預先製作好的引線框架，而引線框架一旦 製作好了，引腳的排布、間距和尺寸均已經確定，因而不利於封裝的靈活性設計。
有鑒於此，本發明提供了一種晶片封裝方法及晶片封裝結構，以保證晶片的非有源面與PCB板之間的絕緣性，同時提高封裝的靈活性設計。
一種晶片封裝方法，包括：在載體的第一表面的第一區域上形成焊線管腳，並在晶片的非有源面形成絕緣層，所述晶片的非有源面與所述晶片的有源面相對；將所述晶片透過所述絕緣層貼裝在所述載體的第一表面的第二區域上；將所述晶片的有源面上的電極透過導電引線與所述焊線管腳電連接，然後進行塑封工藝，以形成覆蓋所述晶片和焊線管腳的塑封體；整流電路，與所述接收側耦合電路連接；將所述載體與所述塑封體進行剝離，以將所述焊線管腳和絕緣層裸露在所述塑封體的表面。
優選的，所述的晶片封裝方法還包括：在形成所述焊線管腳前，先至少將所述第二區域進行表面平坦化處理，以使所述載體與所述塑封體進行剝離時，所述絕緣層可與所述第二區域相剝離開。
優選的，所述的晶片封裝方法還包括：完成所述表面平坦化處理後，將所述第一區域進行表面粗糙化處理，以使得在所述第一區域上形成所述焊線管腳時，防止所述焊線管腳移位，且可使得在所述載體與所 述塑封體進行剝離時，所述焊線管腳可與所述第二區域相剝離開。
優選的，蝕刻所述第一區域，形成具有預定深度的凹槽，以實現所述第一區域表面的粗糙化處理。
優選的，在所述凹槽處電鍍形成所述焊線管腳。
優選的，所述凹槽的深度介於0微米到5微米之間。
優選的，所述焊線管腳的底部與所述載體接觸，所述焊線管腳的底部截面積小於頂部截面積。
優選的，在所述晶片的非有源面塗覆絕緣膠，以形成所述絕緣層，所述晶片的非有源面透過所述絕緣膠粘貼在所述第二區域的表面上。
優選的，採用機械剝離方法將所述載體與所述塑封體進行剝離。
一種根據如任意一項晶片封裝方法所形成晶片封裝結構。
由上可見，本發明提供的晶片封裝方法中，在載體表面的第一區域上形成焊線管腳，並在晶片的非有源面形成絕緣層，然後將晶片透過所述絕緣層粘貼到載體表面的第二區域，在進行引線鍵合和塑封工藝後，將載體與塑封體相剝離，使得絕緣層和焊線管腳裸露在塑封體的表面。這種封裝方法形成的封裝結構在貼裝到PCB板上時，可保證晶片的非有源面與PCB之間的絕緣性，保證了封裝結構的電氣特性。此外，所述封裝方法，無需使用預先製作好的引線框架，而是在封裝的過程中形成焊線管腳，有利於提高封裝設計的靈活性。
1‧‧‧載體
2‧‧‧焊線管腳
3‧‧‧晶片
4‧‧‧絕緣層
5‧‧‧引線
6‧‧‧塑封體
透過以下參照附圖對本發明實施例的描述，本發明的上述以 及其他目的、特徵和優點將更為清楚，在附圖中：圖1為依據本發明實施例的晶片封裝方法的工藝流程圖；圖2a~2d為依據本發明實施例的晶片封裝方法的各個工藝步驟中所形成的剖面結構圖。
以下將參照附圖更詳細地描述本發明。在各個附圖中，相同的組成部分採用類似的附圖標記來表示。為了清楚起見，附圖中的各個部分沒有按比例繪製。此外，可能未示出某些公知的部分。為了簡明起見，可以在一幅圖中描述經過數個步驟後獲得的結構。在下文中描述了本發明的許多特定的細節，例如每個組成部分的結構、材料、尺寸、處理工藝和技術，以便更清楚地理解本發明。但正如本領域的技術人員能夠理解的那樣，可以不按照這些特定的細節來實現本發明。
圖1為依據本發明實施例的晶片封裝方法的工藝流程圖。
參考圖1所示，本發明提供的晶片方法主要包括以下幾大步驟：步驟S1：在載體的第一表面的第一區域形成焊線管腳，且在晶片的非有源面上形成絕緣層；步驟S2：將晶片透過所述絕緣層貼裝在所述載體的第一表面的第一區域；步驟S3：將所述晶片有源面上的電極透過導電引線與所述焊線管腳電連接，然後進行塑封工藝，以形成覆蓋所述晶片和所述焊線管腳的塑封體；步驟S4：將所述載體與塑封體進行剝離，以將所述焊線管腳和所述絕 緣層裸露在所述塑封體的表面。
圖2a~2d為依據本發明實施例的晶片封裝方法的各個工藝步驟中所形成的剖面結構圖。下面將結合圖2a~2d來具體闡述本發明提供的晶片封裝方法。
如圖2a所示，步驟S1包括兩個部分，一個是在載體1的上表面的第一區域形成焊線管腳2，另一個是在晶片3的非有源面形成絕緣層4，且這兩個部分不限定先後順序，可以同時形成，也可以先後形成。
載體1在本實施例中為金屬基板，其形成的化學元素與焊線管腳2底部的化學元素不同族，從而可使其與焊線管腳2之間的粘附力小於預定值，以確保所述焊線管腳2在步驟S4中能夠順利的與載體1相剝離。
此外，為了確保步驟S4中絕緣層4能順利的與載體1相剝離，在形成焊線管腳1之前，先至少將載體1的上表面的第二區域進行表面平坦化處理，使得所述第二區域成為光滑的表面。所述第二區域為載體1上表面的第一區域外的區域，在本實施例中，載體1上表面的第一區域位於第二區域的周圍。由於需要在載體1上表面的第一區域形成焊線管腳，為了防止焊線管腳2移位，在形成焊線管腳2之前，需要將第一區域進行表面粗糙化處理，透過控制第一區域表面粗糙化的程度既能防止焊線管腳2的移位，又能保證在進行步驟S4時，焊線管腳2可與載體1相剝離。
將第一區域進行表面粗糙化處理的具體方法為：微蝕刻第一區域，以形成具有預定值深度的凹槽(圖2a中未畫出)，所述預定值為0微米至5微米之間的一個值，例如3微米。所述凹槽的深度決定第一區域表面粗糙化的程度，因此可以透過控制所述凹槽的深度來防止焊線管腳的移位， 同時還能確保焊線管腳可與載體相剝離。
在形成所述凹槽後，在所述凹槽處電鍍形成焊線管腳2。具體電鍍步驟可以包括：先利用電鍍掩模層，在凹槽處電鍍一金屬層作為電鍍籽層，如金屬鎳層，然後再在電鍍籽層上電鍍厚的金屬層，如金屬銅層。為了保證在步驟S3中，焊線管腳可以更好的被塑封體鎖定住，而不易脫落，在電鍍形成焊線管腳2時，可使電鍍層在掩模層表面適當的延伸。使得形成的焊線管腳2的底部(與載體1的上表面相接觸的部分)截面積小於頂部截面積，可增加焊線管腳2與塑封體的接觸面積，可在進行步驟S4時，焊線管腳不與塑封體相脫離，可確保封裝的可靠性。
在本實施例中，在晶片3的非有源面形成絕緣層4的方法具體為：在晶片3的非有源面上塗覆絕緣膠，以形成絕緣層4。然後，將所述晶片3的非有源面透過所述絕緣膠粘貼在載體1上表面的第二區域上，如圖2b所示。在本申請中，晶片3是指半導體裸晶片，而非有源面為與有源面相對的一面。
參考與2c所示，在完成步驟S2後，將晶片3的有源面上的電極透過導電引線5與焊線管腳2電連接，然後再進行塑封工藝，使塑封料覆蓋在晶片3和焊線管腳2上，以形成塑封體6。最後可採用機械剝離的方法，將載體1與塑封體6進行分離，使得焊線管腳2與絕緣層4裸露在塑封體6的表面，如圖2d所示。
將圖2d所示的晶片封裝結構貼裝在PCB板上時，由於晶片3的非有源面上形成有絕緣層4，因而可保證晶片3的非有源面與PCB板之間的絕緣性，防止漏電，保證了封裝結構的電氣特性和可靠性。
由上可見，本發明提供的晶片封裝方法中，在載體表面的第一區域上形成焊線管腳，並在晶片的非有源面形成絕緣層，然後將晶片透過所述絕緣層粘貼到載體表面的第二區域，在進行引線鍵合和塑封工藝後，將載體與塑封體相剝離，使得絕緣層和焊線管腳裸露在塑封體的表面。這種封裝方法形成的封裝結構在貼裝到PCB板上時，可保證晶片的非有源面與PCB之間的絕緣性，保證了封裝結構的電氣特性。此外，所述封裝方法，無需使用預先製作好的引線框架，而是在封裝的過程中形成焊線管腳，有利於提高封裝設計的靈活性。
依照本發明的實施例如上文所述，這些實施例並沒有詳盡敍述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域技術人員能很好地利用本發明以及在本發明基礎上的修改使用。

Claims (8)

  1. 一種晶片封裝方法，包括：在載體的第一表面的第一區域上形成焊線管腳，並在晶片的非有源面形成絕緣層，所述晶片的非有源面與所述晶片的有源面相對；將所述晶片透過所述絕緣層貼裝在所述載體的第一表面的第二區域上；將所述晶片的有源面上的電極透過導電引線與所述焊線管腳電連接，然後進行塑封工藝，以形成覆蓋所述晶片和焊線管腳的塑封體；及將所述載體與所述塑封體進行剝離，以將所述焊線管腳和絕緣層裸露在所述塑封體的表面，其中，在形成所述焊線管腳前，先至少將所述第二區域進行表面平坦化處理，以使所述載體與所述塑封體進行剝離時，所述絕緣層可與所述第二區域相剝離開。
  2. 根據申請專利範圍第1項所述的晶片封裝方法，另包括：完成所述表面平坦化處理後，將所述第一區域進行表面粗糙化處理，以使得在所述第一區域上形成所述焊線管腳時，防止所述焊線管腳移位，且可使得在所述載體與所述塑封體進行剝離時，所述焊線管腳可與所述第二區域相剝離開。
  3. 根據申請專利範圍第2項所述晶片封裝方法，所述第一區域表面的粗糙化處理係透過蝕刻所述第一區域，形成具有預定深度的凹槽。
  4. 根據申請專利範圍第3項所述晶片封裝方法，其中在所述凹槽處電鍍形成所述焊線管腳。
  5. 根據申請專利範圍第4項所述的晶片封裝方法，其中所述凹槽的深度介於0微米到5微米之間。
  6. 根據申請專利範圍第1項所述的晶片封裝方法，其中所述焊線管腳的底部與所述載體接觸，所述焊線管腳的底部截面積小於頂部截面積。
  7. 根據申請專利範圍第1項所述的晶片封裝方法，其中在所述晶片的非有源面塗覆絕緣膠，以形成所述絕緣層，所述晶片的非有源面透過所述絕緣膠粘貼在所述第二區域的表面上。
  8. 根據申請專利範圍第1項所述的晶片封裝方法，其中所述載體與所述塑封體係以採用機械剝離方法進行剝離。
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