TWI626715B - 半導體結構與其製造方法 - Google Patents
半導體結構與其製造方法 Download PDFInfo
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- TWI626715B TWI626715B TW105138907A TW105138907A TWI626715B TW I626715 B TWI626715 B TW I626715B TW 105138907 A TW105138907 A TW 105138907A TW 105138907 A TW105138907 A TW 105138907A TW I626715 B TWI626715 B TW I626715B
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- Prior art keywords
- layer
- conductor
- dielectric layer
- source drain
- disposed
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種半導體結構包含基板、至少一第一閘極結構、至少一第一間隔層、至少一源極汲極結構、至少一第一介電層、至少一導體以及至少一保護層。第一閘極結構設置於基板上。第一間隔層設置於第一閘極結構的至少一側壁上。源極汲極結構相鄰於第一間隔層。第一介電層至少設置於第一閘極結構上,且具有開口於其中,其中開口裸露源極汲極結構。導體電性連接源極汲極結構,其中導體具有上部與下部,上部位於第一介電層的開口中,下部位於上部與源極汲極結構之間。保護層設置於導體的下部和第一間隔層之間與導體的上部和源極汲極結構之間。
Description
本揭露是有關於一種半導體結構與其製造方法。
半導體元件被用於各種電子應用,例如個人電腦、手機、數位相機與其他電子裝置等。半導體業界藉由不斷降低特徵尺寸以持續提升各種電子元件(例如電晶體、二極體、電阻與電容等)的集成密度。於是,更多的組件可以集成到一個給定區域。
在集成電路中,「內連線(Interconnection)」意指連接多個不同電子元件的導電線。除了在接觸區外,絕緣層分離內連導電線與基板。在特徵密度(Feature Densities)增加的時候,導電線的線寬與內連線結構中導電線之間的線距亦隨之降低。
根據本揭露一實施方式,一種半導體結構包含基板、至少一第一閘極結構、至少一第一間隔層、至少一源極汲極結構、至少一第一介電層、至少一導體以及至少
一保護層。第一閘極結構設置於基板上。第一間隔層設置於第一閘極結構的至少一側壁上。源極汲極結構相鄰於第一間隔層。第一介電層至少設置於第一閘極結構上,且具有開口於其中,其中開口裸露源極汲極結構。導體電性連接源極汲極結構,其中導體具有上部與下部,上部位於第一介電層的開口中,下部位於上部與源極汲極結構之間。保護層設置於導體的下部和第一間隔層之間與導體的上部和源極汲極結構之間。
根據本揭露另一實施方式,一種半導體結構包含基板、至少一閘極結構、至少一間隔層、至少一源極汲極結構、至少一下導體、至少一保護層、至少一第一介電層以及至少一上導體。閘極結構設置於基板上。間隔層設置於閘極結構的至少一側壁上。源極汲極結構相鄰於間隔層。下導體電性連接源極汲極結構。保護層設置於下導體與間隔層之間。第一介電層至少設置於閘極結構上,且具有開口於其中,其中開口至少部分裸露下導體。上導體藉由第一介電層的開口電性連接下導體,且至少覆蓋保護層。
根據本揭露又一實施方式,一種製造半導體結構的方法包含以下步驟。首先,形成第一介電層於至少一閘極結構與至少一源極汲極結構上。然後,形成至少部分於第一介電層中的至少一凹槽。接著,形成至少一保護層至少於凹槽的至少一側壁上。然後,深化凹槽,以裸露源極汲極結構。接著,形成下導體於凹槽中,其中下導體電性連接源極汲極結構。然後,移除第一介電層、保護層的
上部以及位於閘極結構上的下導體的上部。接著,形成第二介電層於閘極結構與下導體上。然後,於第二介電層中形成至少一開口,以裸露下導體。最後,在開口中形成上導體,其中上導體電性連接下導體。
100‧‧‧半導體結構
110‧‧‧基板
121、123‧‧‧閘極結構
130‧‧‧源極汲極結構
141、143‧‧‧間隔層
145、147‧‧‧硬遮罩層
150d、150u、180‧‧‧介電層
151‧‧‧凹槽
160‧‧‧保護層
170、190‧‧‧導電層
171‧‧‧下導體
181‧‧‧開口
191‧‧‧上導體
193‧‧‧導體
以下將以圖式揭露本揭露之複數個實施方式,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖至第8圖繪示依照本揭露一實施方式之半導體結構的製程各步驟的剖面示意圖。
以下將以圖式及不同實施方式或範例清楚說明本揭露之精神,任何所屬技術領域中具有通常知識者在瞭解本揭露之實施方式後,當可由本揭露所教示之技術,加以改變及修飾,其並不脫離本揭露之精神與範圍。舉例來說,當一元件被稱為『連接』或『耦接』至另一元件時,它可以為直接連接或耦接至另一元件,又或是其中有一額外元件存在。另外,本揭露不同實施方式可能使用相同代號或代碼來標示元件,此乃為了方便說明,而不代表不同實施方式間具有特殊關聯性。
此外,相對詞彙,如『下』或『底部』與『上』或『頂部』,用來描述文中在附圖中所示的一元件與另一
元件之關係。相對詞彙是用來描述裝置在附圖中所描述之外的不同方位是可以被理解的。例如,如果一附圖中的裝置被翻轉,元件將會被描述原為位於其它元件之『下』側將被定向為位於其他元件之『上』側。例示性的詞彙『下』,根據附圖的特定方位可以包含『下』和『上』兩種方位。同樣地,如果一附圖中的裝置被翻轉,元件將會被描述原為位於其它元件之『下方』或『之下』將被定向為位於其他元件上之『上方』。例示性的詞彙『下方』或『之下』,可以包含『上方』和『上方』兩種方位。
於本文中,除非內文中對於冠詞有所特別限定,否則「一」與「該」可泛指單一個或多個。將進一步理解的是,本文中所使用之「包含」、「包括」、「具有」及相似詞彙,指明其所記載的特徵、區域、整數、步驟、操作、元件與/或組件,但不排除其所述或額外的其一個或多個其它特徵、區域、整數、步驟、操作、元件、組件,與/或其中之群組。
當一個元件被稱為「在…上」時,它可泛指該元件直接在其他元件上,也可以是有其他元件存在於兩者之中。相反地,當一個元件被稱為「直接在」另一元件,它是不能有其他元件存在於兩者之中間。如本文所用,詞彙「與/或」包含了列出的關聯項目中的一個或多個的任何組合。
除非另有定義,本文所使用的所有詞彙(包括技術和科學術語)具有其通常的意涵,其意涵係能夠被
熟悉此領域者所理解。更進一步的說,上述之詞彙在普遍常用之字典中之定義,在本說明書的內容中應被解讀為與本揭露相關領域相通的意涵。除非有特別明確定義,這些詞彙將不被解釋為理想化的或過於正式的意涵。
第1圖至第8圖繪示依照本揭露一實施方式之半導體結構的製程各步驟的剖面示意圖。
如第1圖所繪示,形成半導體結構。半導體結構包含基板110、閘極結構121、123以及至少一源極汲極結構130。閘極結構121、123分別設置於基板110上。源極汲極結構130設置於基板110上且相鄰於閘極結構121、123。換句話說,源極汲極結構130設置於閘極結構121、123之間。需要注意的是,閘極結構121、123的數量與源極汲極結構130的數量僅為示例且不限制本揭露的其他實施方式,閘極結構121、123的數量與源極汲極結構130的數量可由實際情況決定。
在一些實施方式中,基板110之材質可為半導體材料且可包含例如漸變層或設置於其中的埋藏氧化層。在一些實施方式中,基板110包含摻雜(例如P型摻雜、N型摻雜或其組合)或未摻雜的矽塊材(Bulk Silicon)。其他適合用於形成半導體器件的材料亦可被使用。舉例來說,鍺、石英、藍寶石和玻璃亦可為基板110之材質。另外,基板110可為絕緣底半導體(Semiconductor-on-insulator,SOI)基板的主動層或者多層結構,例如形成於矽塊材上的矽鍺層。
在一些實施方式中,閘極介電層、擴散阻障層、金屬層、阻擋層、潤濕層以及填充金屬的至少一堆疊形成閘極結構121、123的至少其中之一。換句話說,閘極結構121、123的至少其中之一可包含閘極介電層、擴散阻障層、金屬層、阻擋層、潤濕層以及填充金屬的堆疊。
在一些實施方式中,閘極介電層包含介面層(Interfacial Layer,IL)。介面層為閘極介電層的下半部分且為介電層。在一些實施方式中,介面層包含氧化層,例如矽氧化物層,其可藉由基板110的熱氧化製程、化學氧化製程、或沉積製程形成。閘極介電層亦可包含高介電常數介電層。高介電常數介電層為閘極介電層的上半部分,且高介電常數介電層包含高介電常數介電材料,例如氧化鉿、氧化鑭、氧化鋁或其組合。高介電常數介電材質的介電常數(k值)大於約3.9,且可能大於約7。介電常數有時可能會是約21或是更大。高介電常數介電層覆蓋介面層,且高介電常數介電層可以接觸介面層。
在一些實施方式中,擴散阻障層包含氮化鈦,氮化鉭或其組合。舉例來說,擴散阻障層可以包括氮化鈦層與設置於氮化鈦層上的氮化鉭層,氮化鈦層為擴散阻障層的下半部分,氮化鉭層為擴散阻障層的上半部分。
當閘極結構121、123的其中之一形成N型金屬氧化物半導體(Metal-oxide-semiconductor,MOS)器件時,金屬層接觸擴散阻障層。舉例來說,在擴散阻障層包括氮化鈦層與氮化鉭層的實施方式中,金屬層可以實體接
觸氮化鉭層。在另一實施方式中,閘極結構121、123的其中之一形成P型金屬氧化物半導體器件,一個額外的氮化鈦層會形成於(在擴散阻障層中的)氮化鉭層與覆蓋於氮化鉭層上的金屬層之間,於是氮化鈦層接觸氮化鉭層。額外的氮化鈦層提供適合P型金屬氧化物半導體器件的功函數,此功函數大於中間能隙功函數(Mid-gap Work function)。中間能隙功函數約為4.5eV,且其位於矽的價帶與傳導帶的中間。此大於中間能隙功函數的功函數被稱為P型功函數,而具有P型功函數的對應金屬被稱為P型金屬。
金屬層提供適合N型金屬氧化物半導體器件的功函數,此功函數小於中間能隙功函數。此小於中間能隙功函數的功函數被稱為N型功函數,而具有N型功函數的對應金屬被稱為N型金屬。在一些實施方式中,金屬層之材質為N型金屬,其具有低於約4.3eV的功函數。在一些實施方式中,金屬層的功函數亦可為約3.8eV至約4.6eV。金屬層可包含鋁鈦合金(Titanium Aluminum),鋁鈦合金可以包含其他元素,或者鋁鈦合金可以不包含或幾乎不包含其他元素。金屬層可藉由物理氣相沉積製程(Physical Vapor Deposition,PVD)形成。在一些實施方式中,金屬層形成於室溫(舉例來說,約攝氏20度至約攝氏25度)。在其他實施方式中,金屬層形成於高於室溫的溫度(舉例來說,高於約攝氏200度)。
在一些實施方式中,阻擋層可包含氮化鈦層。阻擋層可藉由原子層沉積製程(Atomic Layer Deposition,ALD)形成。
潤濕層具有在進行填充金屬的回焊製程時黏著(與濕潤)填充金屬(填充金屬在潤濕層之後形成)的功能。在一些實施方式中,潤濕層為鈷層,且潤濕層可藉由原子層沉積製程或化學氣相沉積製程(Chemical Vapor Deposition,CVD)形成。
填充金屬可包含鋁、鋁合金(例如鋁鈦合金)、鎢或銅。填充金屬亦可藉由物理氣相沉積製程、化學氣相沉積製程或類似製程形成。填充金屬可被回焊。形成潤濕層將提升填充金屬對於其下之層的濕潤。
源極汲極結構130可藉由摻雜雜質於至少一主動半導體鰭形結構形成,而鰭形結構可藉由微影技術以圖案化與蝕刻基板110形成。在金屬氧化物半導體器件的最終產品為N型金屬氧化物半導體器件的實施方式中,N型雜質例如磷或砷可摻雜於源極汲極結構130。在金屬氧化物半導體器件的最終產品為P型金屬氧化物半導體器件的實施方式中,P型雜質例如硼或二氟化硼可摻雜於源極汲極結構130。
在其他實施方式中,源極汲極結構130可藉由例如磊晶形成。在一些實施方式中,源極汲極結構130可以做為源極汲極應力源(Stressor)以提升半導體器件的載子遷移率與器件效能。源極汲極結構130藉由循環的沉積與蝕刻製
程(Cyclic Deposition and Etching,CDE)形成。循環的沉積與蝕刻製程包含磊晶沉積/局部蝕刻製程與至少一次重複的磊晶沉積/局部蝕刻製程。
在金屬氧化物半導體器件的最終產品為N型金屬氧化物半導體器件的實施方式中,源極汲極結構130可為N型磊晶結構。在金屬氧化物半導體器件的最終產品為P型金屬氧化物半導體器件的實施方式中,源極汲極結構130可為P型磊晶結構。N型磊晶結構之材質可為磷化矽、碳化矽、磷碳化矽、矽、III-V族半導體材料化合物或其組合。P型磊晶結構之材質可為矽鍺、碳化矽鍺、鍺、矽、III-V族半導體材料化合物或其組合。在形成N型磊晶結構時,N型雜質例如磷或砷可摻雜磊晶中。舉例來說,當N型磊晶結構包含磷化矽或碳化矽時,N型雜質摻雜於其中。另外,在形成P型磊晶結構時,P型雜質例如硼或二氟化硼可摻雜磊晶中。舉例來說,當P型磊晶結構包含矽鍺時,P型雜質摻雜於其中。磊晶製程包含化學氣相沉積技術(舉例來說,氣相磊晶(Vapor-phase Epitaxy,VPE)且/或超高真空化學氣相沉積(Ultra-high Vacuum Chemical Vapor Deposition,UHV-CVD))、分子束磊晶且/或其他適合製程。源極汲極結構130在磊晶的同時摻雜(In-situ Doped)。假如源極汲極結構130不是在磊晶的同時摻雜,進行第二佈植製程(即接面佈植製程(Junction Implant Process))以摻雜源極汲極結構130。可以進行一或多個退火製程以活化源極汲極結構130。退火製程包含快速熱退火製程(Rapid
Thermal Annealing,RTA)且/或雷射退火製程(Laser Annealing)。
另外,間隔層141設置於閘極結構121的側壁上,且間隔層143設置於閘極結構123的側壁上。在一些實施方式中,間隔層141、143的至少其中之一包含一或多層,包含氮化矽、氮氧化矽、氧化矽或其他介電材料。可能的形成方法包含電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)、低壓化學氣相沉積(Low-pressure Chemical Vapor Deposition,LPCVD)、在低於一大氣壓的環境中進行的化學氣相沉積(Sub-atmospheric Chemical Vapor Deposition,SACVD)與其他沉積方法。
另外,硬遮罩層145為設置於閘極結構121的頂面上,且硬遮罩層147為設置於閘極結構123的頂面上。硬遮罩層145、147可包含氮化矽或類似材料。硬遮罩層145、147可藉由使用化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、其他適合製程或其組合形成。
然後,形成介電層150於閘極結構121、123與源極汲極結構130上。介電層150為層間介電層(Interlayer Dielectric,ILD)。介電層150之材質為介電材料,例如氧化矽、氮化矽、氮氧化矽或其組合。在一些實施方式中,介電層150之材質為低介電常數介電材料,以提升阻容遲滯(Resistive-Capacitive Delay)。低介電常數介電材料的介電常數低於二氧化矽的介電常數。可以藉由引入碳或
氟原子降低介電材料的介電常數。舉例來說,引入碳原子至二氧化矽,其κ值為3.9,以形成摻雜氫化碳的氧化矽(Hydrogenated Carbon-doped Silicon Oxide),其κ值在2.7至3.3之間,且引入氟原子至二氧化矽以形成氟矽酸鹽玻璃(Fluorosilicate Glass,FSG),其κ值在3.5至3.9之間,因而降低其介電常數。在一些實施方式中,低介電常數介電材料為例如摻雜納米孔碳的氧化物(Nanopore Carbon Doped Oxide,CDO)、黑鑽石(Black Diamond,BD)、苯環丁烯(Benzocyclobutene,BCB)的基礎聚合物、芳香族(烴)熱固性聚合物(Aromatic Thermosetting Polymer,ATP)、氫倍半矽氧烷(Hydrogen Silsesquioxane,HSQ)、甲基倍半矽氧烷(Methyl Silsesquioxane,MSQ)、聚亞芳基醚(Poly-arylene Ethers,PAE)、摻雜氮的類金剛石碳(Diamond-like Carbon,DLC)或其組合。介電層150可藉由例如化學氣相沉積、旋塗或其組合形成。
如第2圖所繪示,於介電層150中形成凹槽151,以裸露間隔層141、143的至少其中之一的至少一部份,同時介電層150的一部分(介電層150d)遺留在源極汲極結構130上,其中位於源極汲極結構130上的介電層150d相鄰於間隔層141、143且設置於間隔層141、143之間。凹槽151為藉由微影與蝕刻製程形成。微影與蝕刻製程包含塗佈光阻、曝光、顯影、蝕刻與移除光阻。光阻藉由例如旋
塗塗佈於介電層150上。接著,光阻被預烤以除去多餘的光阻劑。在預烤後,光阻暴露於具有圖案的強烈光線。
強烈光線為例如波長為約436奈米的G-光線(G-line)、波長為約365奈米的I-光線(I-line)、波長為約248奈米的氟化氪(Krypton Fluoride)準分子雷射、波長為約193奈米的氟化氬(Argon Fluoride)準分子雷射、波長為約157奈米的氟(Fluoride)準分子雷射或其組合。曝光工具的最後透鏡和光阻表面之間的空間在曝光時可以填充具有大於一的折射率的液態介質,以提高微影分辨率。光阻暴露於光線將引起化學變化,使部分光阻可溶於顯影劑。
接著,在顯影前可以進行後曝光烘烤(Post-exposure Bake,PEB),以幫助減少入射光的破壞性和建設性干涉圖案所造成的駐波現象。然後將顯影劑施加到光阻上以移除可溶於顯影劑的部分光阻。然後硬烘烤剩餘的光阻,以固化剩餘的光阻。
沒有被剩餘的光阻保護的至少部分介電層150會被蝕刻而形成凹槽151。蝕刻製程可為乾蝕刻,例如反應式離子蝕刻(Reactive Ion Etching,RIE)、電漿增強(Plasma Enhanced,PE)的蝕刻或感應耦合電漿(Inductively Coupled Plasma,ICP)蝕刻。在一些實施方式中,當介電層150之材質為氧化矽時,可以使用以氟為基礎的反應式離子蝕刻形成凹槽151。用來乾蝕刻介電層150的氣體蝕刻劑可為例如四氟化碳/氧。
在凹槽151形成後,光阻可以藉由例如電漿灰化、剝離或其組合自介電層150移除。電漿灰化使用電漿源產生一種單原子反應性物質,例如氧或氟。反應性物質與光阻結合形成灰分,然後灰分為藉由真空幫浦移除。剝離使用光阻剝離劑,例如丙酮或酚溶劑,以自介電層150移除光阻。
如第3圖所繪示,形成保護層160於位於閘極結構121、123上(或者位於硬遮罩層145、147上)的介電層150(介電層150u)的頂面上、凹槽151的至少一側壁上(即位於介電層150u的至少一側壁與至少部分裸露的間隔層141、143)與凹槽151的底面上(即介電層150d的頂面)。在一些實施方式中,保護層160與介電層150之材質不同。保護層160可包含例如氮化矽、氮氧化矽等。保護層160可藉由原子層沉積製程、其他適合製程或其組合形成。
如第3圖與第4圖所繪示,進行非等向性蝕刻以移除位於介電層150u的頂面上與凹槽151的底面上(即介電層150d的頂面上)的保護層160與介電層150d的一部分,同時使殘留的保護層160與殘留的介電層150d的一部分仍然覆蓋凹槽151的側壁(即介電層150u的側壁與間隔層141、143),且殘留的介電層150d的此部分位於保護層160與源極汲極結構130之間。於是,凹槽151被深化,且深化的凹槽151裸露源極汲極結構130。在一些實施方式中,非等向性蝕刻製程可為乾蝕刻,例如反應式離子蝕刻、電漿增強的蝕刻或感應耦合電漿蝕刻。
如第4圖與第5圖所繪示,過度填充(Overfill)導電層170於凹槽151,以使下導體171形成於凹槽151中,且下導體電性連接源極汲極結構130。導電層170之材質為金屬,例如銅(Copper)、鋁(Aluminum)、鎢(Tungsten)、鎳(Nickel)、鈷(Cobalt)、鈦(Titanium)、鉑(Platinum)、鉭(Tantalum)或其組合。導電層170可藉由例如電化學沉積製程(Electrochemical Deposition)、物理氣相沉積製程、化學氣相沉積製程或其組合形成。
然後,藉由移除製程移除介電層150u、保護層160的上部(保護層160的上部的設置高度大於源極汲極結構121、123的設置高度與硬遮罩層145、147的設置高度)與導體層170的上部(導體層170的上部的設置高度大於源極汲極結構121、123的設置高度與硬遮罩層145、147的設置高度),其中導體層170的上部包含下導體171的上部。
在一些實施方式中,多餘的介電層150u、保護層160與導電層170為藉由化學機械研磨製程(Chemical Mechanical Polishing,CMP)移除。在一些實施方式中,當導電層170之材質為銅時,化學機械研磨製程的研磨液為例如懸浮磨料顆粒、氧化劑與腐蝕抑制劑的混合物,且研磨液為酸性的。兩步驟的化學機械研磨製程可以用來移除多餘的介電層150u、保護層160與導電層170。在第一步驟中,磨料顆粒移除導體層170卻沒有影響介電層150u與保護層160。在第二步驟中,藉由二氧化
矽磨料顆粒移除殘留的介電層150u、保護層160與導電層170。在完成化學機械研磨製程後,保護層160為設置於下導體171和間隔層141之間與下導體171和間隔層143之間。
如第6圖所繪示,形成介電層180於閘極結構121、123、保護層160與下導體171上。介電層180為層間介電層。介電層180之材質為介電材料,例如氧化矽、氮化矽、氮氧化矽或其組合。在一些實施方式中,介電層180之材質為低介電常數介電材料,以提升阻容遲滯。低介電常數介電材料的介電常數低於二氧化矽的介電常數。可以藉由引入碳或氟原子降低介電材料的介電常數。舉例來說,引入碳原子至二氧化矽,其κ值為3.9,以形成摻雜氫化碳的氧化矽,其κ值在2.7至3.3之間,且引入氟原子至二氧化矽以形成氟矽酸鹽玻璃,其κ值在3.5至3.9之間,因而降低其介電常數。在一些實施方式中,低介電常數介電材料為例如摻雜納米孔碳的氧化物、黑鑽石、苯環丁烯的基礎聚合物、芳香族(烴)熱固性聚合物、氫倍半矽氧烷、甲基倍半矽氧烷、聚亞芳基醚、摻雜氮的類金剛石碳或其組合。在一些實施方式中,介電層180與介電層150d之材質大致相同。介電層180可藉由例如化學氣相沉積、旋塗或其組合形成。
如第7圖所繪示,於介電層180中形成開口181,以裸露保護層160的至少一部分與下導體171的至少一部分。開口181為藉由微影與蝕刻製程形成。在一些實施方式中,一層光阻材料(未繪示)形成於介電層180上,然
後依照一圖案(即開口181)照射(曝光)這層光阻材料,並顯影而移除光阻材料的一部分。殘留的光阻材料保護位於其下的材料不受例如蝕刻製程的後續步驟影響。然後,進行蝕刻製程,以形成開口181。
如第8圖所繪示,過度填充(Overfill)導電層190於開口181,然後移除位於開口181外的多餘導電層190。導電層190之材質為金屬,例如銅、鋁、鎢、鎳、鈷、鈦、鉑、鉭或其組合。導電層190可藉由例如電化學沉積製程、物理氣相沉積製程、化學氣相沉積製程或其組合形成。
移除位於開口181外的多餘導電層190為藉由移除製程移除。在一些實施方式中,多餘的導電層190為藉由化學機械研磨製程移除。在一些實施方式中,當導體層190之材質為銅時,化學機械研磨製程的研磨液為例如懸浮磨料顆粒、氧化劑與腐蝕抑制劑的混合物,且研磨液為酸性的。在完成化學機械研磨製程後,形成上導體191(導電層190)於開口181中。上導體191電性連接下導體171,且上導體191直接接觸開口181的至少一側壁。
根據本揭露另一實施方式,半導體結構100包含基板110、閘極結構121、123、間隔層141、143、至少一源極汲極結構130、至少一介電層180、至少一導體193以及至少一保護層160。閘極結構121、123設置於基板110上。間隔層141設置於閘極結構121的至少一側壁上,且間隔層143設置於閘極結構123的至少一側壁上。源極汲極結構130設置
於基板110上且相鄰於間隔層141、143,且源極汲極結構130設置於間隔層141、143之間。介電層180至少設置於閘極結構121、123上,且具有開口181於其中,其中源極汲極結構130至少被開口181裸露。導體193至少藉由開口181電性連接源極汲極結構130。導體193具有上部(即上導體191)與下部(即下導體171),上部位於介電層180的開口181中,下部位於導體193的上部與源極汲極結構130之間。開口181至少部分裸露導體193的下部。保護層160至少設置於導體193的下部和間隔層141之間與導體193的下部和間隔層143之間,且保護層160至少設置於導體193的上部和源極汲極結構130之間。
具體而言,導體193的上部藉由開口181電性連接導體193的下部,且導體193的上部至少覆蓋保護層160。
另外,保護層160設置於導體193的下部和閘極結構121之間與導體193的下部和閘極結構123之間。保護層160沒有設置於導體193的上部與介電層180之間,且保護層160沒有設置於開口181中。換句話說,導體193的上部直接接觸開口181的至少一側壁(即介電層180的至少一側壁)。
具體而言,間隔層141的一部分設置於閘極結構121與導體193的下部之間,且間隔層143的一部分設置於閘極結構123與導體193的下部之間。
具體而言,保護層160之材質為介電材料,例如例如氮化矽、氮氧化矽或其組合。應了解到,以上所舉之保護層160的材質僅為例示,並非用以限制本揭露,本揭
露所屬技術領域中具有通常知識者,應視實際需要,彈性選擇保護層160的材質。
保護層160的高度(即保護層160的頂面與底面之間的距離)可為約5奈米至約2000奈米,且保護層160的寬度(即保護層160的兩側面之間的距離)可為約5埃至約200埃米。應了解到,以上所舉之保護層160的具體實施方式僅為例示,並非用以限制本揭露,本揭露所屬技術領域中具有通常知識者,應視實際需要,彈性選擇保護層160的具體實施方式。
半導體結構100更包含介電層150d。介電層150d至少設置於導體193的下部和間隔層141之間與導體193的下部和間隔層143之間。保護層160設置於介電層150d上方。換句話說,介電層150d設置於保護層160與源極汲極結構130之間。
介電層150d的高度(即介電層150d的頂面與底面之間的距離)可為約5奈米至約1000奈米,且介電層150d的寬度(即介電層150d的兩側面之間的距離)可為約5埃至約100埃。應了解到,以上所舉之介電層150d的具體實施方式僅為例示,並非用以限制本揭露,本揭露所屬技術領域中具有通常知識者,應視實際需要,彈性選擇介電層150d的具體實施方式。
半導體結構100更包含硬遮罩層145、147。硬遮罩層145為設置於閘極結構121的頂面上,且硬遮罩層147為設置於閘極結構123的頂面上。換句話說,硬遮罩層
145設置於閘極結構121與介電層180之間,硬遮罩層147設置於閘極結構123與介電層180之間。
源極汲極結構130更可包含至少一源極汲極應力源。應了解到,以上所舉之源極汲極結構130的具體實施方式僅為例示,並非用以限制本揭露,本揭露所屬技術領域中具有通常知識者,應視實際需要,彈性選擇源極汲極結構130的具體實施方式。
保護層160可以在深化凹槽151時保護間隔層141、143不被過度蝕刻。於是,在形成導體193後,導體193的下部(即下導體171)可以電性絕緣於閘極結構121、123而不會有短路故障且/或漏電的問題。在有保護層160的情況下,器件尺寸將可以在不用給予微影與蝕刻製程巨大負載的情況下進一步縮小,於是器件的效能可以因此提升。進一步來說,疊對(Overlay)與圖案化的負載要求將可減輕。另外,保護層160可以擴大接觸孔形成時的製程容許範圍(Process Window)與改善半導體器件製造製程的產線產品級別控制(In-line Control)。於是,製造半導體器件的穩定性且/或良率可以因此提升。
進一步來說,因為導體193的上部(即上導體191)與下部為在不同步驟中形成,導體193的上部可以直接觸開口181的至少一側壁。換句話說,導體193的上部直接觸介電層180。於是,因為沒有其他元件設置於導體193的上部與介電層180之間,因此導體193的寬度可以更大。
根據本揭露一實施方式,一種半導體結構包含基板、至少一第一閘極結構、至少一第一間隔層、至少一源極汲極結構、至少一第一介電層、至少一導體以及至少一保護層。第一閘極結構設置於基板上。第一間隔層設置於第一閘極結構的至少一側壁上。源極汲極結構相鄰於第一間隔層。第一介電層至少設置於第一閘極結構上,且具有開口於其中,其中開口裸露源極汲極結構。導體電性連接源極汲極結構,其中導體具有上部與下部,上部位於第一介電層的開口中,下部位於上部與源極汲極結構之間。保護層設置於導體的下部和第一間隔層之間與導體的上部和源極汲極結構之間。
根據本揭露另一實施方式,一種半導體結構包含基板、至少一閘極結構、至少一間隔層、至少一源極汲極結構、至少一下導體、至少一保護層、至少一第一介電層以及至少一上導體。閘極結構設置於基板上。間隔層設置於閘極結構的至少一側壁上。源極汲極結構相鄰於間隔層。下導體電性連接源極汲極結構。保護層設置於下導體與間隔層之間。第一介電層至少設置於閘極結構上,且具有開口於其中,其中開口至少部分裸露下導體。上導體藉由第一介電層的開口電性連接下導體,且至少覆蓋保護層。
根據本揭露又一實施方式,一種製造半導體結構的方法包含以下步驟。首先,形成第一介電層於至少一閘極結構與至少一源極汲極結構上。然後,形成至少部分
於第一介電層中的至少一凹槽。接著,形成至少一保護層至少於凹槽的至少一側壁上。然後,深化凹槽,以裸露源極汲極結構。接著,形成下導體於凹槽中,其中下導體電性連接源極汲極結構。然後,移除第一介電層、保護層的上部以及位於閘極結構上的下導體的上部。接著,形成第二介電層於閘極結構與下導體上。然後,於第二介電層中形成至少一開口,以裸露下導體。最後,在開口中形成上導體,其中上導體電性連接下導體。
雖然本揭露已以實施方式揭露如上,然其並非用以限定本揭露,任何熟習此技藝者,在不脫離本揭露之精神和範圍內,當可作各種之更動與潤飾,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
Claims (10)
- 一種半導體結構,包含:一基板;至少一第一閘極結構,設置於該基板上;至少一第一間隔層,設置於該第一閘極結構的至少一側壁上;至少一源極汲極結構,相鄰於該第一間隔層;至少一第一介電層,至少設置於該第一閘極結構上,且具有一開口於其中,其中該開口裸露該源極汲極結構;至少一導體,電性連接該源極汲極結構,其中該導體具有一上部與一下部,該上部位於該第一介電層的該開口中,該下部位於該上部與該源極汲極結構之間;以及至少一保護層,設置於該導體的該下部和該第一間隔層之間與該導體的該上部和該源極汲極結構之間,該導體的該上部接觸並覆蓋該保護層的頂表面。
- 如請求項1所述之半導體結構,更包含:一第二介電層,至少設置於該導體的該下部和該第一間隔層之間與該保護層和該源極汲極結構之間。
- 如請求項2所述之半導體結構,其中該保護層與該第二介電層之材質不同。
- 如請求項2所述之半導體結構,其中該第一介電層與該第二介電層之材質大致相同。
- 一種半導體結構,包含:一基板;至少一閘極結構,設置於該基板上;至少一間隔層,設置於該閘極結構的至少一側壁上;至少一源極汲極結構,相鄰於該間隔層;至少一下導體,電性連接該源極汲極結構;至少一保護層,設置於該下導體與該間隔層之間;至少一第一介電層,至少設置於該閘極結構上,且具有一開口於其中,其中該開口至少部分裸露該下導體;以及至少一上導體,藉由該第一介電層的該開口電性連接該下導體,且接觸並覆蓋該保護層的頂表面。
- 如請求項5所述之半導體結構,其中該保護層沒有設置於該第一介電層的該開口中。
- 如請求項1或5所述之半導體結構,其中該保護層之材質為氮化矽、氮氧化矽或其組合。
- 一種製造半導體結構的方法,包含:形成一第一介電層於至少一閘極結構與至少一源極汲極結構上;形成至少部分於該第一介電層中的至少一凹槽;形成至少一保護層至少於該凹槽的至少一側壁上;深化該凹槽,以裸露該源極汲極結構;形成一下導體於該凹槽中,其中該下導體電性連接該源極汲極結構;移除該第一介電層、該保護層的一上部以及位於該閘極結構上的該下導體的一上部;形成一第二介電層於該閘極結構與該下導體上;於該第二介電層中形成至少一開口,以裸露該下導體;以及在該開口中形成一上導體,其中該上導體電性連接該下導體。
- 如請求項8所述之方法,其中在形成該保護層的步驟中,更形成該保護層的一部分於該凹槽的一底面上,且在深化該凹槽的步驟中,移除設置於該凹槽的該底面上的該保護層的該部分。
- 如請求項8所述之方法,其中該凹槽為藉由非等向性蝕刻深化。
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