TWI621216B - 製作具有絕緣體上覆矽基材之嵌入式記憶體裝置方法 - Google Patents

製作具有絕緣體上覆矽基材之嵌入式記憶體裝置方法 Download PDF

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TWI621216B
TWI621216B TW105126639A TW105126639A TWI621216B TW I621216 B TWI621216 B TW I621216B TW 105126639 A TW105126639 A TW 105126639A TW 105126639 A TW105126639 A TW 105126639A TW I621216 B TWI621216 B TW I621216B
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insulating layer
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堅昇 蘇
曼達娜 塔達尤尼
恩漢 杜
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超捷公司
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Abstract

一種形成半導體裝置之方法，該半導體裝置具有位於該相同絕緣體上覆矽基材上之記憶體單元及邏輯裝置。該方法包括：提供基材，該基材包括矽、直接位於該矽上方的第一絕緣層、及直接位於該第一絕緣層上方的矽層。矽外延生長於該基材之第一(記憶體)區域中而非該基材之第二(邏輯裝置)區域中之該矽層上，以使得該矽層在該基材之該第一區域中比在該基材之該第二區域中更厚。記憶體單元形成於該基材之該第一區域中，且邏輯裝置形成於該基材之該第二區域中。

Description

製作具有絕緣體上覆矽基材之嵌入式記憶體裝置方法 相關申請案之交互參考
本申請案主張於2015年10月7日申請之美國專利臨時申請案第62/238,638號的權利，該案以引用方式併入本文中。
本發明係關於嵌入式非揮發性記憶體裝置。
在塊體矽半導體基材上形成非揮發性記憶體裝置已為人所熟知。例如，美國專利第6,747310號、第7,868,375號及第7,927,994號揭示在塊體半導體基材上形成記憶體單元，記憶體單元含有四個閘(浮閘、控制閘、選擇閘及抹除閘)。源極區及汲極區作為擴散植入區而形成至基材中，從而在基材中在其等之間界定一通道區。浮閘係設置在通道區之一第一部分上方且控制通道區之第一部分，選擇閘係設置在通道區之一第二部分上方且控制通道區之第二部分，控制閘係設置在浮閘上方，且抹除閘係設置在源極區上方。塊體基材對於這些類型記憶體裝置而言為理想的，此係因為深擴散至基材中可用於形成源極區及汲極區接面。為了所有目的，這三個專利以引用之方式併入本文中。
絕緣體上覆矽(SOI)裝置在微電子領域中已為人所熟知。SOI裝置與塊體矽基材裝置差異在於，基材經分層，其中在矽表面下方為一嵌入式絕緣層(即，矽-絕緣體-矽)，而非純粹為矽。運用 SOI裝置，在經設置在嵌入於矽基材中之電絕緣體上方之薄矽層中形成矽接面。該絕緣體一般為二氧化矽(氧化物)。此基材組態減少寄生裝置電容，藉此改良效能。可藉由SIMOX(藉由使用氧離子束植入來植入氧進行分離，請參閱美國專利第5,888,297號及第5,061,642號)、晶圓接合(接合經氧化之矽與一第二基材，且移除大部分第二基材，請參閱美國專利第4,771,016號)，或加晶種(直接在絕緣體上方生長最上層矽層，請參閱美國專利第5,417,180號)，來製造SOI基材。為了所有目的，這四個專利以引用之方式併入本文中。
已知將核心邏輯裝置、高電壓裝置、輸入/輸出裝置、及/或類比裝置形成在與非揮發性記憶體裝置(即，一般稱為嵌入式記憶體裝置)相同之矽基材上。隨著裝置幾何形狀持續縮減，核心邏輯裝置可大幅受益於SOI基材之優點。然而，非揮發性記憶體裝置並不利於SOI基材。有需要結合在SOI基材上形成之核心邏輯裝置與在矽塊體基材上形成之記憶體裝置之優點。
藉由形成半導體裝置之方法來解決前述問題及需要，該方法包括：提供基材，該基材包括矽、直接位於矽上方之第一絕緣層、及直接位於第一絕緣層上方之矽層；在基材之第一區域中而非基材之第二區域中的矽層上外延生長矽，以使得矽層在基材之第一區域中比在基材之第二區域中厚；形成記憶體單元於基材之第一區域中，且形成邏輯裝置於基材之第二區域中。記憶體單元之各者的形成包括：形成隔開的第一源極區及第一汲極區於基材之第一區域中的矽層中，從而在其等之間界定通道區；形成浮閘於通道區之第一部分上方且與之絕緣；及形成選擇閘於通道區之第二部分上方且與之絕緣。邏輯裝置之各者的形成包括：形成隔開的第二源極區及第二汲極區於基 材之第二區域中的矽層中；及形成傳導閘於矽層之一部分上方且與之絕緣，且於第二源極區及第二汲極區之間。
本發明的其他目的與特徵將藉由檢視說明書、申請專利範圍、及隨附圖式而變得顯而易見。
10‧‧‧SOI基材/基材
12‧‧‧下伏(塊體)矽/塊體矽
14‧‧‧絕緣材料層/絕緣體BOX層/絕緣件/BOX層
16‧‧‧薄矽層/薄矽/經曝露矽
16a‧‧‧矽層/經曝露矽
18‧‧‧氧化物層/氧化物
20‧‧‧氮化物層/氮化物
22‧‧‧溝槽
24‧‧‧記憶體區域
26‧‧‧邏輯區域/邏輯裝置區域
28‧‧‧絕緣材料/STI氧化物/STI氧化物堆疊
30‧‧‧第二溝槽
32‧‧‧絕緣材料層/氮化物層
34‧‧‧氧化物層
36‧‧‧多晶矽層/多晶矽/FG多晶矽/浮閘/邏輯區域
38‧‧‧複合絕緣層/ONO絕緣件
40‧‧‧傳導控制閘/控制閘/控制閘多晶矽
42‧‧‧硬遮罩材料/CG硬遮罩/硬遮罩
44‧‧‧隧道氧化物層/氧化物層
46‧‧‧源極接面/源極區
48‧‧‧光阻
50‧‧‧絕緣層
52‧‧‧抹除閘/閘多晶矽
54‧‧‧字線(選擇)閘/閘多晶矽/WL閘/選擇閘
56‧‧‧邏輯閘/傳導閘
58‧‧‧LDD間隔物
60‧‧‧汲極擴散區/汲極區
62‧‧‧源極擴散區/源極區
64‧‧‧汲極擴散區/汲極區
66‧‧‧矽化物層
68‧‧‧通道區
圖1至圖9、圖11、圖13及圖15為依序繪示用以製造本發明之嵌入式記憶體裝置所執行之處理步驟的邏輯區域及記憶體區域之橫剖面側視圖。
圖10、圖12、圖14及圖16為繪示用以製造本發明之嵌入式記憶體裝置所執行之後續處理步驟的記憶體區域之分別正交於圖9、圖11、圖13及圖15之視圖的橫剖面側視圖。
本發明係一種嵌入式記憶體裝置，其具有在SOI基材上形成在邏輯裝置旁之非揮發性記憶體單元。絕緣體上之矽僅在記憶體陣列區域中凸起(即，厚度增強)，而邏輯裝置仍然形成於SOI基材之薄矽層上。凸起的矽允許藉由使用熱氧化、CVD或兩者之組合來形成浮閘氧化物，因為熱氧化將使矽氧化且使其更薄。凸起的矽亦允許形成源極線(SL)接面，該源極線接面足夠深以維持與用於邏輯N+接面相比較高的崩潰電壓。由於較厚的矽及較高的HVII植入能量，SL接面將比邏輯N+接面更深。
藉由提供SOI基材來開始在SOI基材上形成嵌入式記憶體裝置之過程，如圖1中所例示。SOI基材包括三個部分：下伏(塊體)矽12、塊體矽12上方之絕緣材料層14(例如，氧化物-被稱為掩埋氧化物-BOX)、及絕緣體BOX層14上方之薄矽(Si)層16。SOI基材 之形成在所屬技術領域中已為人所熟知，如上文所描述且在上文美國專利中指出，且因此本文中未進一步描述。
氧化物層18(Ox襯墊)形成於薄矽層16上，且氮化物層20(氮化物襯墊)沉積於氧化物層18上，如圖2所示。執行微影程序，其包括：在氮化物層20上形成一光阻材料，後續接著使用一光學遮罩選擇性地使該光阻材料曝光，後續接著選擇性地移除該光阻材料之部分以曝露下伏材料(即，氮化物層20)之部分。微影術在所屬技術領域中已為人所熟知。然後，在光阻使之曝露之彼等部分中執行一系列氮化物、氧化物及矽各向異性蝕刻，以便移除氮化物20之曝露部分、氧化物18、薄矽16、絕緣件14及塊體矽12，從而形成延伸穿過此等層且進入SOI基材10中之溝槽22。額外的氮化物蝕刻(例如，各向同性)經執行以相對於下面的層拉回氮化物層20之邊緣特定拉回量(例如，40至100埃)，以便在氮化物層20處而非在氧化物18處加寬溝槽22。所得結構展示於圖3中(移除光阻後)。溝槽22之間距、寬度及定向在基材10之記憶體區域24(其中將形成記憶體單元)與基材10之邏輯區域26(其中將形成邏輯裝置)之間變化。
然後，溝槽22藉由氧化物沉積及氧化物蝕刻(例如，使用氮化物20作為蝕刻停止的化學機械拋光CMP)填充有諸如CVD氧化物(例如，HDP氧化物-高密度電漿，或HARP氧化物-高縱橫比製程)之絕緣材料28。較佳地，凹入蝕刻用以將STI氧化物28之頂部降低到氮化物層20之頂部以下，從而導致圖4中所示之結構。此STI絕緣材料充當邏輯區域26及記憶體區域24兩者之隔離區。
接著執行氮化物蝕刻以移除氮化物層20，從而留下STI氧化物28之柱體間的第二溝槽30，如圖5所繪示。絕緣材料層32(例如氮化物-蓋帽氮化物)係藉由例如氮化物沉積而經形成於該結構之曝 露表面上方。執行微影程序以在結構上方形成光阻，後續接著遮罩步驟，在遮罩步驟中自記憶體區域24移除光阻，但不自結構之邏輯區域26移除光阻。氮化物蝕刻經執行以自記憶體區域24移除氮化物層32，如圖6所示(移除光阻後)。氧化物蝕刻經執行以在記憶體區域中之第二溝槽的底部處移除氧化物層18。該氧化物蝕刻亦可減小記憶體區域24中之STI氧化物28的高度。氧化物層18藉由邏輯裝置區域26中之氮化物層32保護及維持。然後，矽外延生長於記憶體區域24中之第二溝槽30的底部處之曝露薄矽層16上，以獲得較厚矽層16a，如圖7所示。此矽外延生長有效地增加記憶體區域24中之BOX層14上方的矽層16a之厚度，而不影響邏輯區域26中之BOX層14上方的矽層16之厚度。
然後，使用氧化物形成步驟(例如，氧化)以在記憶體區域24中之加厚矽層16a上形成氧化物層(FG Ox)34(該氧化物層是將在其上形成記憶體單元浮閘之氧化物)。多晶矽形成於該結構上方，後續接著多晶矽蝕刻(例如，CMP)，從而在邏輯區域26及記憶體區域24兩者中之第二溝槽(STI氧化物堆疊28之間)中留下多晶矽層36。微影遮罩步驟用於僅覆蓋記憶體區域24，以使得可執行多晶矽蝕刻來減少邏輯區域26中之多晶矽層36的高度，且使得記憶體區域24及邏輯區域36中之多晶矽層36的厚度近似相等，如圖8所示(移除光阻後)。此允許記憶體區域及邏輯區域兩者中之後續多晶矽蝕刻同時完成20次。若多晶矽層厚度在多晶矽蝕刻(例如，CMP)後已大約相同，則可跳過此步驟。
接下來執行一連串處理步驟以完成在記憶體區域24中的記憶體單元形成，這在所屬技術領域中已為人所熟知。具體地，記憶體區域24中之多晶矽36形成記憶體單元浮閘。可選用的氧化物蝕 刻亦可用於降低記憶體區域24中之STI氧化物28之頂部。利用在多晶矽36及STI氧化物28上方形成複合絕緣層(例如，氧化物/氮化物/氧化物-ONO)38來開始形成記憶體堆疊結構。傳導控制閘(CG)40(例如，多晶矽)形成於記憶體區域24中之複合絕緣層38上及FG多晶矽36上方，且硬遮罩材料42(CG硬遮罩，諸如氮化物或氮化物、氧化物及氮化物之組合層)形成於控制閘40上方。CG硬遮罩42、控制閘多晶矽40、ONO絕緣件38及FG多晶矽36在記憶體單元堆疊蝕刻期間自邏輯區域26移除。然後，隧道氧化物層44形成於記憶體區域24及邏輯區域26兩者中(藉由CVD沉積)。圖9及圖10展示該所得結構(圖10係與圖9之視圖正交的視圖，展示於記憶體區域24中形成之記憶體單元)。
源極接面SL 46形成(例如，植入)於記憶體區域24之相鄰浮閘(FG多晶矽)36之間的厚度增強的矽層16a中(例如，使用圖案化光阻以防止植入基材10之其他曝露區域中)。然後，形成部分地覆蓋成對的記憶體單元之光阻48(藉由微影曝露及選擇性移除光阻)。然後執行氧化物及氮化物蝕刻以移除氧化物層18及44及氮化物層32之未由光阻保護的部分，從而曝露SOI基材10之邏輯區域26的薄矽層16。氧化物層44之間隔物仍然沿浮閘36、控制閘40及硬遮罩42之側壁。圖11及圖12展示所得結構。
移除光阻48後，絕緣層50(例如，氧化物)然後藉由例如熱氧化來形成於邏輯區域26中之經曝露矽16及記憶體區域24中之經曝露矽16a上。然後，一層多晶矽被沉積且被回蝕，以於源極區46上方形成抹除閘(EG)52、於記憶體區域24中的浮閘36之另一側上形成字線(選擇)閘54、及於邏輯區域26中形成邏輯閘56(使用微影圖案化及蝕刻製程)。較佳地，此等多晶矽閘形成如下。首先，一層多晶矽 經沈積於結構上方。於多晶矽上沉積保護絕緣體諸如氧化物。藉由利用微影圖案化及氧化物蝕刻製程，該保護氧化物於記憶體區域24中被移除，但不被從邏輯區域26中移除。然後，虛設多晶矽沉積於該結構上方。使用多晶矽CMP及回蝕製程以於記憶體區域24中形成閘多晶矽52/54。(一旦移除虛設多晶矽)邏輯區域26中之保護氧化物阻止該多晶矽蝕刻及回蝕製程影響邏輯區域26中之多晶矽。然後，使用微影及蝕刻製程以於邏輯區域26中圖案化多晶矽以形成邏輯閘56，並以完成記憶體區域24中之WL閘54的形成。所得結構展示於圖13及圖14中。
接著執行至基材10中之LLD植入，其後續接著沿記憶體區域24中之WL閘54形成LDD間隔物58(例如，氧化物)。然後執行N+植入以完成汲極擴散區60在相鄰於記憶體區域24中之WL閘54的基材中之形成，及源極區62及汲極擴散區64在薄矽層16中之形成，以便完成邏輯區域26中之邏輯裝置。結構之經曝露多晶矽及矽部分可曝露於金屬化製程，以形成針對增強傳導性之矽化物層66。圖15及圖16中展示最終結構。
於記憶體區域24中，源極區46及汲極區60在其等之間界定通道區68，有浮閘36經設置在通道區68之第一部分上方且控制通道區68之第一部分，且選擇閘54經設置在通道區68之第二部分上方且控制通道區68之第二部分。這些記憶體單元之形成在所屬技術領域中已為人所熟知(請參閱美國專利第6,747310號、第7,868,375號及第7,927,994號，該等案以引用之方式併入本文中)且本文中未進一步描述。記憶體單元各具有一浮閘36、控制閘40、源極區46、選擇閘54、抹除閘52及汲極區60。於邏輯區域中，每一邏輯裝置包括傳導閘56、源極區62及汲極區64。
上述製造製程於相同SOI基材上形成記憶體單元及邏輯裝置，其中SOI基材之嵌入式絕緣體層上的矽層之厚度相對於邏輯區域中之矽層被擴大。此組態允許記憶體單元之源極區及汲極區比邏輯區域中之源極區及汲極區更深地延伸至矽中，以維持與用於邏輯N+接面之崩潰電壓相比較高的崩潰電壓。該製程亦允許該相同多晶矽沉積製程於記憶體區域中形成抹除閘及選擇閘，並於邏輯區域中形成邏輯閘。凸起的矽允許藉由使用熱氧化、CVD或兩者之組合來形成浮閘氧化物，因為熱氧化將使矽氧化且使其更薄。由於較厚的矽及較高的HVII植入能量，SL接面將比邏輯N+接面更深。
應理解，本發明不限於上文描述及本文闡釋之實施例。例如，本文中對本發明的引述並非意欲用以限制任何申請專利範圍或申請專利範圍用語之範疇，而僅是用以對最終可由一或多項請求項所涵蓋的一或多種特徵作出引述。上文描述之材料、程序及數值實例僅為例示性，且不應視為對申請專利範圍之限制。此外，並非所有方法步驟都需要以所例示之確切順序執行，而是以允許本發明之記憶體單元區域及邏輯區域的適當形成之任何順序執行。相較於上文描述及圖式中繪示者，記憶體單元可包括額外或較少閘。例如，記憶體單元可排除控制閘及/或抹除閘。最後，單一材料層可形成為多個具有同樣或類似材料之層，且反之亦然。
應注意的是，如本文中所使用，「在...上方(over)」及「在...上(on)」之用語皆含括性地包括了「直接在...之上」(無居中的材料、元件或間隔設置於其間)及「間接在...之上」(有居中的材料、元件或間隔設置於其間)的含意。同樣，用語「相鄰(adjacent)」包含了「直接相鄰(directly adjacent)」(無居中的材料、元件或間隔設置於其間)和「間接相鄰(indirectly adjacent)」(有居中的材料、元件或間隔 設置於其間)。例如，「在一基材上方」形成一元件可包括直接在基材上形成元件而其間無居中的材料/元件存在，以及間接在基材上形成元件而其間有一或多個居中的材料/元件存在。

Claims (8)

  1. 一種形成一半導體裝置之方法，其包含：提供一基材，該基材包括矽、直接位於該矽上方的一第一絕緣層、及直接位於該第一絕緣層上方的一矽層；在該基材之一第一區域中而非該基材之一第二區域中的該矽層上外延生長矽，以使得該矽層在該基材之該第一區域中比在該基材之該第二區域中厚；形成記憶體單元於該基材之該第一區域中，其中該等記憶體單元之各者之該形成包括：形成隔開的第一源極區及第一汲極區於該基材之該第一區域中的該矽層中，從而在其等之間界定一通道區，形成一浮閘於該通道區的一第一部分上方且與之絕緣，以及形成一選擇閘於該通道區的一第二部分上方且與之絕緣；形成邏輯裝置於該基材之該第二區域中，其中該等邏輯裝置之各者之該形成包括：形成隔開的第二源極區及第二汲極區於該基材之該第二區域中的該矽層中，及形成一傳導閘於該矽層的一部分上方且與之絕緣，且於該第二源極區及該第二汲極區之間。
  2. 如請求項1之方法，其中該第一源極區及該第一汲極區比該第二源極區及該第二汲極區更深地延伸至該矽層中。
  3. 如請求項1之方法，其中該第一源極區及該第一汲極區各具有一崩潰電壓，該崩潰電壓大於該第二源極區及該第二汲極區之各者的崩潰電壓。
  4. 如請求項1之方法，其中該等記憶體單元之各者之該形成進一步包含：形成一控制閘於該浮閘上方且與之絕緣；以及形成一抹除閘於該第一源極區上方且與之絕緣。
  5. 如請求項4之方法，其中該等傳導閘、該等選擇閘及該等抹除閘之該形成進一步包含：形成一多晶矽層，該多晶矽層沿該基材之該第一區域及該第二區域延伸；以及選擇性地移除該多晶矽層之部分，以使得該多晶矽層於該基材之該第一區域中之剩餘部分構成該選擇閘及該抹除閘，且該多晶矽層於該基材之該第二區域中之剩餘部分構成該傳導閘。
  6. 如請求項1之方法，其中該外延生長進一步包含：形成一第二絕緣層於該基材之該第一區域及該第二區域中之該矽層上方；自該基材之該第一區域移除該第二絕緣層，同時將該第二絕緣層保持在該基材之該第二區域中；執行一外延生長製程，該外延生長製程於該基材之該第一區域中之該矽層上而非於該基材之該第二區域中之該矽層上生長該矽；以及 自該基材之該第二區域移除該第二絕緣層。
  7. 如請求項1之方法，其中該外延生長進一步包含：直接形成一第二絕緣層於該基材之該第一區域及該第二區域中之該矽層上；直接形成一第三絕緣層於該基材之該第一區域及該第二區域中之該第二絕緣層上；形成溝槽於該基材之該第一區域及該第二區域中，該等溝槽各延伸穿過該第三絕緣層、該第二絕緣層、該矽層、該第一絕緣件，且進入該矽中；利用一絕緣材料至少部分地填充該等溝槽；自該基材之該第一區域及該第二區域移除該第三絕緣層；形成一第四絕緣層於該基材之該第一區域及該第二區域中之該第二絕緣層上方；自該基材之該第一區域移除該第四絕緣層，同時將該第四絕緣層保持於該基材之該第二區域中；自該基材之該第一區域移除該第二絕緣層；執行一外延生長製程，該外延生長製程於該基材之該第一區域中之該矽層上而非於該基材之該第二區域中之該矽層上生長該矽；以及自該基材之該第二區域移除該第四絕緣層。
  8. 如請求項7之方法，其中該形成溝槽進一步包含： 執行一各向同性蝕刻以在該第三絕緣層處而非在該第二絕緣層處加寬該等溝槽。
TW105126639A 2015-10-07 2016-08-19 製作具有絕緣體上覆矽基材之嵌入式記憶體裝置方法 TWI621216B (zh)

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