TWI620292B - 帶有背側導電板的射頻晶粒封裝技術 - Google Patents

帶有背側導電板的射頻晶粒封裝技術 Download PDF

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Publication number
TWI620292B
TWI620292B TW105101513A TW105101513A TWI620292B TW I620292 B TWI620292 B TW I620292B TW 105101513 A TW105101513 A TW 105101513A TW 105101513 A TW105101513 A TW 105101513A TW I620292 B TWI620292 B TW I620292B
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die
cavity
dielectric
package
board
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TW105101513A
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TW201709445A (zh
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泰勒斯弗 坎嘉因
特羅斯登 梅耶爾
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英特爾公司
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Abstract

描述一種用於具有背側導電板之射頻晶粒的封裝件。一實施例包括一導電板；有一前側及一背側的一半導體晶粒，該背側附接至該板；附接至該板的一射頻組件；在該板中鄰近該射頻組件的一充填電介質空腔；以及附接至該晶粒之該前側用於外部連接的一再分布層。

Description

帶有背側導電板的射頻晶粒封裝技術
本揭示內容係有關於封裝半導體晶粒，特別是有關於一種帶有背側金屬化物的封裝件。
含有射頻電路(例如，基頻帶及RF(射頻)IC(積體電路)的半導體晶粒由於射頻電路產生熱及電磁波，因此難以封裝及整合於極小電子裝置中。射頻電路晶粒封裝於QFN(無鉛四邊扁平)封裝件及有實心金屬片以覆蓋晶粒背側(背側金屬化物)的其他封裝件中。該背側金屬化物用作屏蔽(例如，EMI(電磁干擾)屏蔽)以保護其他快速切換裝置。該背側金屬化物也可用作需要高功率消耗之射頻電路晶粒(例如，PMIC(電源管理積體電路)及PA(功率放大器))的散熱器。
在持續推動小型化的趨勢下，要做出更薄的晶體及其封裝件。目前晶粒可減薄到50微米或更小的高度。在此厚度下，半導體晶粒的電路接近背側金屬化物足以受它影響。晶粒背側上的實心金屬片變成有害於任何RF電路，例如PA、LNA(低雜訊放大器)、VCO(電壓受控振蕩器)、混合器等等。大金屬片減少在晶粒上之任何電感器或變壓器 的電感及品質因素(Q)。這些組件常用於射頻電路。電感及Q減少可能導致頻率偏移，雜訊增加，以及輸出功率減少。若無該背側金屬化物，該晶粒可能翹曲、龜裂、過熱或遭受其他問題。
本發明之一實施例，係特地提出一種半導體封裝件，其係包含：一導電板；有一前側及一背側的一半導體晶粒，該背側附接至該板；附接至該板的一射頻組件；在該板中鄰近該射頻組件的一充填電介質空腔；以及附接至該晶粒之該前側用於外部連接的一再分布層。
2‧‧‧主機板
14‧‧‧晶片組
4‧‧‧處理器
16‧‧‧天線
6‧‧‧通訊晶片
18‧‧‧觸控螢幕顯示器
8‧‧‧揮發性記憶體
20‧‧‧觸控螢幕控制器
9‧‧‧非揮發性記憶體
22‧‧‧電池
10‧‧‧大容量儲存裝置/大容量記憶體
24‧‧‧功率放大器
26‧‧‧全球定位系統(GPS)裝置
11‧‧‧計算裝置
28‧‧‧羅盤
12‧‧‧圖形處理器
30‧‧‧揚聲器
32‧‧‧相機
242‧‧‧離散IPD(積體被動裝置)晶粒
102‧‧‧封裝件
104‧‧‧多層晶粒黏接薄膜(DAF)
244‧‧‧貫通空腔
106‧‧‧超薄SOC(系統晶片)晶粒
246‧‧‧電介質空腔
108‧‧‧RF區段
248‧‧‧通孔
110‧‧‧金屬載體/背側金屬化物層
302‧‧‧堆疊封裝晶粒
112‧‧‧封閉或貫通空腔
304‧‧‧晶粒黏接薄膜
120‧‧‧通孔
306‧‧‧下層晶粒
122‧‧‧電介質
306‧‧‧半導體晶粒
124‧‧‧附加通孔
310‧‧‧金屬屏蔽/金屬片
126‧‧‧扇出層或再分布層
322‧‧‧電介質
128‧‧‧焊料中止層
326‧‧‧扇出或再分布層
130‧‧‧焊球
328‧‧‧焊料中止層
202‧‧‧封裝件
330‧‧‧球柵陣列
204‧‧‧晶粒黏接薄膜
340‧‧‧貫通空腔/電介質黏合材料
206‧‧‧半導體晶粒/超薄數位晶粒
342‧‧‧通孔桿
210‧‧‧導電板/金屬載體
348‧‧‧焊球
220‧‧‧通孔
350‧‧‧其他晶粒或封裝件
222‧‧‧電介質
352‧‧‧通孔
224‧‧‧附加通孔
360‧‧‧連接焊墊
226‧‧‧扇出層
362‧‧‧跡線
228‧‧‧阻焊層
370‧‧‧RF區段
230‧‧‧焊球陣列
372‧‧‧封閉或貫通充填電介質空腔
240‧‧‧離散RFIC(射頻積體電路)晶粒
504‧‧‧金屬片
506‧‧‧封閉空腔
508‧‧‧電介質材料
510‧‧‧晶粒黏接薄膜
608‧‧‧電介質材料
512‧‧‧半導體晶粒
610‧‧‧鈍化層
514‧‧‧RF或被動裝置區段
612‧‧‧半導體晶粒
516‧‧‧介電層
614‧‧‧RF或被動裝置區段
518、520‧‧‧通孔
616‧‧‧介電層
522‧‧‧導電材料
618、620‧‧‧通孔
524‧‧‧再分布層或扇出層
622‧‧‧導電材料
526‧‧‧焊料中止層
624‧‧‧再分布層或扇出層
528‧‧‧焊球
626‧‧‧焊料中止層
604‧‧‧板
628‧‧‧焊球
606‧‧‧開放空腔
本發明的具體實施例是為了舉例圖解說明而不是為了限制，附圖中類似的元件用相同的元件符號表示。
圖1的剖面側視圖根據一具體實施例圖示具有一電介質空腔的封裝件。
圖2的剖面側視圖根據一具體實施例圖示有兩個電介質空腔的替代封裝件。
圖3的剖面側視圖根據一具體實施例圖示有一電介質空腔及數個通孔桿的堆疊晶粒封裝件。
圖4根據一具體實施例圖示沿著圖3封裝件之直線4-4繪出的底部剖面圖。
圖5A至圖5J的剖面側視圖根據一具體實施例圖示用於製造有電介質空腔之封裝件的一序列製造階段。
圖6A至圖6J的剖面側視圖根據一具體實施例圖 示用於製造有電介質空腔之替代封裝件的一序列製造階段。
圖7的方塊圖根據一具體實施例圖示含有受測半導體晶粒的計算裝置。
扇出WLB(晶圓級球柵陣列)封裝件有覆蓋著模塑化合物的晶粒。該模塑化合物保護晶粒而不使薄晶粒的RF(射頻)效能劣化。不過，該模塑化合物不提供健壯的支撐供防止晶粒翹曲而且對於需要顯著熱消耗的晶粒可能導熱不足夠。因此，基於可靠性理由，WLB封裝件通常使用較厚的晶粒，例如50微米或更多。
可修改扇出WLB封裝件用於打薄的晶粒(例如30-50微米)。可用單層或多層晶粒黏接薄膜(die attach film)安裝該晶粒於特殊金屬載體上。該金屬載體可經加工成有所欲CTE(熱膨脹係數)。相較於模製晶粒封裝件，該金屬載體提供改良的可靠性及減少的翹曲。對於PMIC晶粒及不含晶片上電感被動組件的其他晶粒，此一改良封裝件效果不錯。
帶有背側金屬載體的扇出WLB封裝件改善可靠性以及減少PMIC及數位電路的封裝成本。該背側金屬載體影響在金屬載體附近之電感組件的效能。更特別的是，在金屬載體平面中產生之虛部電流(image current)的流動方向與電感組件的主電流相反且以此方式促成電感減少。可在金屬層中形成空腔，封閉或貫通的空腔，然後填上電介 質。這可擴大金屬接地層與RF電路的分離，改善電感組件的電性效能。保有改良可靠性及減少翹曲的效益。結果，可使晶粒及封裝件更薄些。
該背側金屬載體也可用來改善晶粒及封裝件的整體熱效能。在3D及緊湊系統封裝件的情形下，該背側金屬載體可用作屏蔽以及結合接地通孔以提供EMI隔離。
該金屬載體使得有可能大幅減少封裝件的成本以及使得有可能做出更薄的封裝件。晶粒厚度可減少到20微米或更小以及背側金屬厚度可減少到30微米或更小。此類極薄封裝件可彎曲。這對於可穿戴計算裝置或其他小型可攜式裝置可能很有用。
圖1的剖面側視圖圖示有背側金屬化物層110的封裝件102。它包含在RF區段(RF section)108中有一或更多積體RF電路的超薄SOC(系統晶片)晶粒106。該晶粒使用多層晶粒黏接薄膜(DAF)104裝在金屬載體(背側金屬)110上面。該DAF可為單層或多層。如圖示，晶粒的背側係面向背側金屬。
背側層110經選定成可提供結構強度給整體封裝件以及與晶粒類似的CTE。此外，為了屏蔽，該背側層應導電，以及為了冷卻，該背側層應導熱。結果，該背側層的形式可為導電板。該等金屬提供容易加工成本低的導電板材料。因此，該背側層可稱為背側金屬化物或金屬片。不過，本發明不受限於此。可使用有抗撓及及防翹曲之高楊氏模數和適當CTE的任何材料。矽封裝基板不適用於此 用途。不過，聚合物板，以及陶瓷(例如，低溫共燒陶瓷)有在適當範圍內的CTE，它接近晶粒基板的CTE。如果該聚合物或陶瓷不導電，則可添加導電層(未圖示)至該背側層使得該背側層為導電板。
該晶粒的前側有覆蓋於電介質122中的晶粒焊墊圖案。通孔120圖案使該等晶粒焊墊連接至扇出層(fan-out layer)或再分布層(redistribution layer)126。該再分布層被焊料中止層128覆蓋且連接至焊球130或另一連接陣列以使該晶粒連接至外部組件。可形成穿過該電介質的附加通孔124以連接至背側金屬化物110以便隔離、屏蔽等等。該等晶粒焊墊或焊墊的外部連接可用各種不同方式。在一些具體實施例中，使用ePLB(埋藏式面板級球柵陣列)或eWLB(埋藏式晶圓級球柵陣列)製程來形成該封裝件。
在晶粒的RF區段108正下方的背側金屬化物中形成填滿不導電材料(例如，電介質)的封閉或貫通空腔112。該不導電材料(電介質)層可經選定成具有低損耗正切(loss tangent)和低電介質常數兩者。該層可由各種不同材料製成，可包括環氧樹脂，聚亞醯胺，液晶聚合物(LCP)或其他合適材料，包括許多已常用於封裝的電介質材料。
該等晶片上電路，例如RF區段108的電感器、變壓器、電容器、電阻器、放大器及其他組件，通常形成於晶粒的前側上。結果，它們與背側金屬分開有晶粒的背側(塊矽)厚度。空腔深度及晶粒厚度一起界定晶片上電感器與金屬平面的離距。為了得到與QFN封裝件類似的穩定度， 此組合厚度可大於150微米。可設計其他的實作以滿足其他效能準則。
可為獨立晶片或如圖1所示SoC晶粒之一部份的典型射頻收發器可具有大小在約200微米x200微米至約1毫米x1毫米之間的數個電感器及變壓器。可形成隔離個別電感組件的電介質空腔112。在此情況下，該空腔可比特定目標電感組件寬些的50微米或更多。替換地，充填電介質空腔112可標定成能覆蓋SoC晶粒的整個RF區段108。在此情形下，空腔的大小可取決於RF區段的大小。這通常在約0.5毫米x0.5毫米至約3毫米x3毫米之間。不過，本發明不受限於此。
圖2圖示有半導體晶粒206的類似封裝件202。該晶粒的背側使用晶粒黏接薄膜204附接至由金屬、陶瓷、聚合物或其他材料製成的導電板210，以及該晶粒的前側有通過通孔220耦合至扇出層226的焊墊陣列。該扇出層覆蓋於有用於焊球陣列230(例如，BGA(球柵陣列))之連接焊墊的阻焊層228中。該晶粒被在晶粒黏接薄膜與扇出層之間的電介質222覆蓋。
該晶粒可包含RF區段與在金屬片210中的對應毗鄰充填電介質空腔，如圖1所示。取決於特別實作，RF區段可安置在晶粒前側上的任何所欲位置。儘管在此實施例未圖示RF區段，然而它們可用與圖1實施例相同的方式形成。
至於附加機能，此封裝件202包含離散RFIC(射頻 積體電路)晶粒240與離散IPD(積體被動裝置)晶粒242。該IPD可包含各種不同的被動組件，例如電感器、電容器、電阻器、以及變壓器。該等晶粒中之一或更多可在各種不同的位置。該等晶粒有面向扇出層之前側上的電路以及穿過電介質的通孔248以使晶粒上的焊墊連接至扇出層。該等晶粒可從該扇出層耦合至主晶粒206，相互耦合，或耦合至其他外部組件。附加通孔224通過電介質或扇出層使金屬片210耦合至接地或其他穩定電壓。
在圖1的實施例中，單一晶粒106可為囊封於電介質、金屬片之間的完整或部份系統。取決於系統的預期機能，可能有附加晶粒。圖2圖示一些附加晶粒。這些可用來實作主晶粒的功能以提供在封裝件中的完整或部份系統。替換地，該RFIC或IPD可用來支援主晶粒的RF功能或I/O(輸入/輸出)功能。
圖2的剖面側視圖圖示SiP(系統級封裝)的示範具體實施例。諸如基頻帶晶粒、應用處理器、PMIC(電源管理積體電路)或SoC(系統晶片)之類的超薄數位晶粒206裝在金屬載體210上。含有RFIC、功率放大器或IPD的射頻組件完全或部份裝在對應充填電介質空腔的上方。該空腔填料經工程設計成有特定的電氣或熱-機械性質以適合特別的晶粒及其預期用途。一起形成2D SiP/無線模組，其中射頻晶粒都放在充填電介質封閉或貫通空腔上方。
為了增強圖2附加晶粒的效能，在緊挨著各個晶粒的金屬片中形成電介質區。有兩個不同類型的電介質 區。各個可使用於晶粒類型中之一或兩者上。以實施例展示不同的類型。在一實施例中，如圖1所示，使用相同類型的空腔112。如圖示，在金屬片210中形成鄰近IPD晶粒242的空腔。然後，此空腔填滿電介質材料以形成電介質空腔246。此一空腔可使用於任一或這兩個晶粒。
在另一實施例中，在鄰近RFIC的位置鑽鑿、蝕刻或機械加工穿過金屬片的孔。然後，該孔填滿電介質以形成電介質的貫通空腔244。儘管空腔244在此橫截面圖中圖示成一路延伸穿過金屬片，然而晶粒及空腔通常與金屬片不一樣寬使得空腔從上面或底面觀看為矩形。晶粒常常為矩形，不過，空腔可做成適合於毗鄰晶粒之RF或被動區段的任何形狀。
空腔的大小可基於晶粒的整體大小或只基於將會與金屬片隔離之組件的位置。例如，如果該IPD包含在一區中的數個變壓器以及在沒有變壓器之另一區中的數個電阻器，則在只對應至變壓器的位置及尺寸中形成空腔。替換地，空腔可經製作成有對應至整個晶粒的的大小，如圖示。
空腔大小的調整可基於將會附接至該板的晶粒。例如，用於大SoC晶粒的空腔大小可在約200微米平方至約3毫米平方之間。對於厚背側金屬化物板(例如300微米)，空腔的深度可約150微米或更小。對於薄背側金屬化物(例如10-100微米)，可能沒有足夠的空間提供充分的隔離。貫通空腔244可用來提供晶粒與金屬的充分距離。
圖3為堆疊封裝晶粒302的剖面側視圖，其中貫通空腔340用來使得薄晶粒封裝件有可能使用於3-D堆疊。在此矯形下，通孔桿(via bar)342都裝在空腔內以致能其他晶粒或封裝件350的堆疊，例如記憶體或微處理器。該背側金屬化物層本質上提供封裝件的金屬屏蔽310以及提供堆疊晶粒的EMI隔離。以此方式，也可去除外部屏蔽的任何需要。3D SiP可以此方式構造成在下層晶粒306與堆疊封裝件或晶粒350之間有完全的電氣隔離。
更詳細地考慮該封裝件，半導體晶粒306(例如，處理器、SoC或任何其他類型的半導體晶粒)的背側使用晶粒黏接薄膜304附接至金屬片310或其他合適背側層材料。該晶粒可具有RF或被動裝置區段，以及這些區段可用充填電介質空腔與金屬片隔離，如圖1所示。晶粒的前側覆蓋於電介質322中。形成穿過電介質的通孔以使晶粒的前側耦合至扇出或再分布層326。該再分布層有焊料中止層328及球柵陣列330或其他外部連接結構。
與圖1及圖2相比，圖3的封裝件302經組配成可支撐在晶粒背側上方及在封裝件之金屬片上方的第二晶粒或封裝件。在任何所欲位置可鑽鑿、機械加工或蝕刻穿過金屬片的大孔。如圖示，在晶粒的相對兩側上各有矩形開孔。該等貫通孔橫向與晶粒隔開使得它們可連接至再分布層而不影響晶粒。各孔填滿用電介質黏合材料340固定位置的預形成通孔桿342。通孔桿342有形成於電介質中的通孔352圖案而且大小經製作成可附接至大貫通孔。儘管在此以桿來 描述，然而也可使用有任何其他的通孔組態。替換地，與通孔桿之通孔類似的通孔可個別形成於金屬片中而不是預形成及附接。
通孔桿的通孔在晶粒之反側上有對應焊墊陣列以連接至連接至第二封裝件或晶粒350的焊球348。該等通孔也通過晶粒黏接薄膜304連接至穿過覆蓋第一晶粒之電介質322的通孔。該等通孔允許通過球柵陣列330至外部組件的連接以及也允許通過扇出層326和第一通孔320集合至第一晶片的連接。
例如，上層封裝件可為在第一晶粒上方的記憶體封裝件。該第一晶粒可為處理器。該記憶體封裝件可使用通孔桿連接至外部電源以及也使用通孔桿及扇出層連接至該處理器。該封裝件可經構造成有不同的記憶體封裝件以適合不同需要及預算。該記憶體封裝件與處理器晶粒用金屬片屏蔽。
如圖1所示，第一晶粒306可包含一或更多RF區段370以及背側金屬化物310可包含封閉或貫通充填電介質空腔372，如圖1的實施例所示。此外，可能有如圖2所示附接至背側金屬化物及對應附加空腔的附加RFIC或IPD晶粒(未圖示)。
圖4為圖3封裝件從底部穿過直線4-4繪出的底部剖面圖，其中移除在金屬片上面的電介質以及晶粒黏接薄膜呈透明。中央主晶粒306圖示成其附接至有晶粒黏接薄膜(未圖示)的金屬片310。通孔桿342形成於晶粒306的相對兩 側上。該等通孔桿有大量貫穿通孔352用於外部連接或連接至晶粒或兩者。
用於解釋目的，一些連接焊墊360通過扇出層326中的跡線362連接至對應通孔352。此通孔會通過金屬片310中的通孔桿342提供穿過電介質322(未圖示)到上層封裝件或晶粒350的連接。儘管只圖示只連接至一些連接焊墊的一些跡線，然而可能有更多。晶粒上的連接焊墊可集中在一起或如圖示分散於晶粒上。該等跡線圖示成可顯示該等通孔桿如何連接至晶粒而且不是穿過直線4-4之底部橫截面的確切部份。
圖5A至圖5J圖示一序列製造階段用於製造如在圖1背景下所述具有用於RF或被動區段之空腔的封裝件。圖示製程使用封閉空腔。圖5A以金屬片504開始。可使用提供合適EMI屏蔽的任何金屬，例如銅、鋁、鈦及彼等之合金。替換地，該板可由提供充分EMI屏蔽作用的聚合物或陶瓷形成。在圖5B中，用鑽鑿、蝕刻、衝壓或軋製形成一或更多封閉空腔506於板中。替換地，對於陶瓷或聚合物材料，空腔的形成可為模造或鑄造該板的一部份。
在圖5C中，空腔填滿電介質材料508。該電介質可用各種不同的方式施加，包括印刷、旋塗、層疊或分配。在圖5D中，晶粒黏接薄膜510施加於封閉空腔的開口側上面。該晶粒黏接薄膜可由各種不同材料中之任一製成。該晶粒黏接薄膜也可選擇合適用於晶粒之鈍化層的材料。替換地，可首先施加鈍化層於該板，接著用黏著劑作為黏晶 層。該鈍化層為視需要層，它未圖示於一些其他附圖但是可使用所述實作中之任一。
在圖5E中，包含一或更多RF或被動裝置區段514的半導體晶粒512使用晶粒黏接薄膜附接至板504。該晶粒的背側附接至該板使得前側的連接在該板的反側上暴露。該晶粒黏接薄膜可施加於鈍化層上方，晶粒上方或兩者上方。該晶粒附接至該板使得RF區段514在充填電介質空腔正上方。儘管只圖示一個晶粒，然而如圖2所示，可附接多個不同類型的晶粒以支撐主晶粒或提供SiP及其他應用的附加機能。
如圖示，該晶粒比該板薄。該晶粒的厚度取決於整體封裝件的所欲厚度。該板的厚度取決於該板的所欲強度及其EMI屏蔽性質。該板可用來物理支撐及加強晶粒的剛性及強度使得可減薄封裝件的晶粒而不是該板。對於典型的薄封裝件，可減薄晶粒使得板厚兩倍於晶粒或更多。
在圖5F中，施加介電層516於晶粒的前側上面。該電介質可為各種不同材料中之任一，包括模造物或樹脂，環氧樹脂，或聚合物。可以一或更多層地層疊該介電層於晶粒上面或用另一種方式施加。該晶粒此時埋藏或囊封於該電介質中。
在圖5G中，用雷射、蝕刻或其他方式鑽出穿過該電介質的通孔。圖示兩種類型的通孔。第一種通孔520是從介電層上面向下到該板。這允許該板被充電或接地用於EMI及其他目的。在圖2的實施例中，此一通孔允許連接至 要堆疊於第一晶粒(如圖5G所示，在金屬片下面)上面的另一晶粒或封裝件。第二種通孔518從介電層上面鑽到晶粒的連接焊墊以允許晶粒連接至外部組件以及在同一個封裝件中的其他晶粒。儘管只圖示一些通孔，然而取決於晶粒的類型及其預期應用，可能有數百或數千個通孔。
在圖5H中，鑽成通孔填滿或塗上導電材料522，例如銅，以及形成再分布層或扇出層524於該電介質上面。該再分布層可由數個導電跡線形成，例如銅跡線，彼等的圖案化用微影技術、印刷或使用任何其他所欲圖案化技術。該再分布層允許封裝件的晶粒互相連接及連接至外部組件。
該再分布層也可讓連接從它們在晶粒上的位置重新定位到用於外部連接的更合適位置。可能一個以上的再分布層以提供更複雜的外部連接分布。在此情況下，施加第二層電介質於第一再分布層上面。在電介質中形成數個通孔以及形成另一導電再分布圖案於該電介質及該等通孔上面。按需要，可重覆這種分層法以適合任何特定實作。
在圖5I中，形成及構造在上再分布層上面的焊料中止層526。在圖5J中，施加或圖案化焊錫、或焊錫膏或焊劑於焊料中止層上面以及施加焊球528於焊料中止層上面。該等焊球允許晶粒及該板(視需要)連接至外部組件。不過，完成圖5J的封裝件可添加附加製程。冷卻裝置可附接至金屬片。藉由鑽鑿穿過該板以形成附加通孔，可添加附加晶粒至在晶粒反側的金屬片，如圖4所示。也可進行其他 附加製程。完成封裝件可附接至將會封裝其他封裝件之較大封裝件的插座、電路板或封裝基板。
圖6A至圖6J圖示用於製造封裝件的一序列製造階段，該封裝件有用於RF區段的貫通孔或開放空腔，如在圖2的背景下所述。圖示製程使用用於單一晶粒的單一開放空腔。該製程與圖5A至圖5J的類似。不過，如同圖5A至圖5J，可修改該等操作以適合不同的大小、組態及晶粒個數。此外，儘管只圖示一些特徵，然而可能有更多空腔、通孔、層及其他結構以適合不同應用。圖6A以形式為板604的EMI屏蔽或加強材開始。在圖6B中，用鑽鑿、蝕刻、衝壓、軋製、模製、鑄造等等，在該板用形成一或更多開放空腔606。如圖示，該空腔從上到下延伸穿過該板。在封閉空腔不夠深時，此一開放空腔特別適用於較薄的板。
在圖6C中，該空腔填滿電介質材料608。在圖6D中，施加鈍化層610於封閉空腔的開口側上面。可首先施加該鈍化層至該板，接著是黏上黏晶層。替換地，可能只有黏晶層。
在圖6E中，包含一或更多RF或被動裝置區段614的一或更多半導體晶粒612使用晶粒黏接薄膜附接至板604。替換地，該RF區段可為不同晶粒的一部份。晶粒的背側附接至該板。前側的連接在該板的反側上暴露。該晶粒附接至該板使得RF區段614在充填電介質空腔正上方。
在圖6F中，施加介電層616於晶粒前側上面。在圖6G中，用雷射、蝕刻或其他方式，鑽出穿過電介質的通 孔。有些通孔620可附接至該板，同時其他通孔618附接至晶粒。
在圖6H中，該等通孔填滿或塗上導電材料622以及形成再分布層或扇出層624於電介質上面。取決於特定實作，可能有多層電介質與經圖案化的再分布層。
在圖6I中，形成焊料中止層626於上再分布層上面。在圖6J中，施加焊球628於焊料中止層上面以形成球柵陣列。可形成任何其他類型的導電連接結構以便適合封裝件的預期連接。對於該封裝件的最終主要用途，按需要，可用附加操作及製程完成該封裝件。
描述於本文的技術及結構可應用於有各種不同類型及大小的晶粒。特別適用於薄及超薄晶粒。可做成厚達350微米或更多的背側金屬化物以提供剛性及強度和保護晶粒。替換地，薄晶粒及板，例如50微米或更小，將允許晶粒及背側層彎曲。這對於可穿戴計算裝置或可攜式裝置的實作為較佳。
在背側金屬化物中的貫通空腔及封閉空腔兩者有助於保留晶片之射頻組件的電性效能。例如，當前側上有電感器的晶粒由150微米減薄到30微米且附接至金屬板時，電感減少35%以上。不過，當空腔建立於電感器下面時，電感完全恢復。在電感器的品質因素上也可看到類似的減少。不過，利用空腔，電感器的品質因素可改善而超過厚晶粒的數值。這是因為矽厚度由150微米減到30微米促成此效益。減薄晶粒排除一些與矽基板有關的渦電流損失。
圖7根據本發明之一實作圖示計算裝置11。計算裝置11容納板2。板2可包含許多組件，包括但不限於處理器4及至少一通訊晶片6。處理器4物理及電氣耦合至板2。在有些實作中，至少一通訊晶片6也物理及電氣耦合至板2。在其他實作中，通訊晶片6為處理器4之一部份。
取決於它的應用，計算裝置11可包含可能或不物理及電氣耦合至主機板2的其他組件。這些其他組件包括但不限於：揮發性記憶體(例如，DRAM)8，非揮發性記憶體(例如，ROM)9，快閃記憶體(未圖示)，繪圖處理器12，數位訊號處理器(未圖示)，加解密處理器(未圖示)，晶片組14，天線16，顯示器18，例如觸控螢幕顯示器，觸控螢幕控制器20，電池22，聲頻編碼解碼器，視頻編碼解碼器，功率放大器24，全球定位系統(GPS)裝置26，羅盤28，加速計，陀螺儀，揚聲器30，相機32、以及大容量儲存裝置(例如，硬碟驅動器)10，光碟(CD)，數位光碟(DVD)等等)。這些組件可連接至系統板2，安裝至系統板，或與其他組件中之任一者結合。
通訊晶片6致能進出計算裝置11之資料傳輸的無線及/或有線通訊。用語「無線」及其衍生詞可用來描述通過利用非固體媒介之調變電磁輻射來傳達資料的電路、裝置、系統、方法、技術、通訊通道等等。該用語不意謂相關裝置不包含任何配線，然而在一些具體實施例中，它們可能沒有。通訊晶片6可實現許多無線標準或協定中之任一者，包括但不限於：Wi-Fi(IEEE 802.11家族)，WiMAX(IEEE 802.16家族)，IEEE 802.20，長程演進技術(LTE)，Ev-DO，HSPA+，HSDPA+，HSUPA+，EDGE，GSM，GPRS，CDMA，TDMA，DECT，藍芽，彼等之衍生物，以及指定作為3G、4G、5G及以上的任何其他無線及有線協定。計算裝置11可包含多個通訊晶片6。例如，第一通訊晶片6可專用於較短程的無線通訊，例如Wi-Fi及藍芽，以及第二通訊晶片6可專用於較長程的無線通訊，例如GPS，EDGE，GPRS，CDMA，WiMAX，LTE，Ev-DO及其他。
計算裝置11的處理器4包含封裝於處理器4內的積體電路晶粒。在本發明的一些實作中，該處理器的積體電路晶粒、記憶裝置、通訊裝置或其他組件包含或經封裝成具有數個RF或被動組件，彼等係附接至具有如本文所述之電介質空腔的板。用語「處理器」可指任何裝置或裝置之一部份用於處理來自暫存器及/或記憶體的電子資料以將該電子資料轉換成可存入暫存器及/或記憶體的其他電子資料。
在各種實作中，計算裝置11可為膝上電腦，連網電腦(netbook)，筆記型電腦，超輕薄筆電(ultrabook)，智慧型手機，平板電腦，個人數位助理(PDA)，迷你行動型個人電腦(ultra mobile PC)，行動電話，桌上電腦，伺服器，列表機，掃描器，監視器，機上盒，娛樂控制單元，數位相機，可攜式音樂播放器，或數位錄影機。在其他實作中，計算裝置11可為處理資料的任何其他電子裝置，包括穿戴裝置。
具體實施例可實作成用主機板、特殊應用積體電路(ASIC)及/或現場可程式閘陣列(FPGA)互連的一或更多記憶晶片、控制器、CPU(中央處理單元)，微晶片或積體電路。
對於「一具體實施例」、「具體實施例」、「示範具體實施例」、「各種具體實施例」等等的參照係表示所描述的本發明具體實施例(或數個)可包括特定特徵、結構或特性，但是並非每個具體實施例一定包括該等特定特徵、結構或特性。此外，一些具體實施例可具有針對其他具體實施例所述的特徵中之一些、所有或全無。
在以下描述及請求項中，可使用用語「耦合」及其衍生詞。應瞭解，這些用語無意用作彼此的同義詞。反而，在特定具體實施例中，「連接」用來表示互相直接物理或電性接觸的兩個或更多元件。「耦合」用來表示互相合作或互動的兩個或更多元件，但是它們之間可能有或沒有居間的物理或電氣組件。
如請求項中所使用的，除非特別指明，描述共同元件的序數形容詞「第一」、「第二」、「第三」只是表示參照類似元件的不同實例，而非旨在暗示所描述的元件必須在時間、空間、順序上或者是以任何其他方式遵循給定順序。
附圖及以下說明給出具體實施例的例子。熟諳此藝者應瞭解，一或更多所述元件也可結合成單一功能元件。替換地，某些元件可分成多個功能元件。來自一具體 實施例的元件可加到另一具體實施例。例如，可改變描述於本文的方法順序而且不受限於描述於本文的方式。此外，任何流程圖中的動作不需以圖示順序實作；也不一定做所有的動作。再者，不取決於其他動作的動作可其他動作並行地執行。具體實施例的範疇決不受限於特定的實施例。不適是否明示於本專利說明書中，仍可能有許多變體，例如結構，尺寸以及材料用法的差異。具體實施例的範疇至少與以下所給出的請求項的一樣寬廣。
以下實施例有關於其他具體實施例。不同具體實施例的各種特徵可與一些特徵以各種方式組合，包括或不包括這些特徵以適合各式各樣的不同應用系統。有些具體實施例有關於一種半導體封裝件，其係包含：一導電板；有一前側及一背側的一半導體晶粒，該背側附接至該板；附接至該板的一射頻組件；在該板中鄰近該射頻組件的一充填電介質空腔；以及附接至該晶粒之該前側用於外部連接的一再分布層。
在其他具體實施例中，該板包含銅、陶瓷或聚合物。
在其他具體實施例中，該電介質包含環氧樹脂、聚亞醯胺或液晶聚合物。
在其他具體實施例中，該空腔由附接至該晶粒之一側延伸穿過該板至在該晶粒對面之一側。
在其他具體實施例中，該射頻組件形成於該晶粒之該前側上。
在其他具體實施例中，該晶粒有一區段，該區段含有包括該射頻組件的數個射頻電路。
在其他具體實施例中，該等射頻電路包含一射頻放大器。
其他具體實施例包括：一第二晶粒。該第二晶粒也附接至該板，以及其中該射頻組件形成於該第二晶粒上。
其他具體實施例包括：在該晶粒與該再分布層之間覆蓋該晶粒及該板的一電介質。
其他具體實施例包括：一第二晶粒，在該板中與該第一晶粒和在該第二電介質空腔內之一通孔桿隔開的一第二充填電介質空腔，以及在該通孔桿上以連接至位於該板在該第一晶粒對面之一側上之該第二晶粒的一連接焊墊陣列。
其他具體實施例包括：使該通孔桿連接至該再分布層的多個通孔。
其他具體實施例包括：在該晶粒與該板之間的一鈍化層。
有些具體實施例有關於一種方法，其係包含下列步驟：在該板中形成一空腔，使一晶粒之一背側附接至該板，該晶粒有一RF區段而且該晶粒經附接成該RF區段鄰近該空腔，用一電介質覆蓋該晶粒之一前側，以及形成一再分布層於該電介質上面用於該晶粒之該前側的外部連接。
其他具體實施例包括：在附接該晶粒之前，用一電介質填滿該空腔。
其他具體實施例包括：使一第二晶粒附接至該板，以及用一電介質覆蓋該晶粒的步驟包括：用該電介質覆蓋該第一及該第二晶粒。
其他具體實施例包括：在形成該等再分布層之前，在該電介質中形成數個通孔，該等通孔使該晶粒的數個連接焊墊連接至該再分布層。
在其他具體實施例中，形成一空腔的步驟包括：形成從最靠近該晶粒之一側穿過該板至反側的一空腔。
其他具體實施例包括：在附接該晶粒之前，形成穿過該板且與該晶粒隔開的一第二空腔，用一電介質填滿該第二空腔，形成穿過該該第二空腔之該電介質的數個通孔，使該等第二空腔通孔在一側上連接至該再分布層，以及使該等第二空腔通孔在反側上連接至一附加晶粒。
在其他具體實施例中，連接在一側上之該等第二空腔通孔的步驟包括：形成穿過覆蓋該晶粒之該電介質的數個通孔以使該等第二空腔通孔連接至該再分布層。
有些具體實施例有關於一種計算裝置，其係包含：一電源供應器，一天線，以及一封裝件，其含有一導電板；有一前側及一背側的一半導體晶粒，該背側附接至該板；附接至該板且耦合至該天線的一射頻組件；在該板中鄰近該射頻組件的一充填電介質空腔；以及附接至該晶粒之該前側用於外部連接至該天線及該電源供應器的一再分布層。
在其他具體實施例中，該等射頻電路包含一射頻 放大器。
其他具體實施例包括：一第二晶粒。該第二晶粒也附接至該板，以及其中該射頻組件形成於該第二晶粒上。
其他具體實施例包括：在該晶粒與該再分布層之間覆蓋該晶粒及該板的一電介質。
在其他具體實施例中，該晶粒為一處理器，該封裝件更包含一記憶體晶粒，在該板中之一第二充填電介質空腔及在該第二電介質空腔內之一通孔桿，該第二電介質空腔與該處理器間隔開，以及在該通孔桿上的一連接焊墊陣列以連接至位於該板在該處理器對面之一側上的該記憶體晶粒以及通過該再分布層使該記憶體晶粒連接至該處理器。
其他具體實施例包括：使該通孔桿連接至該再分布層的多個通孔。

Claims (22)

  1. 一種半導體封裝件，其係包含：一導電板；一半導體晶粒，其具有一前側及一背側，該背側附接至該板；一射頻組件，其附接至該板；一充填電介質空腔，其在該板中於該射頻組件正下方；以及一再分布層，其附接至該晶粒之該前側以用於外部連接。
  2. 如請求項1所述之封裝件，其中該板包含銅、陶瓷或聚合物。
  3. 如請求項1所述之封裝件，其中該電介質包含環氧樹脂、聚亞醯胺或液晶聚合物。
  4. 如請求項1所述之封裝件，其中該空腔由附接至該晶粒之一側延伸穿過該板至在該晶粒對面之一側。
  5. 如請求項1所述之封裝件，其中該射頻組件形成於該晶粒之該前側上。
  6. 如請求項5所述之封裝件，其中該晶粒有一區段，該區段含有包括該射頻組件的數個射頻電路。
  7. 如請求項6所述之封裝件，其中該等射頻電路包含一射頻放大器。
  8. 如請求項1所述之封裝件，其更包含一第二晶粒，該第 二晶粒也附接至該板，以及其中該射頻組件形成於該第二晶粒上。
  9. 如請求項1所述之封裝件，其更包含在該晶粒與該再分布層之間覆蓋該晶粒及該板的一電介質。
  10. 如請求項1所述之封裝件，其更包含：一第二晶粒；在該板中之一第二充填電介質空腔及在該第二電介質空腔內之一通孔桿，該第二電介質空腔與該第一晶粒間隔開；一連接焊墊陣列，其在該通孔桿上連接至該第二晶粒，該第二晶粒位於該板在該第一晶粒對面之一側上。
  11. 如請求項10所述之封裝件，其更包含用以連接該通孔桿至該再分布層的多個通孔。
  12. 如請求項1所述之封裝件，其更包含在該晶粒與該板之間的一鈍化層。
  13. 一種用以封裝半導體晶粒之方法，其係包含下列步驟：在該板中形成一空腔；使一晶粒之一背側附接至該板，該晶粒有一RF區段而且該晶粒經附接成該RF區段於該空腔正上方；用一電介質覆蓋該晶粒之一前側；以及形成一再分布層於該電介質上面用於該晶粒之該前側的外部連接。
  14. 如請求項13所述之方法，其更包括：在附接該晶粒之前，用一電介質填滿該空腔。
  15. 如請求項13所述之方法，其更包括：使一第二晶粒附接至該板，以及其中用一電介質覆蓋該晶粒的步驟包括：用該電介質覆蓋該第一及該第二晶粒。
  16. 如請求項13所述之方法，其更包括：在形成該等再分布層之前，在該電介質中形成數個通孔，該等通孔使該晶粒的數個連接焊墊連接至該再分布層。
  17. 如請求項13所述之方法，其中形成一空腔的步驟包括：形成從最靠近該晶粒之一側穿過該板至反側的一空腔。
  18. 如請求項13所述之方法，其更包括：在附接該晶粒之前，形成穿過該板且與該晶粒間隔開的一第二空腔；用一電介質填滿該第二空腔；形成穿過該該第二空腔之該電介質的數個通孔；使該等第二空腔通孔在一側上連接至該再分布層；以及使該等第二空腔通孔在反側上連接至一附加晶粒。
  19. 一種計算裝置，其係包含：一電源供應器；一天線；以及一封裝件，其含有一導電板；具有一前側及一背側的一半導體晶粒，該背側附接至該板；附接至該板且耦合至該天線的一射頻組件；在該板中於該射頻組件正下方的一充填電介質空腔；以及附接至該晶粒之該前側用於外部連接至該天線及該電源供應器的一再分布層。
  20. 如請求項19所述之計算裝置，其中該空腔由附接至該晶粒之一側延伸穿過該板至在該晶粒對面之一側。
  21. 如請求項19所述之計算裝置，其中該晶粒為一處理器，該封裝件更包含：一記憶體晶粒；在該板中之一第二充填電介質空腔及在該第二電介質空腔內之一通孔桿，該第二電介質空腔與該處理器間隔開；在該通孔桿上的一連接焊墊陣列，其用以連接至位於該板在該處理器對面之一側上的該記憶體晶粒以及通過該再分布層使該記憶體晶粒連接至該處理器。
  22. 一種半導體封裝件，其係包含：一導電板；一半導體晶粒，其具有一前側及一背側，該背側附接至該板；一射頻組件，其附接至該板；一充填電介質空腔，其在該板中鄰近於該射頻組件；一再分布層，其附接至該晶粒之該前側以用於外部連接；一第二晶粒；一第二充填電介質空腔及在該第二電介質空腔內之一通孔桿，該第二電介質空腔在該板中與該第一晶粒間隔開；以及 一連接焊墊陣列，其在該通孔桿上連接至該第二晶粒，該第二晶粒位於該板在該第一晶粒對面之一側上。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3178162A4 (en) * 2014-08-07 2018-04-04 Intel Corporation Method and apparatus for forming backside die planar devices and saw filter
US11189573B2 (en) * 2016-03-31 2021-11-30 Intel Corporation Semiconductor package with electromagnetic interference shielding using metal layers and vias
TWI622149B (zh) 2017-01-03 2018-04-21 力成科技股份有限公司 封裝結構的製造方法
DE102018109028B4 (de) 2017-06-30 2023-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Abschirmstruktur zur Verringerung von Übersprechen und Verfahren zur Herstellung derselben
US10269728B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with shielding structure for cross-talk reduction
US10879197B2 (en) * 2017-08-30 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating package structure
US10643919B2 (en) * 2017-11-08 2020-05-05 Samsung Electronics Co., Ltd. Fan-out semiconductor package
KR102185706B1 (ko) * 2017-11-08 2020-12-02 삼성전자주식회사 팬-아웃 반도체 패키지
US10978408B2 (en) * 2018-06-07 2021-04-13 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
CN111821567A (zh) * 2019-03-30 2020-10-27 深圳硅基仿生科技有限公司 电子封装体及植入式器件
US11101840B1 (en) 2020-02-05 2021-08-24 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
US11183765B2 (en) 2020-02-05 2021-11-23 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
KR20210099947A (ko) 2020-02-05 2021-08-13 삼성전기주식회사 칩 고주파 패키지 및 고주파 모듈
US11550158B2 (en) * 2020-06-24 2023-01-10 Meta Platforms Technologies, Llc Artificial reality system having system-on-a-chip (SoC) integrated circuit components including stacked SRAM
CN114556550A (zh) * 2020-08-12 2022-05-27 敦南科技股份有限公司 双面冷却功率封装结构
CN112349700B (zh) * 2020-09-28 2023-05-09 中国电子科技集团公司第二十九研究所 一种气密高导热lcp封装基板及多芯片系统级封装结构
FR3122035B1 (fr) 2021-04-16 2023-04-21 Commissariat Energie Atomique Structure composite, destinée à une co-intégration planaire de composants électroniques de fonctions différentes

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001287A1 (en) * 2005-06-29 2007-01-04 Bosco Bruce A Hermetic cavity package
US20090091904A1 (en) * 2006-03-29 2009-04-09 Kyocera Corporation Circuit Module and Radio Communications Equipment, and Method for Manufacturing Circuit Module
US20110316117A1 (en) * 2007-08-14 2011-12-29 Agency For Science, Technology And Research Die package and a method for manufacturing the die package
US20140084391A1 (en) * 2012-09-25 2014-03-27 Cambridge Silicon Radio Limited Composite Reconstituted Wafer Structures
US20140159212A1 (en) * 2012-12-10 2014-06-12 Industrial Technology Research Institute Stacked type power device module
US20150021754A1 (en) * 2009-11-25 2015-01-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management
TW201510740A (zh) * 2013-07-11 2015-03-16 Mophie Inc 隨身電腦以及將隨身電腦功能連接至獨立計算裝置的方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100543836B1 (ko) * 1997-08-19 2006-01-23 가부시키가이샤 히타치세이사쿠쇼 멀티칩 모듈 구조체 및 그 제작 방법
JP3792635B2 (ja) * 2001-12-14 2006-07-05 富士通株式会社 電子装置
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
JP3938759B2 (ja) * 2002-05-31 2007-06-27 富士通株式会社 半導体装置及び半導体装置の製造方法
JP2007514321A (ja) * 2003-12-10 2007-05-31 ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア ミックスド・シグナル集積回路のための低クロストーク回路基板
US7892882B2 (en) * 2006-06-09 2011-02-22 Freescale Semiconductor, Inc. Methods and apparatus for a semiconductor device package with improved thermal performance
US7518229B2 (en) * 2006-08-03 2009-04-14 International Business Machines Corporation Versatile Si-based packaging with integrated passive components for mmWave applications
US7709934B2 (en) 2006-12-28 2010-05-04 Intel Corporation Package level noise isolation
US20090026619A1 (en) 2007-07-24 2009-01-29 Northrop Grumman Space & Mission Systems Corp. Method for Backside Metallization for Semiconductor Substrate
CN102256893B (zh) 2008-11-07 2015-04-29 卡文迪什动力有限公司 利用多个较小的mems器件替换较大的mems器件的方法
US8970031B2 (en) * 2009-06-16 2015-03-03 Hsio Technologies, Llc Semiconductor die terminal
US8110915B2 (en) * 2009-10-16 2012-02-07 Infineon Technologies Ag Open cavity leadless surface mountable package for high power RF applications
US8217272B2 (en) * 2009-12-18 2012-07-10 Intel Corporation Apparatus and method for embedding components in small-form-factor, system-on-packages
US8241956B2 (en) 2010-03-08 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level multi-row etched lead package
US8105872B2 (en) * 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
JP5711472B2 (ja) * 2010-06-09 2015-04-30 新光電気工業株式会社 配線基板及びその製造方法並びに半導体装置
KR101711048B1 (ko) * 2010-10-07 2017-03-02 삼성전자 주식회사 차폐막을 포함하는 반도체 장치 및 제조 방법
US8624353B2 (en) * 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
US9484313B2 (en) * 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
US9087832B2 (en) * 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001287A1 (en) * 2005-06-29 2007-01-04 Bosco Bruce A Hermetic cavity package
US20090091904A1 (en) * 2006-03-29 2009-04-09 Kyocera Corporation Circuit Module and Radio Communications Equipment, and Method for Manufacturing Circuit Module
US20110316117A1 (en) * 2007-08-14 2011-12-29 Agency For Science, Technology And Research Die package and a method for manufacturing the die package
US20150021754A1 (en) * 2009-11-25 2015-01-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management
US20140084391A1 (en) * 2012-09-25 2014-03-27 Cambridge Silicon Radio Limited Composite Reconstituted Wafer Structures
US20140159212A1 (en) * 2012-12-10 2014-06-12 Industrial Technology Research Institute Stacked type power device module
TW201510740A (zh) * 2013-07-11 2015-03-16 Mophie Inc 隨身電腦以及將隨身電腦功能連接至獨立計算裝置的方法

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CN107251206B (zh) 2020-07-31
KR102376119B1 (ko) 2022-03-17
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