TWI613786B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI613786B
TWI613786B TW102140277A TW102140277A TWI613786B TW I613786 B TWI613786 B TW I613786B TW 102140277 A TW102140277 A TW 102140277A TW 102140277 A TW102140277 A TW 102140277A TW I613786 B TWI613786 B TW I613786B
Authority
TW
Taiwan
Prior art keywords
metal film
nmos transistor
spacer
drain
diffusion region
Prior art date
Application number
TW102140277A
Other languages
English (en)
Chinese (zh)
Other versions
TW201438182A (zh
Inventor
小山威
廣瀬嘉胤
Original Assignee
精工半導體有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精工半導體有限公司 filed Critical 精工半導體有限公司
Publication of TW201438182A publication Critical patent/TW201438182A/zh
Application granted granted Critical
Publication of TWI613786B publication Critical patent/TWI613786B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW102140277A 2012-11-22 2013-11-06 半導體裝置 TWI613786B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012256563A JP6033054B2 (ja) 2012-11-22 2012-11-22 半導体装置
JP2012-256563 2012-11-22

Publications (2)

Publication Number Publication Date
TW201438182A TW201438182A (zh) 2014-10-01
TWI613786B true TWI613786B (zh) 2018-02-01

Family

ID=50727145

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102140277A TWI613786B (zh) 2012-11-22 2013-11-06 半導體裝置

Country Status (5)

Country Link
US (1) US9006831B2 (ko)
JP (1) JP6033054B2 (ko)
KR (1) KR101999312B1 (ko)
CN (1) CN103839925B (ko)
TW (1) TWI613786B (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020096213A (ko) * 2001-06-19 2002-12-31 조현화 광호변성 컬러무스
JP6369886B2 (ja) * 2016-01-14 2018-08-08 新電元工業株式会社 半導体装置
CN109414929B (zh) * 2016-09-19 2020-04-14 惠普发展公司,有限责任合伙企业 具有带间隙的金属层的终止环

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040188763A1 (en) * 2003-03-28 2004-09-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US20060097330A1 (en) * 2004-11-10 2006-05-11 Kuo-Feng Yu Asymmetrical layout structure for ESD protection
JP2006196487A (ja) * 2005-01-11 2006-07-27 Seiko Epson Corp 半導体装置
JP2007043036A (ja) * 2005-06-30 2007-02-15 Seiko Epson Corp 集積回路装置及び電子機器

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0923126A1 (en) * 1997-12-05 1999-06-16 STMicroelectronics S.r.l. Integrated electronic device comprising a mechanical stress protection structure
JP2000022138A (ja) * 1998-07-07 2000-01-21 Seiko Instruments Inc 半導体装置とその製造方法
KR100383003B1 (ko) * 2000-12-30 2003-05-09 주식회사 하이닉스반도체 멀티-핑거구조의 esd 보호회로
US6573568B2 (en) * 2001-06-01 2003-06-03 Winbond Electronics Corp. ESD protection devices and methods for reducing trigger voltage
US6909149B2 (en) * 2003-04-16 2005-06-21 Sarnoff Corporation Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies
CN100446080C (zh) * 2005-06-30 2008-12-24 精工爱普生株式会社 集成电路装置及电子设备
JP2007116049A (ja) 2005-10-24 2007-05-10 Toshiba Corp 半導体装置
JP5603089B2 (ja) 2009-02-23 2014-10-08 セイコーインスツル株式会社 半導体装置
JP5529607B2 (ja) 2010-03-29 2014-06-25 セイコーインスツル株式会社 半導体装置
CN102263104B (zh) * 2011-06-16 2013-04-17 北京大学 Mos结构的esd保护器件
US8817434B2 (en) * 2011-10-11 2014-08-26 United Microelectronics Corporation Electrostatic discharge (ESD) protection device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040188763A1 (en) * 2003-03-28 2004-09-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US20060097330A1 (en) * 2004-11-10 2006-05-11 Kuo-Feng Yu Asymmetrical layout structure for ESD protection
JP2006196487A (ja) * 2005-01-11 2006-07-27 Seiko Epson Corp 半導体装置
JP2007043036A (ja) * 2005-06-30 2007-02-15 Seiko Epson Corp 集積回路装置及び電子機器

Also Published As

Publication number Publication date
JP2014107281A (ja) 2014-06-09
JP6033054B2 (ja) 2016-11-30
US9006831B2 (en) 2015-04-14
TW201438182A (zh) 2014-10-01
CN103839925A (zh) 2014-06-04
KR20140066098A (ko) 2014-05-30
US20140138762A1 (en) 2014-05-22
KR101999312B1 (ko) 2019-07-11
CN103839925B (zh) 2018-01-02

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