TWI610410B - 重配置線路結構及其製作方法 - Google Patents
重配置線路結構及其製作方法 Download PDFInfo
- Publication number
- TWI610410B TWI610410B TW105138521A TW105138521A TWI610410B TW I610410 B TWI610410 B TW I610410B TW 105138521 A TW105138521 A TW 105138521A TW 105138521 A TW105138521 A TW 105138521A TW I610410 B TWI610410 B TW I610410B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- pad
- insulating layer
- patterned
- reconfiguration circuit
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000009826 distribution Methods 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 252
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000011241 protective layer Substances 0.000 claims abstract description 27
- 238000009413 insulation Methods 0.000 claims abstract description 26
- 239000002905 metal composite material Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 7
- 230000001788 irregular Effects 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 6
- 239000011368 organic material Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/022—Protective coating, i.e. protective bond-through coating
- H01L2224/02205—Structure of the protective coating
- H01L2224/02206—Multilayer protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02311—Additive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02317—Manufacturing methods of the redistribution layers by local deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
- H01L2224/02351—Shape of the redistribution layers comprising interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
- H01L2224/05582—Two-layer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
一種重配置線路結構,適於配置於具有接墊與保護層的基材上,保護層具有暴露出部分接墊的第一開口。重配置線路結構包括第一、第二圖案化絕緣層及重配置線路層。第一圖案化絕緣層配置於保護層上且包括對應於第一開口的第二開口及至少一凹槽。重配置線路層配置於第一圖案化絕緣層上且包括接墊部及導線部。接墊部位於第一圖案化絕緣層上,導線部包括本體及凸出本體的至少一根基。本體從接墊部延伸至第一、第二開口內,以與接墊連接。根基伸入凹槽。第二圖案化絕緣層覆蓋導線部且暴露部分的接墊部。本發明更提供一種重配置線路結構的製作方法。
Description
本發明是有關於一種線路結構及其製作方法,且特別是有關於一種重配置線路結構及其製作方法。
在高度情報化社會的今日,多媒體應用的市場不斷地急速擴張著。積體電路封裝技術亦需配合電子裝置的數位化、網路化、區域連接化以及使用人性化的趨勢發展。為達成上述的要求,必須強化電子元件的高速處理化、多功能化、積集化、小型輕量化及低價化等多方面的要求,於是積體電路封裝技術也跟著朝向微型化、高密度化發展。所謂積體電路封裝密度所指的是單位面積所含有腳位(pin)數目多寡的程度。對於高密度積體電路封裝而言,縮短積體電路與封裝基材間配線的長度,將有助訊號傳遞速度的提昇,是以藉由凸塊(bump)作為訊號傳遞之覆晶封裝技術已漸成為高密度封裝的主流。
覆晶晶片(flip chip)上的焊墊則通常是以陣列方式(array type)排列,覆晶晶片的焊墊位置未必對應於基板上的接墊位置,目前通常會透過重配置線路層將基板上的接墊位置進行重配置,使其成為覆晶晶片的焊墊之陣列分佈的型態。如此一來,覆晶晶片的焊墊便能夠透過凸塊與重配置線路層電性連接於基板上的接墊。
由於目前重配置線路層的導線寬度越來越小,為了使導線具有一定的電阻值,通常採用的方式是增加了導線的高度,以使導線的截面積維持一定。這也使得導線的剖面呈現出高且窄的形狀。然而,細窄型的導線縮減了其附著於下方基板或是其附著於基板上的絕緣層的面積,容易傾倒而造成剝離(peeling)的狀況。
本發明提供一種重配置線路結構,其不易剝離(peeling),而具有較佳的結構穩定度。
本發明提供一種重配置線路結構的製作方法,其可製作出上述的重配置線路結構。
本發明的一種重配置線路結構,適配置於一基材上,基材具有一接墊與一保護層,其中保護層具有一第一開口,且第一開口暴露出部分的接墊,重配置線路結構包括一第一圖案化絕緣層、一重配置線路層及一第二圖案化絕緣層。第一圖案化絕緣層配置於保護層上且包括一第二開口及至少一凹槽,其中第二開口對應於第一開口以暴露部分的接墊。重配置線路層配置於第一圖案化絕緣層上且包括一接墊部及一導線部,其中接墊部位於第一圖案化絕緣層上,導線部包括一本體及凸出於本體的至少一根基,本體位於第一圖案化絕緣層上從接墊部延伸至第一開口與第二開口內,以與接墊連接,至少一根基伸入至少一凹槽。第二圖案化絕緣層設置於第一圖案化絕緣層上,第二圖案化絕緣層覆蓋導線部且暴露部分的接墊部。
在本發明的一實施例中,上述的至少一凹槽包括一條狀凹溝或是分離的多個凹槽,至少一根基包括一條狀根基或是分離的多個樁狀根基,且至少一凹槽的數量與位置對應於至少一根基的數量與位置。
在本發明的一實施例中,上述的各根基的寬度小於本體的寬度。
在本發明的一實施例中,上述的各根基的寬度沿著遠離本體的方向漸縮、漸擴或不變。
在本發明的一實施例中,上述的各根基在橫截導線部的延伸方向的一截面積小於、等於或大於本體在橫截導線部的延伸方向的一截面積。
在本發明的一實施例中,上述的凹槽的深度小於或等於第一圖案化絕緣層的厚度。
在本發明的一實施例中,上述的導線部的本體在沿著導線部的延伸方向上包括交替相連的多個放大區及多個連接區,這些放大區的寬度分別大於這些連接區的寬度,這些放大區的形狀包括圓形、橢圓形、矩形、菱形或不規則形。
在本發明的一實施例中,上述的重配置線路結構更包括一球底金屬(Under Bump Metallurgic,UBM)層,配置於重配置線路層下方,並位於重配置線路層與第一圖案化絕緣層之間以及重配置線路層與接墊之間。
在本發明的一實施例中,上述的重配置線路結構更包括一圖案化金屬複合層,配置於重配置線路層上,圖案化金屬複合層的寬度大於重配置線路層的寬度。
本發明的一種重配置線路結構的製作方法,包括:提供一基材,其中基材具有一接墊與一保護層,保護層具有一第一開口,且第一開口暴露出部分的接墊;形成一第一絕緣層於保護層上;對第一絕緣層進行兩次圖案化程序,以製作出一第二開口與至少一凹槽,而形成一第一圖案化絕緣層,其中至少一凹槽的深度小於第二開口的深度;形成一重配置線路層於第一圖案化絕緣層上,其中重配置線路層包括一接墊部及一導線部,接墊部位於第一圖案化絕緣層上,導線部包括一本體及凸出於本體的至少一根基,本體位於第一圖案化絕緣層上從接墊部延伸至第一開口與第二開口內,以與接墊連接,至少一根基伸入至少一凹槽;以及形成一第二圖案化絕緣層於第一圖案化絕緣層上且覆蓋導線部以及接墊部的周圍,第二圖案化絕緣層並暴露部分接墊部。
在本發明的一實施例中,上述的重配置線路結構的製作方法,更包括在形成重配置線路層之前,形成一球底金屬層於第一圖案化絕緣層上,球底金屬層覆蓋接墊及部分的第一圖案化絕緣層。
基於上述,本發明的重配置線路結構藉由在第一圖案化絕緣層形成凹槽,且重配置線路層的導線部包括本體及凸出於本體的根基,導線部除了本體附著於第一圖案化絕緣層的面積之外,還透過根基伸入凹槽來增加附著面積,以降低重配置線路層的導線部剝離(peeling)於第一圖案化絕緣層的機率,而使得重配置線路層的導線部在基材上具有較佳的結構穩定度。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A是依照本發明的一實施例的一種重配置線路結構的局部剖面示意圖。請先參閱圖1A,本實施例的重配置線路結構100適於配置於一基材10上,以將基材10的接墊12重配置到其他位置。在本實施例中,基材10可以是線路板、晶片或晶圓,基材10的種類並不以上述為限制。如圖1A所示,基材10具有一接墊12與一保護層14,其中保護層14具有一第一開口16,且第一開口16暴露出部分的接墊12。
重配置線路結構100包括一第一圖案化絕緣層110、一重配置線路層130及一第二圖案化絕緣層150。第一圖案化絕緣層110配置於保護層14上且包括一第二開口112,其中第二開口112對應於第一開口16以暴露部分的接墊12。
重配置線路層130配置於第一圖案化絕緣層110上且包括一接墊部131及一導線部132。如圖1A所示,導線部132自第二開口112內之接墊12向外延伸,透過第二圖案化絕緣層150於重配置缐層130上定義出該接墊部131。在本實施例中,基材10上的接墊12可以透過導線部132重配置到接墊部131的位置,以方便後續與其他線路結構(未繪示)連接。重配置線路層130的材料包括銅,但不以此為限制。
一般來說,導線的電阻值與其截面積相關,截面積越大,電阻值越低。由於目前的線路朝細線化的方向發展,在習知的重配置線路層中,會透過增加導線的高度來彌補降低導線的寬度所造成的電阻值變化,但此設計使得導線的剖面呈現出高且窄的形狀,而縮減了導線與其下方基材的附著面積,容易發生傾倒或剝離的狀況。本實施例的重配置線路結構100藉由下述的設計可以有效地降低重配置線路層130發生傾倒或與絕緣層剝離的狀況。
圖1B是圖1A的重配置線路結構的沿A-A線段且隱藏基材與第二圖案化絕緣層的剖面示意圖。圖1C是圖1A的重配置線路結構的重配置線路層的俯視示意圖。請同時參閱圖1A至圖1C,在本實施例中,第一圖案化絕緣層110還包括至少一凹槽114。在本實施例中,第二開口112貫穿第一圖案化絕緣層110,凹槽114並未貫穿第一圖案化絕緣層110。也就是說,第二開口112的深度大於凹槽114的深度,但凹槽114的深度並不以此為限制。
如圖1B所示,導線部132包括一本體133及向下凸出於本體133的至少一根基136,在本實施例中,凹槽114為單一個條狀的凹溝,根基136為單一個條狀的根基,且凹槽114的位置對應於根基136的位置。根基136的寬度W1小於本體133的寬度W2,且導線部132的根基136伸入且填滿於第一圖案化絕緣層110的凹槽114。
在本實施例中,重配置線路結構100藉由在第一圖案化絕緣層110形成凹槽114,且重配置線路層130的導線部132包括凸出於本體133的根基136,導線部132除了透過本體133附著於第一圖案化絕緣層110的面積之外,還透過根基136伸入凹槽114來增加附著面積,此設計也使得導線部132與下方的第一圖案化絕緣層110的附著狀態從習知的平面變成了立體的結構。由於導線部132與下方的第一圖案化絕緣層110的附著面積增加,重配置線路層130的導線部132剝離(peeling)於第一圖案化絕緣層110的機率有效地被降低,而使得重配置線路層130的導線部132在基材10上具有較佳的結構穩定度。並且,此設計也可以讓細線寬的導線部132不需為了降低電阻值而刻意提高導線部132的高度(厚度)。
此外,在本實施例中,重配置線路結構100還包括一球底金屬層120與一圖案化金屬複合層140。球底金屬層120配置於重配置線路層130下方,並位於重配置線路層130與第一圖案化絕緣層110之間以及重配置線路層130與接墊12之間,以作為第一圖案化絕緣層110與設置於其上之重配置線路層130之間及接墊12與設置於其上之重配置線路層130之間的接合媒介,進而增加第一圖案化絕緣層110與重配置線路層130之間及接墊12與重配置線路層130之間的接合性。球底金屬層120包括黏著層(adhesive layer)、阻障層(barrier layer)以及沾錫層(wetting layer)等複合金屬層。
圖案化金屬複合層140配置於重配置線路層130上。如圖1B所示,圖案化金屬複合層140的寬度W3大於重配置線路層130的本體133的寬度W2。在本實施例中,圖案化金屬複合層140以配置在重配置線路層130上的一鎳層與配置在鎳層上的一金層為例,但圖案化金屬複合層140的種類並不以此為限制。
第二圖案化絕緣層150設置於第一圖案化絕緣層110與重配置線路層130上方。如圖1A所示,第二圖案化絕緣層150覆蓋導線部132且未遮蔽部分的接墊部131。一未繪示的凸塊(例如錫球或打線凸塊…等等)可以透過接墊部131上方的圖案化金屬複合層140連接於接墊部131。
圖1D是依照本發明的一實施例的一種重配置線路結構的製作方法的步驟示意圖。本實施例的重配置線路結構的製作方法200可製作出如圖1A所示的重配置線路結構100,請同時參考圖1A與圖1D,本實施例的重配置線路結構的製作方法200包括下列步驟。
首先,步驟210,提供一基材10,其中基材10具有一接墊12與一保護層14,保護層14具有一第一開口16,且第一開口16暴露出部分的接墊12。基材10可以是線路板、晶片或晶圓,基材10的種類並不以上述為限制。在本實施例中,接墊12的材料例如為鋁。保護層14的材料可以包括氧化矽、氮氧化矽、氮化矽、有機材料、聚合物或其組合。有機材料例如是苯並環丁烯(BCB)。聚合物例如是聚醯亞胺(PI)。保護層14可以採化學氣相沉積法或是塗佈法來形成,但並不以此為限。
接著,步驟220,形成一第一絕緣層於保護層14上。第一絕緣層的材料可以包括氧化矽、氮氧化矽、氮化矽、有機材料、聚合物或其組合。有機材料例如是苯並環丁烯(BCB)。聚合物例如是聚醯亞胺(PI)。第一絕緣層可以利用化學氣相沉積法或是塗佈法來形成,但本發明並不以此為限。此外,第一絕緣層的材料可以相同於或是不同於保護層14。
再來,步驟230,對第一絕緣層進行兩次圖案化程序,以製作出一第二開口112與至少一凹槽114,而形成一第一圖案化絕緣層110,其中至少一凹槽114的深度小於第二開口112的深度。在步驟230中,利用正型光阻的曝光顯影後會被移除的特性,在第一絕緣層上進行兩次圖案化程序以製作出深度不同的第二開口112與凹槽114。
接著,步驟240,形成一球底金屬層120於第一圖案化絕緣層110上,球底金屬層120覆蓋接墊12及部分的第一圖案化絕緣層110。在本實施例中,形成球底金屬層120於第一圖案化絕緣層110120上的方法包括濺鍍。球底金屬層120包括黏著層(adhesive layer)、阻障層(barrier layer)以及沾錫層(wetting layer)等複合金屬層。
再來,步驟250,形成一重配置線路層130於第一圖案化絕緣層110上,其中重配置線路層130包括一接墊部131及一導線部132,接墊部131位於第一圖案化絕緣層110上,導線部132包括一本體133及凸出於本體133的至少一根基136,本體133位於第一圖案化絕緣層110上從接墊部131延伸至第一開口16與第二開口112內,以與接墊12連接,至少一根基136伸入至少一凹槽114。
在本實施例中,於第一圖案化絕緣層110上形成重配置線路層130的方式是透過電鍍,因電鍍無等向性,可快速地填滿凹槽114而將凹槽114封口。此外,在本實施例中,重配置線路層130的材料包括銅,但重配置線路層130的材料也可以是其他金屬,並不以此為限制。其後可在重配置線路層130上形成一圖案化金屬複合層140,圖案化金屬複合層140可包括一鎳層與配置在鎳層上的一金層,但圖案化金屬複合層140的種類並不以此為限制。
最後,步驟260,形成一第二圖案化絕緣層150於第一圖案化絕緣層110上且覆蓋導線部132以及接墊部131的周圍,第二圖案化絕緣層150並暴露部分接墊部131及圖案化金屬複合層140位在接墊部131上的部分。在本實施例中,第二圖案化絕緣層150的材料可以包括氧化矽、氮氧化矽、氮化矽、有機材料、聚合物或其組合。有機材料例如是苯並環丁烯(BCB)。聚合物例如是聚醯亞胺(PI)。第二圖案化絕緣層150可以透過先以化學氣相沉積法或是塗佈法來形成絕緣層再對絕緣層曝光顯影而成,但本發明並不以此為限。
藉由上述的製造方法可以製作出如圖1A至圖1C所示地不易剝離的重配置線路層130,而具有較佳的結構穩定度。當然,重配置線路結構的形式並不以此為限制,下面將介紹其他形式的重配置線路結構。需說明的是,在下面這些實施例中,與前一實施例相同或相似的元件以相同或相似的符號表示,不再多加贅述。
圖2至圖6分別是依照本發明的其他實施例的多種重配置線路結構隱藏第二圖案化絕緣層150的剖面示意圖。請先參閱圖2,圖2的重配置線路結構100a與圖1B的重配置線路結構100的主要差異在於,在圖1B中,凹槽114的深度小於第一圖案化絕緣層110的厚度。在本實施例中,凹槽114a的深度等於第一圖案化絕緣層110a的厚度,而使得根基136或球底屬層120的底部配置於保護層14上。也就是說,凹槽114a的深度也可以是相同於第二開口112的深度。因此,當採用上述的製作方法來製作本實施例的重配置線路結構100a時,在步驟230中只需要對第一絕緣層進行一次圖案化程序即可。另外,步驟230也可以採用負型光阻,並不以使用正型光阻為限制。
請參閱圖3,圖3的重配置線路結構100b與圖1B的重配置線路結構100的主要差異在於,在圖1B中,根基136在橫截該導線部132的延伸方向的截面積(也就是圖1B中根基136的面積)小於本體133在橫截導線部132的延伸方向的截面積(也就是圖1B中本體133的面積)。在圖3中,根基136b在橫截該導線部132b的延伸方向的截面積(也就是圖3中根基136b的面積)大於本體133b在橫截該導線部132b的延伸方向的截面積(也就是圖3中本體133b的面積)。
換句話說,在圖1B中,本體133佔導線部132較大的一部分,根基136佔導線部132較小的一部分。在圖3中,本體133b佔導線部132b較小的一部分,根基136b佔導線部132b較大的一部分,這可使得重配置線路層130b的導線部132b與第一圖案化絕緣層110b之間存在更大的附著面積,而具有更佳的穩固性。此外,隨著根基136b的長度增加,第一圖案化絕緣層110b的厚度及凹槽114b的長寬也可以對應地調整。當然,在其他的實施例中,根基在橫截導線部的延伸方向的截面積也可以等於本體在橫截導線部的延伸方向的截面積。
請參閱圖4,圖4的重配置線路結構100c與圖3的重配置線路結構100b的主要差異在於,在本實施例中,凹槽114c的深度等於第一圖案化絕緣層110c的厚度。因此,在製作第一圖案化絕緣層110c時可採用正形光阻或負型光阻,對第一絕緣層進行一次曝光顯影的圖案化程序即可。
同樣地,圖4的根基136c佔導線部132c較大的一部分,這可使得重配置線路層130c的導線部132c與第一圖案化絕緣層110c之間存在更大的附著面積,而具有更佳的穩固性。
請參閱圖5與圖6,圖5的重配置線路結構100d、圖6的重配置線路結構100e與圖3的重配置線路結構100的主要差異在於:在圖3中,第一圖案化絕緣層110b的凹槽114b的寬度在不同深度時原則上是相同的,且重配置線路層130b的導線部132b的根基136b的寬度沿著遠離本體133b的方向原則上是相同的。在圖5中,第一圖案化絕緣層110d的凹槽114d的寬度隨深度越大呈漸縮,且重配置線路層130d的導線部132d的根基136d的寬度沿著遠離本體133d的方向呈漸縮。
在圖6中,第一圖案化絕緣層110e的凹槽114e的寬度隨深度越大呈漸擴,且重配置線路層130e的導線部132e的根基136e的寬度沿著遠離本體133e的方向呈漸擴。值得一提的是,在圖6中,根基136e最寬處仍是小於本體133e的寬度。但在其他實施例中,根基136e最寬處可以等於或是大於本體133e的寬度。
圖7A是依照本發明的一實施例的一種重配置線路結構的局部剖面示意圖。圖7B是圖7A的重配置線路結構的重配置線路層的俯視示意圖。請參閱圖7A與圖7B,本實施例的重配置線路結構100f與圖1A的重配置線路結構100的主要差異在,在本實施例中,第一圖案化絕緣層110f包括分離的多個凹槽114f,重配置線路層130f的導線部132f包括分離的多個樁狀根基136f。凹槽114f的數量與位置對應於根基136f的數量與位置。當然,根基136f與凹槽114f的形狀與數量並不以圖面為限。
本實施例的重配置線路結構100f藉由第一圖案化絕緣層110f的這些凹槽114f與導線部132f的這些根基136f的搭配來增加導線部132f與第一圖案化絕緣層110f之間的附著面積,同樣地也可以使導線部132f剝離(peeling)於第一圖案化絕緣層110f的機率有效地被降低,而使得重配置線路層130f的導線部132f在基材10上具有較佳的結構穩定度。
圖8至圖11分別是依照本發明的其他實施例的多種重配置線路結構的導線部的本體的俯視示意圖。請先參閱圖8,圖1C的本體133與圖8的本體133g的主要差異在於,在圖1C中,導線部132的本體133在沿著導線部132的延伸方向(圖面的左右方向)上呈現等寬。在本實施例中,本體133g在沿著導線部的延伸方向上包括交替相連的多個放大區134g及多個連接區135g,連接區135g的寬度可以約接近圖1C的導線部132的本體133的寬度,而這些放大區134g的寬度分別大於這些連接區135g的寬度。
換句話說,在本實施例中,由於本體133g具有這些放大區134g,本體133g與下方的第一圖案化絕緣層110(繪示於圖1B)之間會具有更大的附著面積,因此,導線部剝離於第一圖案化絕緣層110的機率可被降低。在圖8中,這些放大區134g的形狀為矩形,但放大區134g的形狀並不以此為限制。
請參閱圖9至圖11,圖9至圖11的這些本體133h、133i、133j與圖8的本體133g的主要差異在,在圖9中,這些放大區134h的形狀為圓形。在圖10中,這些放大區134i的形狀為橢圓形。在圖11中,這些放大區134j的形狀為菱形。在其他實施例中,放大區的形狀也可以是不規則形,只要放大區的寬度大於連接區的寬度即可,放大區的形狀並不以上述為限制。
此外,需說明的是,圖8至圖11僅是示意性地繪示出導線部的本體133g、133h、133i、133j的形狀,上述本體133g、133h、133i、133j所搭配的根基可以是如圖1C所示的單一個條狀的根基136或是如圖7B所示的多個樁狀的根基136f,又或者也可以是多個短條狀的根基,上述的這些本體133g、133h、133i、133j可分別與不同形式的根基136、136f搭配。
換句話說,若採用圖8至圖11所示的重配置線路層,由於導線部的本體133g、133h、133i、133j除了連接區135g、135h、135i、135j之外還具有寬度更大的放大區134g、133h、133i、133j,因此,除了如前述實施例中提到的透過根基136、136f伸入凹槽114、114f來增加附著面積之外,本體133g、133h、133i、133j與第一圖案化絕緣層之間的附著面積也會增加,而使得重配置線路層的導線部在基材上具有較佳的結構穩定度。
圖12至圖14分別是依照本發明的其他實施例的多種重配置線路結構隱藏第二圖案化絕緣層的剖面示意圖。請先參閱圖12,圖12與圖1B的差別在於,在圖1B中,圖案化金屬複合層140配置於重配置線路層130上,也就是說,重配置線路層130與圖案化金屬複合層140是銅/鎳/金的疊層。在圖12中,重配置線路結構100k沒有圖案化金屬複合層140配置於重配置線路層130上,也就是說,在圖12中,只有例如是銅的本體133凸出於第一圖案化絕緣層110上。
請參閱圖13,圖13與圖4的差別同樣在於,在圖13中,重配置線路結構100l沒有圖案化金屬複合層140配置於重配置線路層130c上,也就是說,在圖13中,只有例如是銅的本體133c凸出於第一圖案化絕緣層110c上。
請參閱圖14,圖14與圖13的差異在於,在圖13中,重配置線路層130c的導線部為本體133c與根基136c組成的T型結構。在圖14中,重配置線路層130m的導線部只有位於第一圖案化絕緣層110內的根基136m,而呈現出I型結構,圖14所示的重配置線路結構100m可以是將圖13的重配置線路結構100l透過蝕刻的方式移除本體133c而得到,但重配置線路結構100m的形成方式並不以此為限制。
綜上所述,本發明的重配置線路結構藉由在第一圖案化絕緣層形成凹槽,且重配置線路層的導線部包括本體及凸出於本體的根基,除了導線部的本體附著於第一圖案化絕緣層的面積之外,還透過根基伸入凹槽來增加附著面積,以降低重配置線路層的導線部剝離(peeling)於第一圖案化絕緣層的機率,而使得重配置線路層的導線部在基材上具有較佳的結構穩定度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
W1、W2、W3‧‧‧寬度
10‧‧‧基材
12‧‧‧接墊
14‧‧‧保護層
16‧‧‧第一開口
100、100a、100b、100c、100d、100e、100f、100k、100l、100m‧‧‧重配置線路結構
110、110a、110b、110c、110d、110e、110f‧‧‧第一圖案化絕緣層
112‧‧‧第二開口
114、114a、114b、114c、114d、114e、114f‧‧‧凹槽
120‧‧‧球底金屬層
130、130b、130c、130d、130e、130f、130m‧‧‧重配置線路層
131‧‧‧接墊部
132、132b、132c、132d、132e、132f‧‧‧導線部
133、133b、133c、133d、133e、133g、133h、133i、133j‧‧‧本體
134g、134h、134i、134j‧‧‧放大區
135g、135h、135i、135j‧‧‧連接區
136、136b、136c、136d、136e、136f、136m‧‧‧根基
140‧‧‧圖案化金屬複合層
150‧‧‧第二圖案化絕緣層
10‧‧‧基材
12‧‧‧接墊
14‧‧‧保護層
16‧‧‧第一開口
100、100a、100b、100c、100d、100e、100f、100k、100l、100m‧‧‧重配置線路結構
110、110a、110b、110c、110d、110e、110f‧‧‧第一圖案化絕緣層
112‧‧‧第二開口
114、114a、114b、114c、114d、114e、114f‧‧‧凹槽
120‧‧‧球底金屬層
130、130b、130c、130d、130e、130f、130m‧‧‧重配置線路層
131‧‧‧接墊部
132、132b、132c、132d、132e、132f‧‧‧導線部
133、133b、133c、133d、133e、133g、133h、133i、133j‧‧‧本體
134g、134h、134i、134j‧‧‧放大區
135g、135h、135i、135j‧‧‧連接區
136、136b、136c、136d、136e、136f、136m‧‧‧根基
140‧‧‧圖案化金屬複合層
150‧‧‧第二圖案化絕緣層
圖1A是依照本發明的一實施例的一種重配置線路結構的局部剖面示意圖。 圖1B是圖1A的重配置線路結構的沿A-A線段且隱藏基材與第二圖案化絕緣層的剖面示意圖。 圖1C是圖1A的重配置線路結構的重配置線路層的俯視示意圖。 圖1D是依照本發明的一實施例的一種重配置線路結構的製作方法的步驟示意圖。 圖2至圖6分別是依照本發明的其他實施例的多種重配置線路結構隱藏第二圖案化絕緣層的剖面示意圖。 圖7A是依照本發明的一實施例的一種重配置線路結構的局部剖面示意圖。 圖7B是圖7A的重配置線路結構的重配置線路層的俯視示意圖。 圖8至圖11分別是依照本發明的其他實施例的多種重配置線路結構的導線部的本體的俯視示意圖。 圖12至圖14分別是依照本發明的其他實施例的多種重配置線路結構隱藏第二圖案化絕緣層的剖面示意圖。
W1、W2、W3‧‧‧寬度
14‧‧‧保護層
100‧‧‧重配置線路結構
110‧‧‧第一圖案化絕緣層
114‧‧‧凹槽
120‧‧‧球底金屬層
130‧‧‧重配置線路層
132‧‧‧導線部
133‧‧‧本體
136‧‧‧根基
140‧‧‧圖案化金屬複合層
Claims (11)
- 一種重配置線路結構,配置於一基材上,該基材具有一接墊與一保護層,其中該保護層具有一第一開口,且該第一開口暴露出部分的該接墊,該重配置線路結構包括: 一第一圖案化絕緣層,配置於該保護層上且包括一第二開口及至少一凹槽,其中該第二開口對應於該第一開口以暴露部分的該接墊; 一重配置線路層,配置於該第一圖案化絕緣層上且包括一接墊部及一導線部,其中該接墊部位於該第一圖案化絕緣層上,該導線部包括一本體及凸出於該本體的至少一根基,該本體位於該第一圖案化絕緣層上從該接墊部延伸至該第一開口與該第二開口內,以與該接墊連接,該至少一根基伸入該至少一凹槽;以及 一第二圖案化絕緣層,設置於該第一圖案化絕緣層上,該第二圖案化絕緣層覆蓋該導線部且暴露部分的該接墊部。
- 如申請專利範圍第1項所述的重配置線路結構,其中該至少一凹槽包括一條狀凹溝或是分離的多個凹槽,該至少一根基包括一條狀根基或是分離的多個樁狀根基,且該至少一凹槽的數量與位置對應於該至少一根基的數量與位置。
- 如申請專利範圍第1項所述的重配置線路結構,其中各該根基的寬度小於該本體的寬度。
- 如申請專利範圍第1項所述的重配置線路結構,其中各該根基的寬度沿著遠離該本體的方向漸縮、漸擴或不變。
- 如申請專利範圍第1項所述的重配置線路結構,其中各該根基在橫截該導線部的延伸方向的一截面積小於、等於或大於該本體在橫截該導線部的延伸方向的一截面積。
- 如申請專利範圍第1項所述的重配置線路結構,其中該凹槽的深度小於或等於該第一圖案化絕緣層的厚度。
- 如申請專利範圍第1項所述的重配置線路結構,其中該導線部的該本體在沿著該導線部的延伸方向上包括交替相連的多個放大區及多個連接區,該些放大區的寬度分別大於該些連接區的寬度,該些放大區的形狀包括圓形、橢圓形、矩形、菱形或不規則形。
- 如申請專利範圍第1項所述的重配置線路結構,更包括: 一球底金屬(Under Bump Metallurgic,UBM)層,配置於該重配置線路層與該第一圖案化絕緣層之間以及該重配置線路層與該接墊之間。
- 如申請專利範圍第1項所述的重配置線路結構,更包括: 一圖案化金屬複合層,配置於該重配置線路層上,該圖案化金屬複合層的寬度大於該重配置線路層的寬度。
- 一種重配置線路結構的製作方法,包括: 提供一基材,其中該基材具有一接墊與一保護層,該保護層具有一第一開口,且該第一開口暴露出部分的該接墊; 形成一第一絕緣層於該保護層上; 對該第一絕緣層進行兩次圖案化程序,以製作出一第二開口與至少一凹槽,而形成一第一圖案化絕緣層,其中該至少一凹槽的深度小於該第二開口的深度; 形成一重配置線路層於該第一圖案化絕緣層上,其中該重配置線路層包括一接墊部及一導線部,該接墊部位於該第一圖案化絕緣層上,該導線部包括一本體及凸出於該本體的至少一根基,該本體位於該第一圖案化絕緣層上從該接墊部延伸至該第一開口與該第二開口內,以與該接墊連接,該至少一根基伸入該至少一凹槽;以及 形成一第二圖案化絕緣層於該第一圖案化絕緣層上且覆蓋該導線部以及該接墊部的周圍,該第二圖案化絕緣層並暴露部分該接墊部。
- 如申請專利範圍第10項所述的重配置線路結構的製作方法,更包括: 在形成該重配置線路層之前,形成一球底金屬層於該第一圖案化絕緣層上,該球底金屬層覆蓋該接墊及部分的該第一圖案化絕緣層。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105138521A TWI610410B (zh) | 2016-11-23 | 2016-11-23 | 重配置線路結構及其製作方法 |
US15/455,140 US9859239B1 (en) | 2016-11-23 | 2017-03-10 | Re-distribution layer structure and manufacturing method thereof |
CN201710161229.7A CN108091626B (zh) | 2016-11-23 | 2017-03-17 | 重配置线路结构及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105138521A TWI610410B (zh) | 2016-11-23 | 2016-11-23 | 重配置線路結構及其製作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI610410B true TWI610410B (zh) | 2018-01-01 |
TW201820564A TW201820564A (zh) | 2018-06-01 |
Family
ID=60788739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105138521A TWI610410B (zh) | 2016-11-23 | 2016-11-23 | 重配置線路結構及其製作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9859239B1 (zh) |
CN (1) | CN108091626B (zh) |
TW (1) | TWI610410B (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200910477A (en) * | 2007-08-16 | 2009-03-01 | Fupo Electronics Corp | Solder pad re-distribution process and integrated circuit chip applying the same |
TW200924086A (en) * | 2007-11-16 | 2009-06-01 | Fupo Electronics Corp | Roughened structure for rearranged bonding pad and its manufacturing method |
TW201044471A (en) * | 2009-06-03 | 2010-12-16 | Advanced Semiconductor Eng | Semiconductor packages and manufacturing thereof |
TW201421590A (zh) * | 2012-11-19 | 2014-06-01 | Powertech Technology Inc | 增進底膠附著力之凸塊製程 |
TW201630133A (zh) * | 2015-02-11 | 2016-08-16 | 東琳精密股份有限公司 | 半導體封裝結構及其製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4626063B2 (ja) * | 2001-02-05 | 2011-02-02 | ソニー株式会社 | 半導体装置の製造方法 |
KR100546346B1 (ko) * | 2003-07-23 | 2006-01-26 | 삼성전자주식회사 | 재배선 범프 형성방법 및 이를 이용한 반도체 칩과 실장구조 |
US7402908B2 (en) | 2005-05-05 | 2008-07-22 | Micron Technology, Inc. | Intermediate semiconductor device structures |
US8058726B1 (en) * | 2008-05-07 | 2011-11-15 | Amkor Technology, Inc. | Semiconductor device having redistribution layer |
JP5582811B2 (ja) * | 2010-02-15 | 2014-09-03 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US8269348B2 (en) * | 2010-02-22 | 2012-09-18 | Texas Instruments Incorporated | IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch |
US8441127B2 (en) * | 2011-06-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace structures with wide and narrow portions |
US8900929B2 (en) * | 2012-03-21 | 2014-12-02 | Stats Chippac, Ltd. | Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation |
US10804153B2 (en) * | 2014-06-16 | 2020-10-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method to minimize stress on stack via |
-
2016
- 2016-11-23 TW TW105138521A patent/TWI610410B/zh active
-
2017
- 2017-03-10 US US15/455,140 patent/US9859239B1/en active Active
- 2017-03-17 CN CN201710161229.7A patent/CN108091626B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200910477A (en) * | 2007-08-16 | 2009-03-01 | Fupo Electronics Corp | Solder pad re-distribution process and integrated circuit chip applying the same |
TW200924086A (en) * | 2007-11-16 | 2009-06-01 | Fupo Electronics Corp | Roughened structure for rearranged bonding pad and its manufacturing method |
TW201044471A (en) * | 2009-06-03 | 2010-12-16 | Advanced Semiconductor Eng | Semiconductor packages and manufacturing thereof |
TW201421590A (zh) * | 2012-11-19 | 2014-06-01 | Powertech Technology Inc | 增進底膠附著力之凸塊製程 |
TW201630133A (zh) * | 2015-02-11 | 2016-08-16 | 東琳精密股份有限公司 | 半導體封裝結構及其製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN108091626A (zh) | 2018-05-29 |
TW201820564A (zh) | 2018-06-01 |
CN108091626B (zh) | 2020-03-13 |
US9859239B1 (en) | 2018-01-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5308145B2 (ja) | 半導体装置 | |
US7285867B2 (en) | Wiring structure on semiconductor substrate and method of fabricating the same | |
US11626393B2 (en) | Semiconductor package and method of fabricating the same | |
TWI495064B (zh) | 晶圓級半導體封裝件及其製造方法 | |
US8097941B2 (en) | Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof | |
US20180090460A1 (en) | Wafer level package and method | |
US20030102551A1 (en) | Semiconductor device and method for manufacturing | |
JP2017505999A (ja) | 金属ポスト相互接続部を備えた下部パッケージ | |
JP2007115776A (ja) | 半導体チップ及びその製造方法 | |
JP2012054359A (ja) | 半導体装置および半導体装置の製造方法 | |
KR20200068958A (ko) | 배선 구조체 및 이의 형성 방법 | |
TW202029364A (zh) | 半導體封裝及其製造方法 | |
JP2009177072A (ja) | 半導体装置及びその製造方法 | |
JP2009124042A (ja) | 半導体装置 | |
JP4959538B2 (ja) | 半導体装置とその製造方法及び電子装置 | |
TWI607535B (zh) | 重配置線路結構及其製作方法 | |
TWI610410B (zh) | 重配置線路結構及其製作方法 | |
JP4506767B2 (ja) | 半導体装置の製造方法 | |
KR100806350B1 (ko) | 반도체 소자 패키지 및 그 제조 방법 | |
JP2004172163A (ja) | 半導体装置及びその製造方法 | |
JP2008028109A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP4099667B2 (ja) | 半導体装置の製造方法 | |
JP5068830B2 (ja) | 半導体装置 | |
CN115547853A (zh) | 半导体封装及其制造方法 | |
JP2013239756A (ja) | 半導体装置 |