TW201630133A - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

Info

Publication number
TW201630133A
TW201630133A TW105101058A TW105101058A TW201630133A TW 201630133 A TW201630133 A TW 201630133A TW 105101058 A TW105101058 A TW 105101058A TW 105101058 A TW105101058 A TW 105101058A TW 201630133 A TW201630133 A TW 201630133A
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor package
package structure
gold seed
metal barrier
Prior art date
Application number
TW105101058A
Other languages
English (en)
Other versions
TWI562297B (en
Inventor
胡玉山
Original Assignee
東琳精密股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東琳精密股份有限公司 filed Critical 東琳精密股份有限公司
Publication of TW201630133A publication Critical patent/TW201630133A/zh
Application granted granted Critical
Publication of TWI562297B publication Critical patent/TWI562297B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05609—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明提出一半導體封裝結構及其製造方法，該半導體封裝結構包含一晶片、一金屬阻障層、一介電層、一第一金種層及一第二金種層。晶片具有一頂面、複數個連接墊及一保護層，連接墊及保護層設置於頂面上，而保護層部分地覆蓋連接墊；金屬阻障層設置於各連接墊上；介電層設置於保護層及金屬阻障層上，且具有複數個貫穿槽，以使金屬阻障層從介電層暴露出；第一金種層設置於介電層及暴露出的金屬阻障層上；第二金種層設置於第一金種層上。藉此，金屬阻障層可有效避免晶片的連接墊於製造過程中受到損害。

Description

半導體封裝結構及其製造方法
本發明有關一種封裝結構及其製造方法，特別關於一種半導體封裝結構及其製造方法。
對於覆晶型(flip chip)晶片的封裝而言，最終都會設置多個凸塊(bump)於晶片上，以使晶片能透過該些凸塊與其他裝置產生電性連接。
凸塊設置於晶片上的方式應可分為：直接植入凸塊(Direct Bump)、保護層重佈(Re-passivation)、線路層重佈(Re-distribution)三種等。在保護層重佈及線路層重佈的方式中，大都會使用到光蝕刻製程(Photolithography)來形成一個以上的圖案化的保護層(或稱介電層)。光蝕刻製程完成後，接著會進行一清潔步驟，以將殘留的顯影液(developer)或其他污染物移除，避免該些殘留物或污染物對晶片的連接墊(pad)造成損害(例如連接墊被氧化、腐蝕、抬升等)。例如台灣專利公告號488052即有揭露上述的光蝕刻製程及清潔步驟。
然而，該清潔步驟仍難以將該些殘留物或污染物完全移除，造成晶片的連接墊(pad)仍有可能被損害。
此外，晶片在進行凸塊製程前，晶片會先收納在收容盒或收納櫃中。在收納時，晶片的連接墊會接觸到空氣，故仍有可能會氧化。
有鑑於此，提供一種可改善至少一種上述缺失的技術方案，乃為此業界待解決的問題。
本發明之一目的在於提供一種半導體封裝結構及其製造方法，其能解決上述先前技術中的至少一技術問題，即至少可使晶片的連接墊不易受損害。
為達上述目的，本發明所揭露的一種半導體封裝結構之製造方法包含：提供一晶片，該晶片具有一頂面、複數個連接墊及一保護層，該等連接墊及該保護層設置於該頂面上，而該保護層部分地覆蓋該等連接墊；形成一金屬阻障層於各該連接墊上；形成一第一介電層於該保護層及該金屬阻障層上；移除部分的該第一介電層，以使該金屬阻障層從該第一介電層暴露出；以化鍍方式(electroless plating)形成一第一金種層於該第一介電層及暴露出的該金屬阻障層上；以及以化鍍方式形成一第二金種層於該第一金種層上。
為達上述目的，本發明所揭露的一種半導體封裝結構包含：一晶片，具有一頂面、複數個連接墊及一保護層，該等連接墊及該保護層設置於該頂面上，而該保護層部分地覆蓋該等連接墊；一金屬阻障層，設置於各該連接墊上；一第一介電層，設置於該保護層及該金屬阻障層上，且具有複數個貫穿槽，以使該金屬阻障層從該第一介電層暴露出；一第一金種層，設置於該第一介電層及暴露出的該金屬阻障層上；以及一第二金種層，設置於該第一金種層上。
為讓上述目的、技術特徵及優點能更明顯易懂，下文係以較佳之實施例配合所附圖式進行詳細說明。
1、1’‧‧‧半導體封裝結構
10‧‧‧晶片
11‧‧‧頂面
12‧‧‧連接墊
13‧‧‧保護層
20‧‧‧金屬阻障層
30‧‧‧第一介電層
31‧‧‧貫穿槽
40A‧‧‧第一金種層
40B‧‧‧第二金種層
50‧‧‧第二介電層
60‧‧‧重分配電路層
70‧‧‧第三介電層
71‧‧‧貫穿槽
80‧‧‧凸塊
90‧‧‧合金層
S1~S11‧‧‧步驟
第1圖為依據本發明之第一較佳實施例的半導體封裝結構的示意圖。
第2圖為依據本發明之第二較佳實施例的半導體封裝結構的示意圖。
第3A圖至第5D圖為依據本發明之第三較佳實施例的半導體封裝結構的製造方法所包含的若干步驟的示意圖，其中第3C圖為第3B圖的部分放大詳圖，而第5C圖為第5B圖的部分放大詳圖。
本發明為一種半導體封裝結構及其製造方法，以下將先說明本發明的半導體封裝結構。
請參閱第1圖所示，為依據本發明之第一較佳實施例的半導體封裝結構的示意圖。該半導體封裝結構1可供凸塊直接設置或透過重分配電路層(圖未示)間接設置於其上，該半導體封裝結構1包含：一晶片10、一金屬阻障層20、一第一介電層30、一第一金種層40A及一第二金種層40B；以下將依序說明各元件之內容。
晶片10為一已藉由半導體製程而形成有積體電路(圖未示)的晶片。晶片10具有一頂面11及複數個連接墊12(本實施例僅以一個為例)，而該等連接墊12設置於晶片10的頂面(或稱主動面)11上，且其製造材料可包含鋁、銅鋁、錫等金屬或合金。晶片10還可具有一保護層13，保護層13也設置於晶片10的頂面11上，並部分地覆蓋連接墊12，例如覆蓋連接墊12的周緣，以使得連接墊12的部分的頂面被暴露出。
該金屬阻障層20設置於各該連接墊12上(即每一個連接墊12上都設置有金屬阻障層20)，以將被暴露出的連接墊12的頂面覆蓋住，從而保護連接墊12。也就是，金屬阻障層20能有效地阻擋空氣或製程中的物質接觸到連接墊12，避免空氣或該些物質對連接墊12造成損害(例如氧化、腐蝕或抬升等)。
較佳地，該金屬阻障層20可藉由化鍍方式(electroless plating)來設置於連接墊12上，以減少製造成本；此外，化鍍出的金屬阻障層20可與後述的第一介電層30平順地結合，使得兩者之間的結合力較強。該金屬阻障層20的製造材料可包含鎳或鈦，以使得後述的第一金種層40A易於設置於金屬阻障層20上；換言之，金屬阻障層20的製造材料係因應第一金種層40A的製造材料而選擇。
該第一介電層30設置於該晶片10的保護層13上、以及該金屬阻障層20上，且該第一介電層30具有複數個貫穿槽31(圖中以一個為例)，以使該金屬阻障層20從該第一介電層30的貫穿槽31暴露出。該些貫穿槽31的開口可等於或小於金屬阻障層20的頂面，以使得金屬阻障層20的頂面完全或部分地暴露出。而較佳地，金屬阻障層20的頂面的周緣被第一介電層30覆蓋，故金屬阻障層20的頂面被部分地暴露出。
此外，該第一介電層30較佳地可完全地覆蓋該晶片10的保護層13，且該第一介電層30的製造材料可為BCB或PI等介電材料。
該第一金種層40A設置於該第一介電層30及暴露出的該金屬阻障層20上，也就是，第一金種層40A會從第一介電層30的頂面連續地延伸至貫穿槽31的壁面、再延伸至該金屬阻障層20的位於貫穿槽31內的頂面。此外，第一金種層40A可僅設置於第一介電層30的部分的頂面。
該第一金種層40A可藉由化鍍方式來設置於第一介電層30及金屬阻障層20上，且當金屬阻障層20亦是藉由化鍍方式來製造時，第一金種層40A可容易地化鍍於該金屬阻障層20上，且第一金種層40A與該金屬阻障層20之間的結合性可較好。
先前曾論述到，金屬阻障層20的製造材料係因應第一金種層40A的製造材料而選擇，而較佳地，該金屬阻障層20與該第一金種層40A的製造材料可為相同，以使兩者的結合性更好；因此，第一金種層40A及金屬阻障層20的製造材料可同為包含鎳或鈦。
該第二金種層40B設置於該第一金種層40A上，且較佳地，可完全覆蓋住該第一金種層40A的頂面；因此，第二金種層40B的分佈範圍會跟第一金種層40A一致，也就是，位於該第一介電層30及暴露出的該金屬阻障層20之上。
該第二金種層40B亦可藉由化鍍方式來設置於第一金種層40A上，且第二金種層40B可容易地化鍍於該第一金種層40A上，從而使得第一金種層40A與第二金種層40B之間的結合性較好。較佳地，第二金種層40B的製造材料可包含銅或金，以便於其他實施例中的金凸塊、銅凸塊或重分配電路層(圖未示)設置於第二金種層40B上。
請參閱第2圖所示，為依據本發明之第二較佳實施例的半導體封裝結構的示意圖。該半導體封裝結構1’包含了該半導體封裝結構1的各元件，即包含一晶片10、一金屬阻障層20、一第一介電層30、一第一金種層40A及一第二金種層40B，故該些元件的技術內容可參照該半導體封裝結構1的對應者。半導體封裝結構1’更可包含：一重分配電路層60、一第三介電層70及複數個凸塊80；以下依序說明這些元件。
該重分配電路層60設置於該第二金種層40B上，且較佳 地，可完全覆蓋住該第二金種層40B的頂面。因此，重分配電路層60的分佈範圍可跟第二金種層40B一致；換言之，當第一及第二金種層40A及40B僅位於部分的第一介電層30上時，該重分配電路層60亦只會位於部分的第一介電層30之上。此外，第一及第二金種層40A及40B的側面(直立面)與重分配電路層60的側面可為共面。
另外，該重分配電路層60的製造材料可相同於第二金種層40B的製造材料，以便於兩者結合。因此，該重分配電路層60與該第二金種層40B的製造材料例如可包含銅。
該第三介電層70設置於該重分配電路層60上，且具有複數個貫穿槽71(圖中以一個為例)，以使部分的該重分配電路層60從該第三介電層70的貫穿槽71暴露出；換言之，該重分配電路層60的部分的頂面沒有被第三介電層70覆蓋到。該第三介電層70可將第一及第二金種層40A及40B的兩側面(直立面)與重分配電路層60的兩側面覆蓋。
該些凸塊80設置於被該些貫穿槽71暴露出的該重分配電路層60上，換言之，該些凸塊80分別設置於該些貫穿槽71中，以電性連接該重分配電路層60；該些凸塊80可為金凸塊或銅凸塊。
半導體封裝結構1’可選擇地包含一合金層90，該合金層90設置於暴露出的該重分配電路層60及該等凸塊80之間；換言之，該合金層90設置於重分配電路層60的位於該些貫穿槽71中的頂面上，然後凸塊80再設置於合金層90上。該合金層90用以增加凸塊80與重分配電路層60之間的結合力，故合金層90的製造材料跟凸塊80與重分配電路層60的製造材料相關，可為鎳、銅及錫等材料組合而成。例如，合金層90可為鎳銅合金或鎳錫合金。
另說明的是，該合金層90在設置後，其一部分可跟凸塊80結合成一體、而另一部分可跟重分配電路層60結合成一體。因此，若將半導體封裝結構1’剖切開來觀察其剖面時，該合金層90不易被區隔出。
上述為該半導體封裝結構1及1’之各元件之技術內容的說明，而該半導體封裝結構1及1’至少可提供以下特點：金屬阻障層20可保護晶片10的連接墊12不易受到損害，尤其可減少連接墊12的氧化；當連接墊12的氧化減少(即氧化層較少)時，連接墊12的導通電阻(Rds-on) 可相應地減少。此外，金屬阻障層20可藉由化鍍的方式來形成，故可不需藉由物理氣相沈積(PVD)等製造成本較高的方式來製作。再者，當金屬阻障層20藉由化鍍的方式來形成時，同樣是化鍍所形成的第一金種層40A可容易地形成於金屬阻障層20上，形成緊密地結合。化鍍所形成的金屬阻障層20亦可與第一介電層30平順地結合。
接著說明依據本發明第三較佳實施例的半導體封裝結構之製造方法，該製造方法至少可製作出上述該等半導體封裝結構1及1’，因此半導體封裝結構1及1’的技術內容可供該製造方法參照，反之亦可。然而需說明的是，半導體封裝結構1及1’的製造方法並不侷限於此。
該製造方法可開始於步驟S1(如第3A圖所示)，也就是提供一晶片10。該晶片10具有一頂面11、複數個連接墊12、及一保護層13，該等連接墊12及保護層13設置於晶片10的頂面11上，保護層13部分地覆蓋連接墊12，以使得連接墊12的部分的頂面被暴露出。
接著進行步驟S2(如第3B及第3C圖所示)，形成一金屬阻障層20於各該連接墊12上。每一個連接墊12上都設置有金屬阻障層20，以將被暴露出的連接墊12的頂面覆蓋住，從而保護連接墊12。如此，金屬阻障層20能有效地阻擋空氣或後續製程中的物質接觸到連接墊12，避免空氣或該些物質對連接墊12造成損害。較佳地，該金屬阻障層20可藉由化鍍方式來形成於連接墊12上，以減少金屬阻障層20的製造成本；該金屬阻障層20的製造材料可包含鎳或鈦。
接著進行步驟S3(如第3D圖所示)，形成一第一介電層30於該保護層13及該金屬阻障層20上，然後移除部分的該第一介電層30，以使該金屬阻障層20從該第一介電層30暴露出。具體而言，第一介電層30可先完整地覆蓋保護層13及該金屬阻障層20，然後藉由光蝕刻製程(曝光、顯影及固化)或雷射加工等方式來移除部分的該第一介電層30(即形成複數個貫穿槽31)，從而讓金屬阻障層20的部分或全部的頂面暴露出。
當使用光蝕刻製程來形成第一介電層30的貫穿槽31後，殘留的顯影液或其他污染物難以對晶片10的連接墊12造成損害，原因在於金屬阻障層20可降低該些物質接觸到連接墊12的可能性。
接著進行步驟S4(如第3E圖所示)，以化鍍方式形成一第一 金種層40A於該第一介電層30及暴露出的該金屬阻障層20上，然後再同樣以化鍍方式形成一第二金種層40B於該第一金種層40A上。換言之，第一金種層40A及第二金種層40B係依序地藉由化鍍方式形成於第一介電層30及暴露出的該金屬阻障層20上。較佳地，該金屬阻障層20與該第一金種層400A的製造材料係相同，故該第一金種層400A的製造材料可包含鎳或鈦；而該第二金種層40B的製造材料可包含銅或金。
當步驟S1至S4執行完後，可製造出第一實施例中的半導體封裝結構1。
值得一提的是，當步驟S2(形成一金屬阻障層20於各該連接墊12上)完成後，可選擇地將該晶片10暫時收納於晶元盒等收容裝置之中，以待後續步驟需要進行時、再取出。由於晶片10的連接墊12有金屬阻障層20的保護，故收容裝置內的空氣不易接觸到連接墊12，連接墊12即不易氧化。
爾後，可選擇地執行步驟S5至S8，以在半導體封裝結構1形成一重分配電路層60。首先，如第4A圖所示的步驟S5中，形成一第二介電層50於該第二金種層40B上，然後移除部分的該第二介電層50，以使部分的該第二金種層40B從該第二介電層50暴露出。易言之，該第二介電層50先是覆蓋第二金種層40B的頂面，然後藉由光蝕刻製程或雷射加工等方式來移除部分的該第二介電層50(即形成複數個貫穿槽51)，從而讓第二金種層40B的部分的頂面暴露出。第二介電層50的貫穿槽51的形狀會對應重分配電路層60的形狀。
接著，如第4B圖所示的步驟S6中，形成一重分配電路層60於暴露出的該第二金種層40B上；易言之，重分配電路層60係形成於第二介電層50的貫穿槽51中，並接觸於第二金種層40B。該重分配電路層與60與第二金種層40B的製造材料可為相同，故重分配電路層與60可由金或銅來製造出。
接著下一步驟，如第4C圖所示的步驟S7中，移除剩餘的該第二介電層50。此步驟中，用以定義重分配電路層60形狀及尺寸的第二介電層50將全部地移除，以使得第二金種層40B的頂面上僅存重分配電路層60。
最後，如第4C圖所示的步驟S8中，移除步驟S5中位於剩餘的該第二介電層50之下的該第二金種層40B及該第一金種層40A。也就是，將重分配電路層60的側面旁的第二金種層40B及第一金種層40A皆移除，以使得重分配電路層60的各部分能相分隔、不會相互電性連接。
當步驟S5至S8執行完後，半導體封裝結構1上即可形成重分配電路層60。而需說明的是，重分配電路層60亦可藉由其他方式來形成之，例如藉由印刷方式，塗佈重分配電路層60於第二金種層40B的頂面的特定處。
爾後，可選擇地執行步驟S9至S11，以設置複數個凸塊80於重分配電路層60，從而製造出半導體封裝結構1’。
首先，如第5A圖所示的步驟S9中，形成一第三介電層70於該重分配電路層60上，然後移除部分的該第三介電層70，以使部分的該重分配電路層60從該第三介電層70暴露出。易言之，該第三介電層70先是覆蓋於重分配電路層60的頂面，然後藉由光蝕刻製程或雷射加工等方式來移除部分的該第三介電層70(即形成複數個貫穿槽71)，從而讓重分配電路層60的部分的頂面暴露出。該些貫穿槽71可與該些連接墊12相偏置，故該些貫穿槽71不會位於該些連接墊12的正上方。
爾後，如第5B圖第5C圖所示的步驟S10中，形成一合金層90於暴露出的該重分配電路層60上。該合金層90會位於貫穿槽71中，並跟重分配電路層60相接觸及結合。
最後，如第5D圖所示的步驟S11中，設置複數個凸塊80於該合金層90上，該些凸塊80會分別位於該些貫穿槽71中，並與該合金層90相接觸及結合。若合金層90不需形成時，則該些凸塊80可直接設置於暴露出的該重分配電路層60上，跟重分配電路層60相接觸。
當步驟S9至S11執行完後，第二實施例中的半導體封裝結構1’即可被製造出。
綜合上述，本發明之各實施例提供至少一半導體封裝結構及一半導體封裝結構的製造方法，該半導體封裝結構包含金屬阻障層，以保護晶片的連接墊；該金屬阻障層與第一及第二金種層皆可藉由化鍍方式來形成，以節省製造成本；其餘的技術特點可參閱上述說明所述。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
1’‧‧‧半導體封裝結構
10‧‧‧晶片
11‧‧‧頂面
12‧‧‧連接墊
13‧‧‧保護層
20‧‧‧金屬阻障層
30‧‧‧第一介電層
31‧‧‧貫穿槽
40A‧‧‧第一金種層
40B‧‧‧第二金種層
60‧‧‧重分配電路層
70‧‧‧第三介電層
71‧‧‧貫穿槽
80‧‧‧凸塊
90‧‧‧合金層

Claims (19)

  1. 一種半導體封裝結構，包含：一晶片，具有一頂面、複數個連接墊及一保護層，該等連接墊及該保護層設置於該頂面上，而該保護層部分地覆蓋該等連接墊；一金屬阻障層，設置於各該連接墊上；一第一介電層，設置於該保護層及該金屬阻障層上，且具有複數個貫穿槽，以使該金屬阻障層從該第一介電層暴露出；一第一金種層，設置於該第一介電層及暴露出的該金屬阻障層上；以及一第二金種層，設置於該第一金種層上。
  2. 如請求項1所述的半導體封裝結構，其中，該金屬阻障層與該第一金種層的製造材料係相同。
  3. 如請求項2所述的半導體封裝結構，其中，該金屬阻障層與該第一金種層的製造材料包含鎳或鈦。
  4. 如請求項1所述的半導體封裝結構，其中，該第二金種層的製造材料包含銅或金。
  5. 如請求項1至4任一項所述的半導體封裝結構，其中，該第一金種層係設置於部分的該第一介電層上，而該半導體封裝結構更包含一重分配電路層，該重分配電路層設置於該第二金種層上。
  6. 如請求項5所述的半導體封裝結構，其中，該重分配電路層與該第二金種層的製造材料係相同。
  7. 如請求項6所述的半導體封裝結構，其中，該重分配電路層與 該第二金種層的製造材料包含銅。
  8. 如請求項5所述的半導體封裝結構，更包含：一第三介電層，設置於該重分配電路層上，且具有複數個貫穿槽，以使部分的該重分配電路層從該第三介電層暴露出；以及複數個凸塊，設置於暴露出的該重分配電路層上。
  9. 如請求項8所述的半導體封裝結構，更包含一合金層，其設置於暴露出的該重分配電路層及該等凸塊之間。
  10. 一種半導體封裝結構之製造方法，包含：提供一晶片，該晶片具有一頂面、複數個連接墊及一保護層，該等連接墊及該保護層設置於該頂面上，而該保護層部分地覆蓋該等連接墊；形成一金屬阻障層於各該連接墊上；形成一第一介電層於該保護層及該金屬阻障層上；移除部分的該第一介電層，以使該金屬阻障層從該第一介電層暴露出；以化鍍方式(electroless plating)形成一第一金種層於該第一介電層及暴露出的該金屬阻障層上；以及以化鍍方式形成一第二金種層於該第一金種層上。
  11. 如請求項10所述的半導體封裝結構之製造方法，其中，該金屬阻障層係以化鍍方式形成於各該連接墊上。
  12. 如請求項10或11所述的半導體封裝結構之製造方法，其中，該金屬阻障層與該第一金種層的製造材料係相同。
  13. 如請求項12所述的半導體封裝結構之製造方法，其中，該金屬 阻障層與該第一金種層的製造材料包含鎳或鈦。
  14. 如請求項10或11所述的半導體封裝結構之製造方法，其中，該第二金種層的製造材料包含銅或金。
  15. 如請求項10或11所述的半導體封裝結構之製造方法，更包含：形成一第二介電層於該第二金種層上；移除部分的該第二介電層，以使部分的該第二金種層從該第二介電層暴露出；形成一重分配電路層於暴露出的該第二金種層上；以及移除剩餘的該第二介電層以及其下的該第二金種層及該第一金種層。
  16. 如請求項15所述的半導體封裝結構之製造方法，其中，該重分配電路層與該第二金種層的製造材料係相同。
  17. 如請求項16所述的半導體封裝結構之製造方法，其中，該重分配電路層與該第二金種層的製造材料包含銅。
  18. 如請求項15所述的半導體封裝結構之製造方法，更包含：形成一第三介電層於該重分配電路層上；移除部分的該第三介電層，以使部分的該重分配電路層從該第三介電層暴露出；以及設置複數個凸塊於暴露出的該重分配電路層上。
  19. 如請求項15所述的半導體封裝結構之製造方法，更包含：形成一第三介電層於該重分配電路層上；移除部分的該第三介電層，以使部分的該重分配電路層從該第三介電層暴露出；形成一合金層於暴露出的該重分配電路層上；以及 設置複數個凸塊於該合金層上。
TW105101058A 2015-02-11 2016-01-14 Samiconductor packaging structure and manufactoring method for the same TWI562297B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/619,404 US9478512B2 (en) 2015-02-11 2015-02-11 Semiconductor packaging structure having stacked seed layers

Publications (2)

Publication Number Publication Date
TW201630133A true TW201630133A (zh) 2016-08-16
TWI562297B TWI562297B (en) 2016-12-11

Family

ID=56567032

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105101058A TWI562297B (en) 2015-02-11 2016-01-14 Samiconductor packaging structure and manufactoring method for the same

Country Status (3)

Country Link
US (1) US9478512B2 (zh)
CN (1) CN105870088A (zh)
TW (1) TWI562297B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI610410B (zh) * 2016-11-23 2018-01-01 南茂科技股份有限公司 重配置線路結構及其製作方法
TWI669788B (zh) * 2016-11-29 2019-08-21 台灣積體電路製造股份有限公司 凸塊的薄膜技術

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163661B2 (en) 2015-06-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN113140521B (zh) * 2020-01-20 2022-11-22 上海艾为电子技术股份有限公司 晶圆级封装方法以及晶圆级封装结构
KR20210126310A (ko) 2020-04-10 2021-10-20 삼성전자주식회사 씨드 구조체를 갖는 반도체 소자 및 그 형성 방법

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020640A (en) * 1996-12-19 2000-02-01 Texas Instruments Incorporated Thick plated interconnect and associated auxillary interconnect
TW488052B (en) 2001-05-16 2002-05-21 Ind Tech Res Inst Manufacture process of bumps of double layers or more
US6489229B1 (en) * 2001-09-07 2002-12-03 Motorola, Inc. Method of forming a semiconductor device having conductive bumps without using gold
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
US6750133B2 (en) * 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US7005752B2 (en) * 2003-10-20 2006-02-28 Texas Instruments Incorporated Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
US7838991B1 (en) * 2007-02-05 2010-11-23 National Semiconductor Corporation Metallurgy for copper plated wafers
WO2009078254A1 (ja) * 2007-12-17 2009-06-25 Nippon Mining & Metals Co., Ltd. 基板、及びその製造方法
US8022543B2 (en) * 2008-03-25 2011-09-20 International Business Machines Corporation Underbump metallurgy for enhanced electromigration resistance
JP4601686B2 (ja) * 2008-06-17 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US7615407B1 (en) * 2008-07-02 2009-11-10 National Semiconductor Corporation Methods and systems for packaging integrated circuits with integrated passive components
KR101483273B1 (ko) * 2008-09-29 2015-01-16 삼성전자주식회사 구리 패드와 패드 장벽층을 포함하는 반도체 소자와 그의 배선 구조 및 그 제조 방법들
TW201015718A (en) * 2008-10-03 2010-04-16 Sanyo Electric Co Semiconductor device and method for manufacturing the same
US7994045B1 (en) * 2009-09-08 2011-08-09 Amkor Technology, Inc. Bumped chip package fabrication method and structure
US8748305B2 (en) * 2009-11-17 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure for semiconductor devices
US8963316B2 (en) * 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8865585B2 (en) * 2012-07-11 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming post passivation interconnects
KR102007780B1 (ko) * 2012-07-31 2019-10-21 삼성전자주식회사 멀티 범프 구조의 전기적 연결부를 포함하는 반도체 소자의 제조방법
TW201423879A (zh) * 2012-12-10 2014-06-16 Chipbond Technology Corp 半導體製程及其結構
US9824989B2 (en) * 2014-01-17 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package and methods of forming thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI610410B (zh) * 2016-11-23 2018-01-01 南茂科技股份有限公司 重配置線路結構及其製作方法
TWI669788B (zh) * 2016-11-29 2019-08-21 台灣積體電路製造股份有限公司 凸塊的薄膜技術

Also Published As

Publication number Publication date
TWI562297B (en) 2016-12-11
US20160233182A1 (en) 2016-08-11
US9478512B2 (en) 2016-10-25
CN105870088A (zh) 2016-08-17

Similar Documents

Publication Publication Date Title
US20220157785A1 (en) 3d integrated circuit (3dic) structure
TW201630133A (zh) 半導體封裝結構及其製造方法
US9741659B2 (en) Electrical connections for chip scale packaging
TWI595576B (zh) 銅柱側壁保護
TWI499021B (zh) 半導體元件及其製造方法
TWI721038B (zh) 封裝結構、疊層封裝元件及其形成方法
TWI623064B (zh) 凸塊下金屬結構環及其相關之系統及方法
US10522438B2 (en) Package structure having under ball release layer and manufacturing method thereof
TWI556379B (zh) 半導體封裝件及其製法
US8866293B2 (en) Semiconductor structure and fabrication method thereof
TWI699861B (zh) 用於預防焊錫橋接之互連結構及相關系統及方法
US8349736B2 (en) Semiconductor device manufacturing method and semiconductor device
TWI544555B (zh) 半導體封裝結構及其製造方法
TWI601248B (zh) 電子封裝件及其製法
US9312175B2 (en) Surface modified TSV structure and methods thereof
TWI548049B (zh) 半導體結構及其製法
US11476210B2 (en) Semiconductor device and semiconductor package
JP2008218494A (ja) 半導体装置およびその製造方法
TWI596720B (zh) 封裝半導體晶粒的結構及其方法
JP5876893B2 (ja) 半導体装置及びその製造方法
JP2012119444A (ja) 半導体装置
TW201814877A (zh) 電子封裝件及其製法
CN108074895B (zh) 堆叠封装结构及其制造方法
TWI605554B (zh) 電子封裝結構及電子封裝件之製法
TWI473216B (zh) 半導體製程及其半導體結構