TWI604539B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TWI604539B
TWI604539B TW104127107A TW104127107A TWI604539B TW I604539 B TWI604539 B TW I604539B TW 104127107 A TW104127107 A TW 104127107A TW 104127107 A TW104127107 A TW 104127107A TW I604539 B TWI604539 B TW I604539B
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Taiwan
Prior art keywords
gold
tin alloy
bumps
tin
bump
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TW104127107A
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English (en)
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TW201639050A (zh
Inventor
盧東寶
王恆生
徐子涵
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南茂科技股份有限公司
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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/60—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of tin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/62—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of gold
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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    • C25D5/48—After-treatment of electroplated surfaces
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    • C25D5/505—After-treatment of electroplated surfaces by heat-treatment of electroplated tin coatings, e.g. by melting
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Description

半導體封裝及其製造方法
本揭露係關於金-錫(Au-Sn)合金凸塊以及使用金-錫合金凸塊的半導體結構。
隨著近來電子產業的進步，電子元件已經具有高性能的表現，因而產生微縮化、高密度化的封裝需求。據此，連接IC與主板的連接端子必須以更高密度進行封裝。封裝技術的高密度發展是由於積體電路(IC)的輸出入端(I/O)數目增加、而連接端子的接合方法亦變得更有效率所致。
覆晶接合技術是目前已普及的連結技術當中的一項。覆晶接合技術在現行的積體電路(IC)的製造趨勢流程的發展，主要受到幾個因素影響。第一，當使用傳統打線接合技術，其相關的寄生電感降低時，半導體裝置的電子性能可以再提升。其次，相較於打線接合技術，覆晶接合封裝可在晶片與封裝之間提供更高的互連密度。第三，覆晶接合技術所佔用的矽晶片有效使用面積較少，因而有助於節省矽面積與降低元件成本。第四，當同步接合(gang-bonding)取代連續個別接合步驟時，可降低製造成本及電性接合時間。
為了能降低接合端子的尺寸與其間距，因此在覆晶接合技術中利用金屬凸塊取代早期連結用銲球，特別是藉由改良過的線 球技術所產生的金屬凸塊。典型的作法乃是將該金屬凸塊形成在半導體晶片接墊的鋁層上。接著，利用焊料將晶片附接至基板。該金屬凸塊可使用於LCD、記憶體、微處理器與射頻積體電路(RFIC)的覆晶封裝應用中。
在各種不同的接合材料中，由於環保意識的提升，無鉛焊接凸塊近年來倍受注目。目前還有其他不同形式的材料被採用並持續發展，例如純錫(Sn)、金-錫(Au-Sn)、銅-錫(Cu-Sn)、銀-錫(Ag-Sn)等。在本發明中，將進一步討論電鍍的金-錫(Au-Sn)凸塊。
本發明提供一種半導體封裝，其包括半導體晶片。該半導體晶片包含一主動面及設置於主動面上之傳導墊；電鍍金-錫(Au-Sn)合金凸塊，其位於該半導體晶片之主動面上；以及基板，其包括與該電鍍金-錫合金凸塊電性耦合的導線，其中該電鍍金-錫合金凸塊具有重量百分比約Au0.85Sn0.15至約Au0.75Sn0.25的組成成分，從接近該主動面的一端均勻分布至接近該基板的一端。
本發明提供一種半導體封裝，其包括半導體晶片，該半導體晶片包含一主動面及設置於主動表面上的傳導墊；電鍍金-錫合金凸塊，其位於該主動面上方；以及玻璃基板，其包含與該電鍍金-錫合金凸塊電性耦合的導線，其中該電鍍金-錫合金凸塊具有重量百分比約Au0.85Sn0.15至約Au0.75Sn0.25的組成成分，從接近該主動面的一端均勻分布至接近該玻璃基板的一端。
本揭露的一些實施例係提供一種製造半導體封裝的方法，其包括：在半導體晶片的一主動面上，形成傳導墊的圖案；在該傳導墊上方，電鍍金-錫合金凸塊；以及藉由迴銲程序或熱壓程序，將該半導體晶片接合在基板上相對應的導線上。
10‧‧‧半導體封裝
101‧‧‧電鍍金-錫(Au-Sn)合金凸塊
102‧‧‧下傳導墊
103‧‧‧裝置
105‧‧‧上傳導墊
104‧‧‧明相
107‧‧‧暗相
300‧‧‧半導體結構
301‧‧‧金-錫(Au-Sn)合金凸塊
3006‧‧‧下部
304‧‧‧基板
304a‧‧‧主動表面
302‧‧‧下傳導墊
3002‧‧‧上部
307‧‧‧介電質
305‧‧‧上傳導墊
303‧‧‧裝置
309‧‧‧凸塊下金屬(UBM)層
311‧‧‧傳導柱
400‧‧‧發光二極體結構
401a、401b‧‧‧電鍍金-錫(Au-Sn)合金凸塊
403‧‧‧基板
405‧‧‧N型GaN層
409‧‧‧P型GaN層
407‧‧‧多量子井層
411a‧‧‧n型電極
411b‧‧‧p型電極
4006‧‧‧下部
404‧‧‧基板
404A‧‧‧主動表面
402a、402b‧‧‧傳導墊
406a、406b‧‧‧接合墊
500‧‧‧覆晶薄膜(COF)封裝半導體結構
504‧‧‧可撓性薄膜
504A‧‧‧主動面
502a、502b‧‧‧傳導層
513a、513b‧‧‧金/銀凸塊
501a、501b‧‧‧電鍍金-錫(Au-Sn)合金凸塊
511a、511b‧‧‧上傳導墊
503‧‧‧裝置
506a、506b‧‧‧阻焊圖案
509‧‧‧底膠填充材料
600‧‧‧玻璃上晶片(COG)封裝半導體結構
601a與、601b‧‧‧電鍍金-錫(Au-Sn)合金凸塊
604‧‧‧玻璃基板
604A‧‧‧主動表面
602a與、602b‧‧‧傳導層
603‧‧‧半導體晶片
613a、613b‧‧‧金/銀凸塊
611a、611b‧‧‧上傳導墊
313‧‧‧第一遮罩層
313A‧‧‧開口
700’‧‧‧容器
713‧‧‧電鍍槽
711‧‧‧陽極
712‧‧‧陰極
700A‧‧‧入口
700B‧‧‧出口
413‧‧‧第一遮罩層
413A‧‧‧開口
413B‧‧‧開口
800’‧‧‧容器
811‧‧‧陽極
812‧‧‧陰極
813‧‧‧電鍍槽
800B‧‧‧出口
800A‧‧‧入口
經由以下所提供之詳細說明與所附圖式，將得以最佳方式了解本揭露之各方面特徵。值得注意的是，根據業界的標準做法，各種特徵並非依比例繪示。實際上，為了清楚解釋及說明，各種特徵的尺寸可任意放大或縮小。
圖1係根據本揭露的一些實施例說明具有電鍍金-錫(Au-Sn)合金凸塊的簡化半導體封裝之剖面圖。
圖2A係根據本揭露的一些實施例說明電鍍金-錫合金凸塊平行於支撐該電鍍金-錫合金凸塊的表面之剖面圖。
圖2B係根據本揭露的一些實施例說明電鍍金-錫合金凸塊平行於支撐該電鍍金-錫合金凸塊的表面之剖面圖。
圖3係根據本揭露的一些實施例說明具有電鍍金-錫合金凸塊的半導體結構之剖面圖。
圖4係根據本揭露的一些實施例說明具有電鍍金-錫合金凸塊的發光二極體(LED)結構之剖面圖。
圖5係根據本揭露的一些實施例說明具有電鍍金-錫合金凸塊之覆晶薄膜封裝(chip-on film，COF)半導體結構之剖面圖。
圖6係根據本揭露的一些實施例說明具有電鍍金-錫合金凸塊之玻璃覆晶結合技術(chip-on glass，COG)半導體結構之剖面圖。
圖7A至圖7F係說明圖3所示之具有電鍍金-錫合金凸塊之半導體結構的製造步驟。
圖8A至圖8D係說明圖4所示之具有電鍍金-錫合金凸塊之發光二極體(LED)的製造步驟。
以下的詳細說明提供許多具體的細節，以使本發明能被透徹理解。然而，本領域之技術人士會理解其不需這些細節亦可得 以實施本發明。在其他例子中，已知的方法、步驟、元件與電路並未詳細描述，但不會使得本發明因而難以理解。應理解的是，下述的揭露提供許多不同的實施例或範例，其用於實現各種實施例的不同特徵。為簡化本文，元件與配置乃以特定範例描述如下。當然，這些僅作為範例而非用於限制本發明。
以下揭露提供許多不同的實施例或範例，用於實現本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本發明之揭示內容。當然，這些僅為範例，而非用於限制本發明。例如，以下關於在第二特徵上或上方形成第一特徵之描述可包含以該第一特徵與該第二特徵直接接觸之實施例；亦可包含在該第一特徵與第二特徵之間出現其他特徵的實施例，因而該第一特徵與該第二特徵並非直接接觸。此外，本揭露可在不同範例中重複相同的元件符號和/或字母。此重複作法係為達到簡化並清楚表達之目的，而非用於描述不同實施例和/或配置彼此之間的關係。
再者，本揭露可使用空間相對用語，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似用語，以簡化本文，且能描述圖式中一元件或特徵與另一元件或特徵的關係。空間相對用語除用於包括元件在圖式中描述的位向之外，還有使用或操作中之不同位向。舉例而言，若將圖式中的元件倒置，則描述成在其他零件「下」或「之下」的零件就會變成在其他零件「之上」。因此，例示的「在下」用詞亦可包含「在上」以及「在下」的位向。裝置亦可被轉向(旋轉90度或是其他位向)，並且本文所使用的空間相對用語也可以類似方式加以解釋。
關於本文實施例的製造與使用將在以下詳細討論。然而應理解的是，本發明提供許多可應用的發明概念，其可廣泛實施於不同的特定背景。本文所討論的特定實施例僅說明製造與使用本發明 的特定方法，並非限制本發明的範圍。
在半導體封裝的金屬凸塊技術中，金凸塊技術由於其材料性質與處理技術在該領域中廣為熟知，因而最為普及。然而，金凸塊本身材料成本高、接合可靠度較差以及其材料性質無法令人滿意，例如低導電性與低導熱性，皆為有待解決的問題。製造金屬凸塊有另一個節省成本的方法，是產生多層凸塊，例如一銅(Cu、在底層)、Ni(鎳、在中間層)以及金(Au、在頂層)結構的凸塊。此方法節省金屬凸塊的金料消耗，但是銅底層容易氧化與腐蝕，因而產生可靠度的問題。
相較於電子束氣相沉積技術，電鍍金-錫(Au-Sn)凸塊可提供較佳的組成成分均勻度。這是由於在沉積製程中，較輕的錫原子比起較重的金原子移動速度更快。因此，以電子束氣相沉積所形成的金-錫凸塊結構中，在接近沉積表面處形成了富含錫的相，而在較遠離沉積表面處形成富含金的相。金-錫凸塊由於其組成物不均勻，而導致可靠度不良，此一問題可藉由以下所探討的電鍍技術獲得解決。
圖1係為簡化的半導體封裝10的剖面圖，該半導體封裝10在下方傳導墊102與裝置103之間具有電鍍金-錫合金凸塊101。在一些實施例中，裝置103包含(但不限於)主動元件，例如記憶體、電晶體、二極體(PN或PIN接面)、積體電路或是可變電容。在其他實施例中，裝置103包含被動元件，例如電阻、電容或是電感。在一些實施例中，在裝置103上包含其上方的傳導墊105。圖1顯示一電鍍金-錫合金凸塊101的微結構。為清楚說明，在圖1右下角呈現電鍍金-錫合金凸塊101的放大剖面圖，並且藉由使用電子顯微鏡顯示電鍍金-錫合金凸塊101橫切面的微結構。在一些實施例中，電鍍金-錫合金凸塊101包含具有0.15至0.25重量百分比的錫(Sn)之成份，並且均勻分布在 下方的傳導墊102與裝置103之間。如圖1之放大圖所示，電鍍金-錫合金凸塊101包含明相(light phase)104與暗相(dark phase)107，其皆具有伸長形狀。在一些實施例中，平行於支撐電鍍金-錫合金凸塊101之表面的橫切面之最大尺寸係在約10微米至約50微米的範圍內。在一些實施例中，由於電鍍金-錫合金凸塊101係藉由電鍍而形成，因此明相104與暗相107為非晶(amorphous)結構而不是單晶(single crystals)結構。
參閱圖2A與圖2B，其分別說明平行於支撐電鍍金-錫合金凸塊101之表面的橫切面為圓形或矩形的最大尺寸。該剖面圖示係沿著圖1之剖面線AA的剖面。在一些實施例中，電鍍金-錫合金凸塊101的形狀係取決於裝置103上方的上傳導墊105之形狀。在一些實施例中，電鍍金-錫合金凸塊101的寬度係大於、等於或小於上傳導墊105之寬度。在一些實施例中，平行於支撐電鍍金-錫合金凸塊101之表面的電鍍金-錫合金凸塊101的圓形橫切面之尺寸係在約10微米(μm)至約50微米的範圍內，如圖2A中的W1所示。在一些實施例中，與支撐電鍍金-錫合金凸塊101平行的電鍍金-錫合金矩形橫切面的對角線係在約10微米至約50微米的範圍內，如圖2B中所標示之W2所示。
參閱圖3，其係根據一些實施例說明具有電鍍金-錫合金凸塊301的半導體結構300之剖面圖。在一些實施例中，半導體結構300係一半導體封裝體。半導體結構300包含下部3006。下部3006視其應用需求可包含(但不限於)一裝置或僅有一基板304，並且在基板的主動面304a上沉積下傳導墊302。上部3002包含一裝置303，該裝置303上具有被介電質307環繞的上傳導墊305。再者，上部3002進一步包含一層設置於上傳導墊305上的凸塊下金屬層(UBM)309、一部份的介電質307以及一設置於凸塊下金屬層(UBM)309上的傳導柱311。在一些實施例中，傳導柱311實質上為包含具有金、銅、銀及其合金的 金屬層。在一些實施例中，傳導柱311可由化學氣相沉積(CVD)、濺鍍或電化學電鍍(ECP)等方式形成。在一些實施例中，傳導柱311的高度H2，其範圍視應用需求可由從約10微米至約40微米。
在一些實施例中，UBM層309可為一單層結構或包含由不同材料形成多個次層之複合結構，該些次層結構可選自於鎳層、鈦層、鈦鎢層、鈀層、金層、銀層及其組合。上部3002還包含了一層在傳導柱311上的電鍍金-錫合金凸塊301。在一些實施例中，在傳導柱311與電鍍金-錫合金凸塊301之間形成介金屬化合物(intermetallic compound，IMC)319。在一些實施例中，介金屬化合物(IMC)的成分係取決於凸塊以及UBM層上方的傳導凸塊之材料以及其組成比例。例如，在一些實施例中，IMC包含二元的金/錫介金屬AuSn4或是AuSn/AuSn2的介金屬化合物層。
如圖3所示，電鍍金-錫合金凸塊301的高度H3係從電鍍金-錫合金凸塊體的頂部表面量到半導體晶片304的頂部表面為止。在一些實施例中，電鍍金-錫合金凸塊301或Au1-xSnx，其組成成分的x具有從約x=0.15至約x=0.25的重量百分比，具有H3的高度。在一些實施例中，以電鍍形成的金-錫合金凸塊301原始高度範圍係約從10微米至約40微米。在第一道迴銲程序之後，由於表面張力，金-錫合金凸塊301變軟且形成彎曲表面，其高度增加約為原始高度的10%，可達到約11微米至44微米。接著，當金-錫合金凸塊301接觸另一工件(workpiece，例如半導體裝置或基板)時，進行第二道迴銲程序，造成金-錫合金凸塊301的厚度縮減30%，而其厚度範圍變為從約7微米至約31微米。在一些實施例中，電鍍金-錫合金凸塊301的寬度(圖3的W3所示)可大於、等於或小於傳導柱311的寬度。在一些實施例中，與支撐電鍍金-錫合金凸塊的表面平行之電鍍金-錫合金凸塊301的圓形橫切面之直徑係在約20微米至約50微米範圍內，如圖2A之W1所示。在 一些實施例中，與支撐電鍍金-錫合金凸塊的表面平行之電鍍金-錫合金凸塊301的的矩形橫切面之對角線係在約20微米至約50微米的範圍內，如圖2B的W2所示。相較於傳統方法(例如氣相沉積技術)，電鍍金-錫合金凸塊具有非晶結構。由於非晶結構的內部應力較小，因而沉積程序後無需進行退火程序以降低電鍍金-錫合金凸塊的內部應力。
關於發光二極體(LED)結構的封裝技術，該技藝中具有通常知識者慣常使用金凸塊以連接LED結構至基板或裝置。然而，要接合基板(或裝置)上的銅線(作為導線)與LED結構，金凸塊的黏著性能較差，這在某種程度上是由於金凸塊的硬度相對較高所導致。為了解決黏著性問題，傳統方法係在銅線上形成錫膜，以使導線與金凸塊之間更容易黏著。而本文所提供的改良方法，係使用電鍍金-錫合金凸塊作為金屬凸塊與導線之間的介面。
參閱圖4，其係根據一些實施例說明具有電鍍金-錫合金凸塊401a與401b之發光二極體(LED)結構400的剖面圖。LED結構400包含基板403、N型GaN層405與P型GaN層409、在N型GaN層405與P型GaN層409之間的多量子井層(multiple quantum well layer)407、n型電極411a以及p型電極411b。在一些實施例中，基板可選自於藍寶石、玻璃、或任何合適的材料。在基板403的頂部，形成N型GaN層405。此外，多量子槽層407、P型GaN層409以及p型電極411b則接續沉積在部分N型GaN層405上方。另一方面，形成N型GaN層405的其他部分，以及n型電極411a。在一些實施例中，下部4006經由電鍍金-錫合金凸塊401a與401b而連接LED結構400。下部4006視其應用需求，可包含(但不限於)一裝置或僅具有主動面404A的基板404。下部4006還包含傳導墊402a與402b，其分別接合至電鍍金-錫合金凸塊401a與401b。在一些實施例中，下部4006可包含接合墊406a與406b以連接至 其他裝置。在一些實施例中，電鍍金-錫合金凸塊401a與401b的組成包含重量百分比0.15至0.25的錫，並且均勻分布在傳導墊402a與n型電極411a之間以及傳導墊402b與p型電極411b之間。在一些實施例中，兩個電鍍金-錫合金凸塊401a與401b的高度H4係在約3微米至約10微米範圍內，兩個電鍍金-錫合金凸塊401a與401b的寬度W4係在200至600微米範圍內，並且兩個電鍍金-錫合金凸塊401a與401b的長度(垂直紙面的方向)係在500至1500微米範圍內。在一些實施例中，電鍍金-錫合金凸塊401a與401b的寬度係等於或小於n型電極411a與p型電極411b的寬度。
在圖4的覆晶發光二極體(LED)結構400中，n型電極411a與p型電極411b係形成在LED結構400的同一側上。因此，包含n型電極411a與p型電極411b的LED結構400可直接堆疊於裝置或基板404上，如此一來，相較於習知的金屬打線接合技術，可達成較小的封裝面積。此外，LED結構400與傳導墊402a及402b之間係利用金-錫合金凸塊401a與401b形成連接，並不需要形成錫鍍層，就如前文所述。再者，在LED結構400中，電鍍金-錫合金凸塊401a與401b可單獨使用或是結合金(Au)或銀(Ag)凸塊使用，例如形成在金或銀凸塊上，其材料成本較低、並且熱穩定性較佳、對於溫度循環(thermal cycle)的耐受性更好並且接合效能明顯較佳。
覆晶薄膜封裝(chip-on film，COF)半導體結構在晶片與搭載該晶片之可撓性薄膜之間亦有黏著性不良的問題，與前述所提關於覆晶LED結構400的電極與基板上的導線接合不良的問題有類似狀況。因此本發明提供一種電鍍金-錫合金凸塊，其可作為晶片與可撓性薄膜之間的介面或連接物。
圖5係顯示具有電鍍金-錫合金凸塊的覆晶薄膜封裝(chip-on film，COF)半導體結構500。在一些實施例中，半導體結構 500為一半導體封裝體。COF半導體結構500包含一可撓性薄膜504，其可包含(但不限於)可撓印刷電路板(FPCB)或聚亞醯胺(PI)。該傳導層502a與502b(例如銅導線)經圖案化而設置於可撓性薄膜504之主動面504A上。在金凸塊或銀凸塊513a與513b上方的多個電鍍金-錫合金凸塊501a與501b經由上傳導墊511a與511b而將裝置503電性耦合至可撓性薄膜504的傳導層502a與502b。或者，可在上傳導墊511a與511b上方，沉積凸塊下金屬(UBM)層。在一些實施例中，底膠填充材料509，例如無溶劑環氧樹脂，以適當黏性注入至可撓性薄膜504與裝置503之間的空間中。在一些實施例中，阻焊圖案506a與506b係分別位於傳導層502a與502b上方，用以將底膠填充材料509限制於所需要的位置。在一些實施例中，底膠填充材料509可保護傳導層(502a與502b)以及可撓性薄膜504上方的電鍍金-錫合金凸塊(501a與501b)。還有要注意的的地方是在此實施例中，傳導層502a與502b的上方不需要錫鍍層用以連接電鍍金-錫合金凸塊(501a與501b)與可撓性薄膜504。
在一些實施例中，電鍍金-錫合金凸塊501a與501b的形狀係取決於裝置503上方的上傳導墊511a與511b的形狀。在一些實施例中，電鍍金-錫合金凸塊501a與501b的寬度等於或小於上傳導墊511a與511b的寬度。在一些實施例中，電鍍金-錫合金凸塊501a與501b的組成成分包含重量百分比0.15至0.25的錫，並且均勻分布在傳導層502a與上傳導墊511a之間以及傳導層502b與上傳導墊511b之間。在一些實施例中，特別是在液晶顯示器(LCD)應用中，對於矩形的金-錫合金凸塊501a與501b，其寬度為大約或小於30微米，並且其長度大約或小於17微米。在一些實施例中，需要在低結合溫度下將電鍍金-錫合金凸塊501a及501b分別連接至傳導層502a及502b。電鍍金-錫合金凸塊的共晶溫度約為攝氏280~300度。換言之，結合點(亦即金-錫合金凸塊與可撓基板的介面)溫度應控制在約攝氏280~300度。據此， 對於覆晶薄膜封裝(chip-on film，COF)的半導體結構而言，可撓基板並不會因為高溫而變形，而使裝置效具有良好的可靠度。
此外，電鍍金-錫合金凸塊可用於玻璃上晶片(COG)基板。傳統上，非等向傳導膜(ACF)係置於玻璃基板與半導體晶片上的金凸塊或銀凸塊之間。接著，在高溫下處理ACF，而使玻璃基板與半導體晶片係彼此電性連接。ACF通常係由具黏性的聚合物基質與用金屬粒或金屬塗覆聚合物球所組成的細微傳導填充物所組成。ACF的限制因素在於細微傳導填充物需達到一門檻濃度才能確保良好的電性連接。然而，由於主導導電特性的細微傳導填充物受到壓縮後的變形難以掌控，特別是發生在當積體電路的尺寸持續變小的情況，封裝結構的可靠度與接觸電阻可能因而受到影響。除了增加半導體封裝的製造成本之外，細微傳導填充物可能聚集在某些區域而非均勻分布，而使得ACF易於造成斷路(open circuit)。較小的元件尺寸可能造成細微傳導填充物在ACF中的流動性更低。在以下的段落中，採用電鍍金-錫合金凸塊連同COG結構的改良設計可用以解決前述問題。
在本揭露的一些實施例中，如圖6所示，將本文中所討論的電鍍金-錫合金凸塊601a與601b使用於COG半導體結構600中。具有主動面604A的玻璃基板604之傳導層602a與602b，以及半導體晶片603的金凸塊或銀凸塊613a與613b上方的電鍍金-錫合金凸塊601a與601b，其中間不需設置ACF就可完成電性連接的封裝。在一些實施例中，底膠填充材料609，例如無溶劑環氧樹脂，以適當的黏性注入玻璃基板604與半導體晶片603之間的空間，用以保護傳導層(602a與602b)、金-錫合金凸塊(601a與601b)以及金凸塊或銀凸塊613a與613b。在一些實施例中，底膠填充材料609由虛線所標明之處，為非強制的選項。值得注意的還有在本實施例中，傳導層602a與602b上方不需要錫膜用以連接電鍍金-錫合金凸塊(601a與601b)與玻璃基板604。
在一些實施例中，電鍍金-錫合金凸塊601a與601b的形狀係取決於半導體晶片603上方的上傳導墊611a與611b的形狀。在一些實施例中，電鍍金-錫合金凸塊601a與601b的寬度係等於或小於上傳導墊611a與611b的寬度。此外，電鍍金-錫合金凸塊601a與601b的尺寸可依不同應用需求而改變。相較於金凸塊或銀凸塊，金-錫合金凸塊以介面塗層或連接物的形式，能提供較佳的熱穩定性、更好的溫度循環耐受度以及更優良的接合效能。
圖7A至圖7F顯示圖3的電鍍金-錫合金凸塊之半導體結構的製造步驟。在圖7A中，上傳導墊305與部分的介電質307係位於裝置303上方。而後，在上傳導墊305與部分的介電質307上形成UBM層309。在一些實施例中，UBM層309係藉由將材料經由CVD程序、濺鍍、電鍍或無電鍍而形成，該材料係選自於鎳、鈦、鈦鎢、鈀、金、銀及其組合。在一些實施例中，將UBM層309的厚度T1控制在約1000Å至約3000Å的範圍內。在一些實施例中，在UBM層309上，沉積晶種層(因簡化而未繪示)。在一些實施例中，UBM層的最上層可作為晶種層。在一些實施例中，晶種層係藉由CVD、濺鍍、電鍍或無電鍍而形成。
參閱圖7B，在UBM層309上方，形成第一遮罩層313，其可為硬遮罩或是光阻。在上傳導墊305的上方形成第一遮罩層313的開口313A，用於接收導電性凸塊材料。在一些實施例中，第一遮罩層313係由正光阻製成，並且其厚度T2係大於所要鍍上的導電性凸塊之厚度。在其他實施例中，第一遮罩層313係由負光阻所製成。
參閱圖7C，在開口313A上方，可形成傳導柱311。傳導柱311的材料可包含純銅或是銅合金。在一些實施例中，傳導柱311可藉由化學氣相沉積(CVD)、濺鍍或電化學鍍(ECP)而形成。在一些實施例中，傳導柱311的高度H2視應用需求，在約10微米至約40微米的範圍內。
圖7D與圖7E顯示電鍍程序及其結果。圖7D顯示電鍍系統，其包含容納電鍍槽713的容器700’、陽極711以及陰極712。在一些實施例中，陽極711係不可溶且可由塗覆鈀(Pd)的鈦所製成，而裝置303(其具有的上傳導墊305受到介電質307環繞)係位於陰極712，且傳導柱311係形成於開口313A(見圖7C)中。電鍍槽713含有金-錫電解質電鍍溶液。在一些實施例中，將電鍍槽713的pH值控制於大約4至6。將電鍍槽713的溫度控制於約攝氏35至60度。在一些實施例中，可藉由位於容器700’下方的加熱板(未繪示)維持電鍍槽713的溫度。在其他實施例中，電鍍槽713的溫度可藉由電鍍溶液循環系統加以維持，其中出口700B排放電鍍溶液而入口700A引入溫控的電鍍溶液。在一些實施例中，用於電鍍金-錫合金凸塊的直流電(DC)之電流密度係在約0.2ASD(Amperes/Square Decimeter，安培/平方公寸)至約1.0ASD範圍內。在一些實施例中，將電鍍金-錫合金凸塊的速度控制在約0.2微米/分鐘(μm/min)至約0.4微米/分鐘的範圍內。要注意的是，電鍍金-錫合金凸塊的速度比蒸鍍金-錫合金凸塊的速度要快(通常用於金-錫凸塊的蒸鍍速度約為0.06微米/分鐘，而用於金-錫合金凸塊的電鍍沉積速度約為0.3微米/分鐘)。使用電鍍程序，可得到更高的生產量。在一些實施例中，外部DC電流的正端係連接至陽極711，而該外部DC電流的負端係連接至陰極712。如圖7D所示，還原的金離子與還原的錫離子填充由第一遮罩層313定義的開口313A，並且在傳導柱311的頂部形成金-錫二元合金。如圖7D所示，在傳導柱311上沉積金-錫合金之後，自電鍍槽移除裝置303。
圖7E顯示在圖7D所示之電鍍程序完成後的裝置303。在圖7E中，電鍍金-錫合金凸塊301形成在傳導柱311上方。在一些實施例中，電鍍金-錫合金凸塊301的高度係在約7微米至約31微米的範圍中。在一些實施例中，如果使用光阻，則去除第一遮罩層313，如圖7E所示。UBM層309未被電鍍金-錫合金凸塊301覆蓋的部分則藉由蝕刻程序加以去除，以將不同的電鍍金-錫合金凸塊301隔離。
圖7F顯示半導體結構300的完成結構，其電鍍金-錫合金凸塊301電性耦合至裝置或基板301(依應用需求而定)之主動面304A上的下傳導墊302。在一些實施例中，將下傳導墊302與對應的半導體結構300接合的步驟包含加熱半導體結構300，以使金-錫合金凸塊301與傳導墊302之間的介面溫度達到攝氏約280度至約320度。在一些實施例中，在電鍍程序之後且在接合程序之前，不進行退火程序。
圖8A至圖8D顯示製造具有圖4之電鍍金-錫合金凸塊之LED結構的步驟。在圖8A中，N型GaN層405形成於基板403上方。然後，多量子槽層407與P型GaN層409接續沉積在N型GaN層405上。為簡化說明，省略將多量子槽層407與P型GaN層409圖案化的細節。在一些實施例中，N型GaN層405、多量子槽層407以及P型GaN層409係藉由CVD、物理氣相沉積(PVD)或濺鍍方法形成。在一些實施例中，材料可為GaAs、GaN或任何合適的材料。復參閱圖8A，在P型GaN層409或N型GaN層405上方，形成第一遮罩層413，其可為硬遮罩或光阻。在P型GaN層409上方形成第一遮罩層413的開口413A，以及在N型GaN層405上方形成第一遮罩層413的開口413B，用於接收導電性凸塊材料。在一些實施例中，第一遮罩層413係由光阻製成，其厚度T8大於所欲鍍上之導電性凸塊的厚度。在其他實施例中，第一遮罩層413係由負光阻製成。如圖8B所示，在N型GaN層405或P型GaN層409上，分別沉積n型電極411a與p型電極411b。
圖8C與圖8D顯示電鍍程序及其結果。圖8C顯示電鍍系統，其包含容納電鍍槽813的容器800’、陽極811以及陰極812。在一些實施例中，陽極811係不可溶的，並且可由塗覆鈀的鈦所製成，而具有n型電極411a與p型電極411b的LED結構係位於陰極812。電鍍槽813含有金-錫電解質電鍍溶液。在一些實施例中，將電鍍槽813的pH值控制於弱酸的情況，例如大約4至6。電鍍槽813的溫度控制於約攝氏35至60度。在一些實施例中，電鍍槽813的溫度可藉由位於容器800’下方的加熱板(未繪示)維持。在其他實施例中，電鍍槽813的溫度 可藉由電鍍溶液循環系統維持，其中出口800B排放電鍍溶液而入口800A引入溫控的電鍍溶液。在一些實施例中，用於電鍍金-錫合金凸塊的直流電(DC)之電流密度係在約0.2ASD至約1.0ASD範圍內。在一些實施例中，將電鍍金-錫合金凸塊的速度控制在約0.2微米/分鐘至約0.4微米/分鐘的範圍內。在一些實施例中，外部DC電流的正端係連接至陽極811，而該外部DC電流的負端係連接至陰極812。如圖8C所示，還原的金離子與還原的錫離子係沉積在發光二極體400的n型電極411a與p型電極411b上、填充由第一遮罩層413定義的開口413A與413B(見圖8A)、並且在n型電極411a與p型電極411b頂部形成金-錫二元合金。在LED結構400之n型電極411a與p型電極411b上沉積金-錫合金之後，如圖8C所示，自電鍍槽移除發光結構400。
圖8D顯示圖8C所示之電鍍程序完成後的LED結構400。在圖8D中，電鍍金-錫合金凸塊401a與401b分別形成在n型電極411a與p型電極411b上方。在一些實施例中，如果使用光阻，則去除第一遮罩層413，如圖8D所示。未被電鍍金-錫合金凸塊401a與401b覆蓋的P型GaN層409或N型GaN層405則藉由蝕刻程序加以去除，以隔離電鍍金-錫合金凸塊401a與401b。再者，圖8D顯示LED結構400的完成結構，其具有電鍍金-錫凸塊401a與401b電性耦合至裝置或基板404(視應用需求不同而定)之主動面404a上的傳導墊402a與402b。在一些實施例中，將下傳導墊402a與402b與對應的LED結構400進行接合的步驟包含將具有電鍍金-錫合金凸塊的LED結構400加熱，使電鍍金-錫合金凸塊401a和401b與傳導墊402a和402b之間的介面溫度達到約攝氏280度至約320度。在一些實施例中，在電鍍程序之後且在接合程序之前，不進行退火程序。
在本揭露的一些實施例中，半導體封裝包含半導體晶片，其包含：具有傳導墊於其上的主動表面；在主動面上方的電鍍金-錫合金凸塊；以及基板，其包括與該電鍍金-錫合金凸塊電性耦合的導線。
在本揭露的一些實施例中，電鍍金-錫合金凸塊具有重量百分比約Au0.85Sn0.15至約Au0.75Sn0.25的組成成分，從接近主動面的一端均勻分布至接近基板的一端。
在本揭露的一些實施例中，傳導柱係位於電鍍金-錫合金凸塊與傳導墊之間。
在本揭露的一些實施例中，電鍍金-錫合金凸塊的高度係在約7微米至約31微米的範圍內。
在本揭露的一些實施例中，介金屬化合物係位於傳導柱與電鍍金-錫合金凸塊之間。
在本揭露的一些實施例中，傳導墊係電極，並且電鍍金-錫合金凸塊係位於電極與導線之間。
在本揭露的一些實施例中，半導體晶片係發光二極體(LED)。
在本揭露的一些實施例中，傳導墊係p型電極，另一傳導墊係n型電極，電鍍金-錫合金凸塊係位於p型電極與導線之間，並且另一電鍍金-錫凸塊係位於n型電極與導線之間。
在本揭露的一些實施例中，兩個金-錫合金凸塊的高度係在約3微米至約10微米的範圍內，兩個電鍍金-錫合金凸塊的寬度係在200至600微米的範圍內，以及兩個電鍍金-錫合金凸塊的長度係在500至1500微米的範圍內。
在本揭露的一些實施例中，半導體封裝係覆晶薄膜(chip-on film，COF)封裝。
在本揭露的一些實施例中，半導體封裝係玻璃上晶片(chip-on glass，COG)封裝。
在本揭露的一些實施例中，半導體封裝包含半導體晶片，其包含：具有傳導墊於其上的主動面；在主動面上方的電鍍金-錫合金凸塊；以及玻璃基板，其包括與電鍍金-錫合金凸塊電性耦合的導線。
在本揭露的一些實施例中，電鍍金-錫合金凸塊具有重量百分比約Au0.85Sn0.15至約Au0.75Sn0.25的組成成分，從接近主動面的一端均勻分布至接近玻璃基板的一端。
在本揭露的一些實施例中，傳導柱係位於電鍍金-錫合金凸塊與傳導墊之間。
在本揭露的一些實施例中，半導體晶片與玻璃基板之間沒有非等向性傳導膜(ACF)。
在本揭露的一些實施例中，一介金屬化合物係位於傳導柱與電鍍金-錫合金凸塊之間。
在本揭露的一些實施例中，各傳導柱係由選自於由金、銅、銀及其合金所組成的群組之材料所製成。
在本揭露的一些實施例中，製造半導體封裝的方法包含：在半導體晶片的主動面上形成傳導墊的圖案；電鍍傳導墊上方的金-錫合金凸塊；以及藉由迴銲程序或熱壓程序，將半導體晶片接合至基板上相對應的導線上。
在本揭露的一些實施例中，電鍍金-錫合金凸塊的方法包含：將半導體晶片浸入金-錫電鍍槽中；將流經金-錫電鍍槽的電流密度控制在約0.2ASD至約1.0ASD的範圍內；以及將金-錫電鍍槽的溫度保持在約攝氏30度至約攝氏60度的範圍內。
在本揭露的一些實施例中，將電鍍金-錫合金凸塊的速度控制在約0.2微米/分鐘至約0.4微米/分鐘的範圍內。
在本揭露的一些實施例中，將半導體晶片接合至對應的導線上的步驟包括將半導體晶片加熱，使得金-錫合金凸塊與導線之間的介面溫度達到約攝氏280度至約攝氏320度。
在本揭露的一些實施例中，在電鍍程序之後且在接合程序之前，不進行退火程序。
前述說明概述一些實施例，使得該技藝之技術人士更能理解本揭露之各方面。該技藝之技術人士應理解其可輕易使用本揭露作為設計或修飾其他製程與結構的基礎，以產生與本文所述之實施例相同之目的與/或達到相同的優點。該技藝之技術人士亦應理解此均等架構並不脫離本揭露之精神與範圍，並且其可進行各種改變、取代與更動而不脫離本揭露之精神與範圍。
再者，本申請案的範圍並不受限於說明書中所述之製程、機器、產品與物質之組成物、手段、方法與步驟的特定實施例。該技藝之技術人士從本揭露的揭示內容可理解根據本揭露可使用現存或未來所發展之製程、機器、產品、物質之組合、手段、方法或步驟而執行本文所述之對應實施例所示之實質相同功能或達到其實質相同結果。
據此，所附隨的申請專利範圍係用以包含例如製程、機器、製造、物質之組合、手段、方法或步驟之範圍。此外，每一申請專利範圍構成個別的實施例，並且不同申請專利範圍與實施例之組合係在本發明的範圍內。
10‧‧‧半導體封裝
101‧‧‧電鍍金-錫(Au-Sn)合金凸塊
102‧‧‧下傳導墊
103‧‧‧裝置
105‧‧‧上傳導墊
104‧‧‧明相
107‧‧‧暗相

Claims (10)

  1. 一種製造半導體封裝的方法，其包括：在半導體晶片的主動面上，形成傳導墊的圖案；在該傳導墊上方，電鍍金-錫合金凸塊；以及藉由迴銲程序或熱壓程序，將該半導體晶片接合在基板上對應的導線上，其中電鍍該金-錫合金凸塊之步驟包括：將該半導體晶片浸入金-錫電鍍槽中；將流經該金-錫電鍍槽的電流密度控制在約0.2ASD至約1.0ASD的範圍內；以及將該金-錫電鍍槽的溫度控制在約攝氏35度至約攝氏60度的範圍內。
  2. 如請求項1所述之方法，其中電鍍金-錫合金凸塊的速度係控制在約0.2微米/分鐘至約0.4微米/分鐘的範圍內。
  3. 如請求項1所述之方法，其中該半導體晶片接合在基板上對應的導線上的步驟包括加熱該半導體晶片，使得該金-錫合金凸塊與該導線之間的介面溫度達到約攝氏280度至約攝氏320度。
  4. 如請求項1所述之方法，其中在該電鍍程序之後且在該接合程序之前，不進行退火程序。
  5. 如請求項1所述之方法，其中該金-錫電鍍槽的pH值係控制在約4至6的範圍內。
  6. 如請求項1所述之方法，其中電鍍該金-錫合金凸塊之步驟還包含形成高度在約7微米至31微米範圍內的該金-錫合金凸塊。
  7. 如請求項1所述之方法，進一步包括形成介電質在該半導體晶片的該主動面上方，其中該介電質覆蓋該傳導墊的一部分。
  8. 如請求項7所述之方法，進一步包括形成凸塊下金屬(UBM)層於該介電質及該傳導墊上。
  9. 如請求項8所述之方法，進一步包括：選擇性地形成傳導柱連接該UBM層；以及形成該金-錫合金凸塊於該傳導柱上方。
  10. 如請求項8所述之方法，進一步包括在形成該金-錫合金凸塊後，去除該UBM層未被該金-錫合金凸塊覆蓋的部分，以將該金-錫合金凸塊與另一金-錫合金凸塊隔離。
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