CN106058024A - 一种半导体封装及其制造方法 - Google Patents

一种半导体封装及其制造方法 Download PDF

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Publication number
CN106058024A
CN106058024A CN201510598352.6A CN201510598352A CN106058024A CN 106058024 A CN106058024 A CN 106058024A CN 201510598352 A CN201510598352 A CN 201510598352A CN 106058024 A CN106058024 A CN 106058024A
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China
Prior art keywords
electrogilding
ashbury metal
metal projection
semiconductor packages
projection
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CN201510598352.6A
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Inventor
卢东宝
王恒生
徐子涵
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication of CN106058024A publication Critical patent/CN106058024A/zh
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    • C25D3/60—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of tin
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Abstract

本发明提供了一种半导体封装，其包括一半导体芯片，其中包含：一主动面，其上有传导垫；在主动面上方的电镀金-锡(Au-Sn)合金凸块；以及(玻璃)基板，其包括与电镀金-锡合金凸块电耦合的导线，其中电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近所述主动面的一端均匀分布至接近基板的一端。本发明还提供了一种制造半导体封装的方法，包括：在半导体芯片的主动面上形成传导垫的图案；在传导垫上方电镀金-锡合金凸块；以及藉由回焊程序或热压程序，将半导体芯片接合在基板上相对应的导线上。

Description

一种半导体封装及其制造方法
技术领域
本发明是关于金-锡(Au-Sn)合金凸块以及使用金-锡合金凸块的半导体结构。
背景技术
随着近来电子产业的进步，电子组件已经具有高性能的表现，因而产生微缩化、高密度化的封装需求。据此，连接IC与主板的连接端子必须以更高密度进行封装。封装技术的高密度发展是由于集成电路(IC)的输出入端(I/O)数目增加、而连接端子的接合方法亦变得更有效率所致。
覆晶接合技术是目前已普及的连结技术当中的一项。覆晶接合技术在现行的集成电路(IC)的制造趋势流程的发展，主要受到几个因素影响。第一，当使用传统金属丝连接技术，其相关的寄生电感降低时，半导体装置的电子性能可以再提升。其次，相较于金属丝连接技术，覆晶接合封装可在芯片与封装之间提供更高的互连密度。第三，覆晶接合技术所占用的硅芯片有效使用面积较少，因而有助于节省硅面积与降低组件成本。第四，当同步接合(gang-bonding)取代连续个别接合步骤时，可降低制造成本及电性接合时间。
为了能降低接合端子的尺寸与其间距，因此在覆晶接合技术中利用金属凸块取代早期连结用焊球，特别是藉由改良过的线球技术所产生的金属凸块。典型的作法乃是将该金属凸块形成在半导体芯片接垫的铝层上。接着，利用焊料将芯片附接至基板。该金属凸块可使用于LCD、内存、微处理器与射频集成电路(RFIC)的覆晶封装应用中。
在各种不同的接合材料中，由于环保意识的提升，无铅焊接凸块近年来倍受注目。目前还有其它不同形式的材料被采用并持续发展，例如纯锡(Sn)、金-锡(Au-Sn)、铜-锡(Cu-Sn)、银-锡(Ag-Sn)等。在本发明中，将进一步讨论电镀的金-锡(Au-Sn)凸块。
发明内容
本发明提供一种半导体封装，其包括半导体芯片。该半导体芯片包含一主动面及设置于主动面上之传导垫；电镀金-锡(Au-Sn)合金凸块，其位于该半导体芯片之主动面上；以及基板，其包括与该电镀金-锡合金凸块电性耦合的导线，其中该电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近该主动面的一端均匀分布至接近该基板的一端。
本发明提供一种半导体封装，其包括半导体芯片，该半导体芯片包含一主动面及设置于主动表面上的传导垫；电镀金-锡合金凸块，其位于该主动面上方；以及玻璃基板，其包含与该电镀金-锡合金凸块电性耦合的导线，其中该电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近该主动面的一端均匀分布至接近该玻璃基板的一端。
本发明的一些实施例是提供一种制造半导体封装的方法，其包括：在半导体芯片的一主动面上，形成传导垫的图案；在该传导垫上方，电镀金-锡合金凸块；以及藉由回焊程序或热压程序，将该半导体芯片接合在基板上相对应的导线上。
附图说明
经由以下所提供之详细说明与所附图式，将得以最佳方式了解本发明之各方面特征。值得注意的是，根据业界的标准做法，各种特征并非依比例绘示。实际上，为了清楚解释及说明，各种特征的尺寸可任意放大或缩小。
图1是根据本发明的一些实施例说明具有电镀金-锡(Au-Sn)合金凸块的简化半导体封装之剖面图。
图2A是根据本发明的一些实施例说明电镀金-锡合金凸块平行于支撑该电镀金-锡合金凸块的表面之剖面图。
图2B是根据本发明的一些实施例说明电镀金-锡合金凸块平行于支撑该电镀金-锡合金凸块的表面之剖面图。
图3是根据本发明的一些实施例说明具有电镀金-锡合金凸块的半导体结构之剖面图。
图4是根据本发明的一些实施例说明具有电镀金-锡合金凸块的发光二极管(LED)结构之剖面图。
图5是根据本发明的一些实施例说明具有电镀金-锡合金凸块之覆晶薄膜封装(chip-on film，COF)半导体结构之剖面图。
图6是根据本发明的一些实施例说明具有电镀金-锡合金凸块之玻璃覆晶结合技术(chip-on glass，COG)半导体结构之剖面图。
图7A至图7F是说明图3所示之具有电镀金-锡合金凸块之半导体结构的制造步骤。
图8A至图8D是说明图4所示之具有电镀金-锡合金凸块之发光二极管(LED)的制造步骤。
附图标记：
10 半导体封装
101 电镀金-锡(Au-Sn)合金凸块
102 下传导垫
103 装置
105 上传导垫
104 明相
107 暗相
300 半导体结构
301 金-锡(Au-Sn)合金凸块
3006 下部
304 基板
304a 主动表面
302 下传导垫
3002 上部
307 介电质
305 上传导垫
303 装置
309 凸块下金属(UBM)层
311 传导柱
400 发光二极管结构
401a、401b 电镀金-锡(Au-Sn)合金凸块
403 基板
405 N型GaN层
409 P型GaN层
407 多量子井层
411a n型电极
411b p型电极
4006 下部
404 基板
404A 主动表面
402a、402b 传导垫
406a、406b 接合垫
500 覆晶薄膜(COF)封装半导体结构
504 可挠性薄膜
504A 主动面
502a、502b 传导层
513a、513b 金/银凸块
501a、501b 电镀金-锡(Au-Sn)合金凸块
511a、511b 上传导垫
503 装置
506a、506b 阻焊图案
509 底胶填充材料
600 玻璃上芯片(COG)封装半导体结构
601a与、601b 电镀金-锡(Au-Sn)合金凸块
604 玻璃基板
604A 主动表面
602a、602b 传导层
603 半导体芯片
613a、613b 金/银凸块
611a、611b 上传导垫
313 第一屏蔽层
313A 开口
700’ 容器
713 电镀槽
711 阳极
712 阴极
700A 入口
700B 出口
413 第一屏蔽层
413A 开口
413B 开口
800’ 容器
811 阳极
812 阴极
813 电镀槽
800B 出口
800A 入口
具体实施方式
以下的详细说明提供许多具体的细节，以使本发明能被透彻理解。然而，本领域之技术人士会理解其不需这些细节亦可得以实施本发明。在其它例子中，已知的方法、步骤、组件与电路并未详细描述，但不会使得本发明因而难以理解。应理解的是，下述的发明提供许多不同的实施例或范例，其用于实现各种实施例的不同特征。为简化本文，组件与配置乃以特定范例描述如下。当然，这些仅作为范例而非用于限制本发明。
以下发明提供许多不同的实施例或范例，用于实现本申请案之不同特征。组件与配置的特定范例之描述如下，以简化本发明之揭示内容。当然，这些仅为范例，而非用于限制本发明。例如，以下关于在第二特征上或上方形成第一特征之描述可包含以该第一特征与该第二特征直接接触之实施例；亦可包含在该第一特征与第二特征之间出现其它特征的实施例，因而该第一特征与该第二特征并非直接接触。此外，本发明可在不同范例中重复相同的组件符号和/或字母。此重复作法是为达到简化并清楚表达之目的，而非用于描述不同实施例和/或配置彼此之间的关系。
再者，本发明可使用空间相对用语，例如「之下」、「低于」、「较低」、「高于」、「较高」等类似用语，以简化本文，且能描述图式中一组件或特征与另一组件或特征的关系。空间相对用语除用于包括组件在图式中描述的位向之外，还有使用或操作中之不同位向。举例而言，若将图式中的组件倒置，则描述成在其它零件「下」或「之下」的零件就会变成在其它零件「之上」。因此，例示的「在下」用词亦可包含「在上」以及「在下」的位向。装置亦可被转向(旋转90度或是其它位向)，并且本文所使用的空间相对用语也可以类似方式加以解释。
关于本文实施例的制造与使用将在以下详细讨论。然而应理解的是，本发明提供许多可应用的发明概念，其可广泛实施于不同的特定背景。本文所讨论的特定实施例仅说明制造与使用本发明的特定方法，并非限制本发明的范围。
在半导体封装的金属凸块技术中，金凸块技术由于其材料性质与处理技术在该领域中广为熟知，因而最为普及。然而，金凸块本身材料成本高、接合可靠度较差以及其材料性质无法令人满意，例如低导电性与低导热性，皆为有待解决的问题。制造金属凸块有另一个节省成本的方法，是产生多层凸块，例如一铜(Cu、在底层)、Ni(镍、在中间层)以及金(Au、在顶层)结构的凸块。此方法节省金属凸块的金料消耗，但是铜底层容易氧化与腐蚀，因而产生可靠度的问题。
相较于电子束气相沉积技术，电镀金-锡(Au-Sn)凸块可提供较佳的组成成分均匀度。这是由于在沉积制程中，较轻的锡原子比起较重的金原子移动速度更快。因此，以电子束气相沉积所形成的金-锡凸块结构中，在接近沉积表面处形成了富含锡的相，而在较远离沉积表面处形成富含金的相。金-锡凸块由于其组成物不均匀，而导致可靠度不良，此一问题可藉由以下所探讨的电镀技术获得解决。
图1是为简化的半导体封装10的剖面图，该半导体封装10在下方传导垫102与装置103之间具有电镀金-锡合金凸块101。在一些实施例中，装置103包含(但不限于)主动组件，例如内存、晶体管、二极管(PN或PIN接面)、集成电路或是可变电容。在其它实施例中，装置103包含被动组件，例如电阻、电容或是电感。在一些实施例中，在装置103上包含其上方的传导垫105。图1显示一电镀金-锡合金凸块101的微结构。为清楚说明，在图1右下角呈现电镀金-锡合金凸块101的放大剖面图，并且藉由使用电子显微镜显示电镀金-锡合金凸块101横切面的微结构。在一些实施例中，电镀金-锡合金凸块101包含具有0.15至0.25重量百分比的锡(Sn)之成份，并且均匀分布在下方的传导垫102与装置103之间。如图1之放大图所示，电镀金-锡合金凸块101包含明相(light phase)104与暗相(dark phase)107，其皆具有伸长形状。在一些实施例中，平行于支撑电镀金-锡合金凸块101之表面的横切面之最大尺寸是在约10微米至约50微米的范围内。在一些实施例中，由于电镀金-锡合金凸块101是藉由电镀而形成，因此明相104与暗相107为非晶(amorphous)结构而不是单晶(single crystals)结构。
参阅图2A与图2B，其分别说明平行于支撑电镀金-锡合金凸块101之表面的横切面为圆形或矩形的最大尺寸。该剖面图示是沿着图1之剖面线AA的剖面。在一些实施例中，电镀金-锡合金凸块101的形状是取决于装置103上方的上传导垫105之形状。在一些实施例中，电镀金-锡合金凸块101的宽度是大于、等于或小于上传导垫105之宽度。在一些实施例中，平行于支撑电镀金-锡合金凸块101之表面的电镀金-锡合金凸块101的圆形横切面之尺寸是在约10微米(μm)至约50微米的范围内，如图2A中的W1所示。在一些实施例中，与支撑电镀金-锡合金凸块101平行的电镀金-锡合金矩形横切面的对角线是在约10微米至约50微米的范围内，如图2B中所标示之W2所示。
参阅图3，其是根据一些实施例说明具有电镀金-锡合金凸块301的半导体结构300之剖面图。在一些实施例中，半导体结构300是一半导体封装体。半导体结构300包含下部3006。下部3006视其应用需求可包含(但不限于)一装置或仅有一基板304，并且在基板的主动面304a上沉积下传导垫302。上部3002包含一装置303，该装置303上具有被介电质307环绕的上传导垫305。再者，上部3002进一步包含一层设置于上传导垫305上的凸块下金属层(UBM)309、一部份的介电质307以及一设置于凸块下金属层(UBM)309上的传导柱311。在一些实施例中，传导柱311实质上为包含具有金、铜、银及其合金的金属层。在一些实施例中，传导柱311可由化学气相沉积(CVD)、溅镀或电化学电镀(ECP)等方式形成。在一些实施例中，传导柱311的高度H2，其范围视应用需求可由从约10微米至约40微米。
在一些实施例中，UBM层309可为一单层结构或包含由不同材料形成多个次层之复合结构，该些次层结构可选自于镍层、钛层、钛钨层、钯层、金层、银层及其组合。上部3002还包含了一层在传导柱311上的电镀金-锡合金凸块301。在一些实施例中，在传导柱311与电镀金-锡合金凸块301之间形成介金属化合物(intermetallic compound，IMC)319。在一些实施例中，介金属化合物(IMC)的成分是取决于凸块以及UBM层上方的传导凸块之材料以及其组成比例。例如，在一些实施例中，IMC包含二元的金/锡介金属AuSn4或是AuSn/AuSn2的介金属化合物层。
如图3所示，电镀金-锡合金凸块301的高度H3是从电镀金-锡合金凸块体的顶部表面量到半导体芯片304的顶部表面为止。在一些实施例中，电镀金-锡合金凸块301或Au1-xSnx，其组成成分的x具有从约x＝0.15至约x＝0.25的重量百分比，具有H3的高度。在一些实施例中，以电镀形成的金-锡合金凸块301原始高度范围是约从10微米至约40微米。在第一道回焊程序之后，由于表面张力，金-锡合金凸块301变软且形成弯曲表面，其高度增加约为原始高度的10％，可达到约11微米至44微米。接着，当金-锡合金凸块301接触另一工件(workpiece，例如半导体装置或基板)时，进行第二道回焊程序，造成金-锡合金凸块301的厚度缩减30％，而其厚度范围变为从约7微米至约31微米。在一些实施例中，电镀金-锡合金凸块301的宽度(图3的W3所示)可大于、等于或小于传导柱311的宽度。在一些实施例中，与支撑电镀金-锡合金凸块的表面平行之电镀金-锡合金凸块301的圆形横切面之直径是在约20微米至约50微米范围内，如图2A之W1所示。在一些实施例中，与支撑电镀金-锡合金凸块的表面平行之电镀金-锡合金凸块301的的矩形横切面之对角线是在约20微米至约50微米的范围内，如图2B的W2所示。相较于传统方法(例如气相沉积技术)，电镀金-锡合金凸块具有非晶结构。由于非晶结构的内部应力较小，因而沉积程序后无需进行退火程序以降低电镀金-锡合金凸块的内部应力。
关于发光二极管(LED)结构的封装技术，该技艺中具有通常知识者惯常使用金凸块以连接LED结构至基板或装置。然而，要接合基板(或装置)上的铜线(作为导线)与LED结构，金凸块的黏着性能较差，这在某种程度上是由于金凸块的硬度相对较高所导致。为了解决黏着性问题，传统方法是在铜线上形成锡膜，以使导线与金凸块之间更容易黏着。而本文所提供的改良方法，是使用电镀金-锡合金凸块作为金属凸块与导线之间的接口。
参阅图4，其是根据一些实施例说明具有电镀金-锡合金凸块401a与401b之发光二极管(LED)结构400的剖面图。LED结构400包含基板403、N型GaN层405与P型GaN层409、在N型GaN层405与P型GaN层409之间的多量子井层(multiple quantum well layer)407、n型电极411a以及p型电极411b。在一些实施例中，基板可选自于蓝宝石、玻璃、或任何合适的材料。在基板403的顶部，形成N型GaN层405。此外，多量子槽层407、P型GaN层409以及p型电极411b则接续沉积在部分N型GaN层405上方。另一方面，形成N型GaN层405的其它部分，以及n型电极411a。在一些实施例中，下部4006经由电镀金-锡合金凸块401a与401b而连接LED结构400。下部4006视其应用需求，可包含(但不限于)一装置或仅具有主动面404A的基板404。下部4006还包含传导垫402a与402b，其分别接合至电镀金-锡合金凸块401a与401b。在一些实施例中，下部4006可包含接合垫406a与406b以连接至其它装置。在一些实施例中，电镀金-锡合金凸块401a与401b的组成包含重量百分比0.15至0.25的锡，并且均匀分布在传导垫402a与n型电极411a之间以及传导垫402b与p型电极411b之间。在一些实施例中，两个电镀金-锡合金凸块401a与401b的高度H4是在约3微米至约10微米范围内，两个电镀金-锡合金凸块401a与401b的宽度W4是在200至600微米范围内，并且两个电镀金-锡合金凸块401a与401b的长度(垂直纸面的方向)是在500至1500微米范围内。在一些实施例中，电镀金-锡合金凸块401a与401b的宽度是等于或小于n型电极411a与p型电极411b的宽度。
在图4的覆晶发光二极管(LED)结构400中，n型电极411a与p型电极411b是形成在LED结构400的同一侧上。因此，包含n型电极411a与p型电极411b的LED结构400可直接堆栈于装置或基板404上，如此一来，相较于习知的金属丝连接技术，可达成较小的封装面积。此外，LED结构400与传导垫402a及402b之间是利用金-锡合金凸块401a与401b形成连接，并不需要形成锡镀层，就如前文所述。再者，在LED结构400中，电镀金-锡合金凸块401a与401b可单独使用或是结合金(Au)或银(Ag)凸块使用，例如形成在金或银凸块上，其材料成本较低、并且热稳定性较佳、对于温度循环(thermal cycle)的耐受性更好并且接合效能明显较佳。
覆晶薄膜封装(chip-on film，COF)半导体结构在芯片与搭载该芯片之可挠性薄膜之间亦有黏着性不良的问题，与前述所提关于覆晶LED结构400的电极与基板上的导线接合不良的问题有类似状况。因此本发明提供一种电镀金-锡合金凸块，其可作为芯片与可挠性薄膜之间的接口或连接物。
图5是显示具有电镀金-锡合金凸块的覆晶薄膜封装(chip-on film，COF)半导体结构500。在一些实施例中，半导体结构500为一半导体封装体。COF半导体结构500包含一可挠性薄膜504，其可包含(但不限于)可挠印刷电路板(FPCB)或聚亚酰胺(PI)。该传导层502a与502b(例如铜导线)经图案化而设置于可挠性薄膜504之主动面504A上。在金凸块或银凸块513a与513b上方的多个电镀金-锡合金凸块501a与501b经由上传导垫511a与511b而将装置503电性耦合至可挠性薄膜504的传导层502a与502b。或者，可在上传导垫511a与511b上方，沉积凸块下金属(UBM)层。在一些实施例中，底胶填充材料509，例如无溶剂环氧树脂，以适当黏性注入至可挠性薄膜504与装置503之间的空间中。在一些实施例中，阻焊图案506a与506b是分别位于传导层502a与502b上方，用以将底胶填充材料509限制于所需要的位置。在一些实施例中，底胶填充材料509可保护传导层(502a与502b)以及可挠性薄膜504上方的电镀金-锡合金凸块(501a与501b)。还有要注意的的地方是在此实施例中，传导层502a与502b的上方不需要锡镀层用以连接电镀金-锡合金凸块(501a与501b)与可挠性薄膜504。
在一些实施例中，电镀金-锡合金凸块501a与501b的形状是取决于装置503上方的上传导垫511a与511b的形状。在一些实施例中，电镀金-锡合金凸块501a与501b的宽度等于或小于上传导垫511a与511b的宽度。在一些实施例中，电镀金-锡合金凸块501a与501b的组成成分包含重量百分比0.15至0.25的锡，并且均匀分布在传导层502a与上传导垫511a之间以及传导层502b与上传导垫511b之间。在一些实施例中，特别是在液晶显示器(LCD)应用中，对于矩形的金-锡合金凸块501a与501b，其宽度为大约或小于30微米，并且其长度大约或小于17微米。在一些实施例中，需要在低结合温度下将电镀金-锡合金凸块501a及501b分别连接至传导层502a及502b。电镀金-锡合金凸块的共晶温度约为摄氏280～300度。换言之，结合点(亦即金-锡合金凸块与可挠基板的接口)温度应控制在约摄氏280～300度。据此，对于覆晶薄膜封装(chip-on film，COF)的半导体结构而言，可挠基板并不会因为高温而变形，而使装置具有良好的可靠度。
此外，电镀金-锡合金凸块可用于玻璃上芯片(COG)基板。传统上，非等向传导膜(ACF)是置于玻璃基板与半导体芯片上的金凸块或银凸块之间。接着，在高温下处理ACF，而使玻璃基板与半导体芯片是彼此电性连接。ACF通常是由具黏性的聚合物基质与用金属粒或金属涂覆聚合物球所组成的细微传导填充物所组成。ACF的限制因素在于细微传导填充物需达到一门坎浓度才能确保良好的电性连接。然而，由于主导导电特性的细微传导填充物受到压缩后的变形难以掌控，特别是发生在当集成电路的尺寸持续变小的情况，封装结构的可靠度与接触电阻可能因而受到影响。除了增加半导体封装的制造成本之外，细微传导填充物可能聚集在某些区域而非均匀分布，而使得ACF易于造成断路(open circuit)。较小的组件尺寸可能造成细微传导填充物在ACF中的流动性更低。在以下的段落中，采用电镀金-锡合金凸块连同COG结构的改良设计可用以解决前述问题。
在本发明的一些实施例中，如图6所示，将本文中所讨论的电镀金-锡合金凸块601a与601b使用于COG半导体结构600中。具有主动面604A的玻璃基板604之传导层602a与602b，以及半导体芯片603的金凸块或银凸块613a与613b上方的电镀金-锡合金凸块601a与601b，其中间不需设置ACF就可完成电性连接的封装。在一些实施例中，底胶填充材料609，例如无溶剂环氧树脂，以适当的黏性注入玻璃基板604与半导体芯片603之间的空间，用以保护传导层(602a与602b)、金-锡合金凸块(601a与601b)以及金凸块或银凸块613a与613b。在一些实施例中，底胶填充材料609由虚线所标明之处，为非强制的选项。值得注意的还有在本实施例中，传导层602a与602b上方不需要锡膜用以连接电镀金-锡合金凸块(601a与601b)与玻璃基板604。
在一些实施例中，电镀金-锡合金凸块601a与601b的形状是取决于半导体芯片603上方的上传导垫611a与611b的形状。在一些实施例中，电镀金-锡合金凸块601a与601b的宽度是等于或小于上传导垫611a与611b的宽度。此外，电镀金-锡合金凸块601a与601b的尺寸可依不同应用需求而改变。相较于金凸块或银凸块，金-锡合金凸块以接口涂层或连接物的形式，能提供较佳的热稳定性、更好的温度循环耐受度以及更优良的接合效能。
图7A至图7F显示图3的电镀金-锡合金凸块之半导体结构的制造步骤。在图7A中，上传导垫305与部分的介电质307是位于装置303上方。而后，在上传导垫305与部分的介电质307上形成UBM层309。在一些实施例中，UBM层309是藉由将材料经由CVD程序、溅镀、电镀或无电镀而形成，该材料是选自于镍、钛、钛钨、钯、金、银及其组合。在一些实施例中，将UBM层309的厚度T1控制在约至约的范围内。在一些实施例中，在UBM层309上，沉积晶种层(因简化而未绘示)。在一些实施例中，UBM层的最上层可作为晶种层。在一些实施例中，晶种层是藉由CVD、溅镀、电镀或无电镀而形成。
参阅图7B，在UBM层309上方，形成第一屏蔽层313，其可为硬屏蔽或是光阻。在上传导垫305的上方形成第一屏蔽层313的开口313A，用于接收导电性凸块材料。在一些实施例中，第一屏蔽层313是由正光阻制成，并且其厚度T2是大于所要镀上的导电性凸块之厚度。在其它实施例中，第一屏蔽层313是由负光阻所制成。
参阅图7C，在开口313A上方，可形成传导柱311。传导柱311的材料可包含纯铜或是铜合金。在一些实施例中，传导柱311可藉由化学气相沉积(CVD)、溅镀或电化学镀(ECP)而形成。在一些实施例中，传导柱311的高度H2视应用需求，在约10微米至约40微米的范围内。
图7D与图7E显示电镀程序及其结果。图7D显示电镀系统，其包含容纳电镀槽713的容器700’、阳极711以及阴极712。在一些实施例中，阳极711是不可溶且可由涂覆钯(Pd)的钛所制成，而装置303(其具有的上传导垫305受到介电质307环绕)是位于阴极712，且传导柱311是形成于开口313A(见图7C)中。电镀槽713含有金-锡电解质电镀溶液。在一些实施例中，将电镀槽713的pH值控制于大约4至6。将电镀槽713的温度控制于约摄氏35至60度。在一些实施例中，可藉由位于容器700’下方的加热板(未绘示)维持电镀槽713的温度。在其它实施例中，电镀槽713的温度可藉由电镀溶液循环系统加以维持，其中出口700B排放电镀溶液而入口700A引入温控的电镀溶液。在一些实施例中，用于电镀金-锡合金凸块的直流电(DC)之电流密度是在约0.2ASD(Amperes/Square Decimeter，安培/平方公寸)至约1.0ASD范围内。在一些实施例中，将电镀金-锡合金凸块的速度控制在约0.2微米/分钟(μm/min)至约0.4微米/分钟的范围内。要注意的是，电镀金-锡合金凸块的速度比蒸镀金-锡合金凸块的速度要快(通常用于金-锡凸块的蒸镀速度约为0.06微米/分钟，而用于金-锡合金凸块的电镀沉积速度约为0.3微米/分钟)。使用电镀程序，可得到更高的生产量。在一些实施例中，外部DC电流的正端是连接至阳极711，而该外部DC电流的负端是连接至阴极712。如图7D所示，还原的金离子与还原的锡离子填充由第一屏蔽层313定义的开口313A，并且在传导柱311的顶部形成金-锡二元合金。如图7D所示，在传导柱311上沉积金-锡合金之后，自电镀槽移除装置303。
图7E显示在图7D所示之电镀程序完成后的装置303。在图7E中，电镀金-锡合金凸块301形成在传导柱311上方。在一些实施例中，电镀金-锡合金凸块301的高度是在约7微米至约31微米的范围中。在一些实施例中，如果使用光阻，则去除第一屏蔽层313，如图7E所示。UBM层309未被电镀金-锡合金凸块301覆盖的部分则藉由蚀刻程序加以去除，以将不同的电镀金-锡合金凸块301隔离。
图7F显示半导体结构300的完成结构，其电镀金-锡合金凸块301电性耦合至装置或基板304(依应用需求而定)之主动面304A上的下传导垫302。在一些实施例中，将下传导垫302与对应的半导体结构300接合的步骤包含加热半导体结构300，以使金-锡合金凸块301与传导垫302之间的接口温度达到摄氏约280度至约320度。在一些实施例中，在电镀程序之后且在接合程序之前，不进行退火程序。
图8A至图8D显示制造具有图4之电镀金-锡合金凸块之LED结构的步骤。在图8A中，N型GaN层405形成于基板403上方。然后，多量子槽层407与P型GaN层409接续沉积在N型GaN层405上。为简化说明，省略将多量子槽层407与P型GaN层409图案化的细节。在一些实施例中，N型GaN层405、多量子槽层407以及P型GaN层409是藉由CVD、物理气相沉积(PVD)或溅镀方法形成。在一些实施例中，材料可为GaAs、GaN或任何合适的材料。复参阅图8A，在P型GaN层409或N型GaN层405上方，形成第一屏蔽层413，其可为硬屏蔽或光阻。在P型GaN层409上方形成第一屏蔽层413的开口413A，以及在N型GaN层405上方形成第一屏蔽层413的开口413B，用于接收导电性凸块材料。在一些实施例中，第一屏蔽层413是由光阻制成，其厚度T8大于所欲镀上之导电性凸块的厚度。在其它实施例中，第一屏蔽层413是由负光阻制成。如图8B所示，在N型GaN层405或P型GaN层409上，分别沉积n型电极411a与p型电极411b。
图8C与图8D显示电镀程序及其结果。图8C显示电镀系统，其包含容纳电镀槽813的容器800’、阳极811以及阴极812。在一些实施例中，阳极811是不可溶的，并且可由涂覆钯的钛所制成，而具有n型电极411a与p型电极411b的LED结构是位于阴极812。电镀槽813含有金-锡电解质电镀溶液。在一些实施例中，将电镀槽813的pH值控制于弱酸的情况，例如大约4至6。电镀槽813的温度控制于约摄氏35至60度。在一些实施例中，电镀槽813的温度可藉由位于容器800’下方的加热板(未绘示)维持。在其它实施例中，电镀槽813的温度可藉由电镀溶液循环系统维持，其中出口800B排放电镀溶液而入口800A引入温控的电镀溶液。在一些实施例中，用于电镀金-锡合金凸块的直流电(DC)之电流密度是在约0.2ASD至约1.0ASD范围内。在一些实施例中，将电镀金-锡合金凸块的速度控制在约0.2微米/分钟至约0.4微米/分钟的范围内。在一些实施例中，外部DC电流的正端是连接至阳极811，而该外部DC电流的负端是连接至阴极812。如图8C所示，还原的金离子与还原的锡离子是沉积在发光二极管400的n型电极411a与p型电极411b上、填充由第一屏蔽层413定义的开口413A与413B(见图8A)、并且在n型电极411a与p型电极411b顶部形成金-锡二元合金。在LED结构400之n型电极411a与p型电极411b上沉积金-锡合金之后，如图8C所示，自电镀槽移除发光结构400。
图8D显示图8C所示之电镀程序完成后的LED结构400。在图8D中，电镀金-锡合金凸块401a与401b分别形成在n型电极411a与p型电极411b上方。在一些实施例中，如果使用光阻，则去除第一屏蔽层413，如图8D所示。未被电镀金-锡合金凸块401a与401b覆盖的P型GaN层409或N型GaN层405则藉由蚀刻程序加以去除，以隔离电镀金-锡合金凸块401a与401b。再者，图8D显示LED结构400的完成结构，其具有电镀金-锡凸块401a与401b电性耦合至装置或基板404(视应用需求不同而定)之主动面404a上的传导垫402a与402b。在一些实施例中，将下传导垫402a与402b与对应的LED结构400进行接合的步骤包含将具有电镀金-锡合金凸块的LED结构400加热，使电镀金-锡合金凸块401a和401b与传导垫402a和402b之间的接口温度达到约摄氏280度至约320度。在一些实施例中，在电镀程序之后且在接合程序之前，不进行退火程序。
在本发明的一些实施例中，半导体封装包含半导体芯片，其包含：具有传导垫于其上的主动表面；在主动面上方的电镀金-锡合金凸块；以及基板，其包括与该电镀金-锡合金凸块电性耦合的导线。
在本发明的一些实施例中，电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近主动面的一端均匀分布至接近基板的一端。
在本发明的一些实施例中，传导柱是位于电镀金-锡合金凸块与传导垫之间。
在本发明的一些实施例中，电镀金-锡合金凸块的高度是在约7微米至约31微米的范围内。
在本发明的一些实施例中，介金属化合物是位于传导柱与电镀金-锡合金凸块之间。
在本发明的一些实施例中，传导垫是电极，并且电镀金-锡合金凸块是位于电极与导线之间。
在本发明的一些实施例中，半导体芯片是发光二极管(LED)。
在本发明的一些实施例中，传导垫是p型电极，另一传导垫是n型电极，电镀金-锡合金凸块是位于p型电极与导线之间，并且另一电镀金-锡凸块是位于n型电极与导线之间。
在本发明的一些实施例中，两个金-锡合金凸块的高度是在约3微米至约10微米的范围内，两个电镀金-锡合金凸块的宽度是在200至600微米的范围内，以及两个电镀金-锡合金凸块的长度是在500至1500微米的范围内。
在本发明的一些实施例中，半导体封装是覆晶薄膜(chip-on film，COF)封装。
在本发明的一些实施例中，半导体封装是玻璃上芯片(chip-on glass，COG)封装。
在本发明的一些实施例中，半导体封装包含半导体芯片，其包含：具有传导垫于其上的主动面；在主动面上方的电镀金-锡合金凸块；以及玻璃基板，其包括与电镀金-锡合金凸块电性耦合的导线。
在本发明的一些实施例中，电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近主动面的一端均匀分布至接近玻璃基板的一端。
在本发明的一些实施例中，传导柱是位于电镀金-锡合金凸块与传导垫之间。
在本发明的一些实施例中，半导体芯片与玻璃基板之间不需使用非等向性传导膜(ACF)。
在本发明的一些实施例中，一介金属化合物是位于传导柱与电镀金-锡合金凸块之间。
在本发明的一些实施例中，各传导柱是由选自于由金、铜、银及其合金所组成的群组之材料所制成。
在本发明的一些实施例中，制造半导体封装的方法包含：在半导体芯片的主动面上形成传导垫的图案；电镀传导垫上方的金-锡合金凸块；以及藉由回焊程序或热压程序，将半导体芯片接合至基板上相对应的导线上。
在本发明的一些实施例中，电镀金-锡合金凸块的方法包含：将半导体芯片浸入金-锡电镀槽中；将流经金-锡电镀槽的电流密度控制在约0.2ASD至约1.0ASD的范围内；以及将金-锡电镀槽的温度保持在约摄氏30度至约摄氏60度的范围内。
在本发明的一些实施例中，将电镀金-锡合金凸块的速度控制在约0.2微米/分钟至约0.4微米/分钟的范围内。
在本发明的一些实施例中，将半导体芯片接合至对应的导线上的步骤包括将半导体芯片加热，使得金-锡合金凸块与导线之间的接口温度达到约摄氏280度至约摄氏320度。
在本发明的一些实施例中，在电镀程序之后且在接合程序之前，不进行退火程序。
前述说明概述一些实施例，使得该技艺之技术人士更能理解本发明之各方面。该技艺之技术人士应理解其可轻易使用本发明作为设计或修饰其它制程与结构的基础，以产生与本文所述之实施例相同之目的与/或达到相同的优点。该技艺之技术人士亦应理解此均等架构并不脱离本发明之精神与范围，并且其可进行各种改变、取代与更动而不脱离本发明之精神与范围。
再者，本申请案的范围并不受限于说明书中所述之制程、机器、产品与物质之组成物、手段、方法与步骤的特定实施例。该技艺之技术人士从本发明的揭示内容可理解根据本发明可使用现存或未来所发展之制程、机器、产品、物质之组合、手段、方法或步骤而执行本文所述之对应实施例所示之实质相同功能或达到其实质相同结果。
据此所附随的申请专利范围是用以包含例如制程、机器、制造、物质之组合、手段、方法或步骤之范围。此外，每一申请专利范围构成个别的实施例，并且不同申请专利范围与实施例之组合是在本发明的范围内。

Claims (20)

1.一种半导体封装，其包括：
半导体芯片，其包含具有传导垫于其上的主动面；
电镀金-锡(Au-Sn)合金凸块，其位于所述主动面上方；以及
基板，其包括与所述电镀金-锡合金凸块电性耦合的导线，
其中所述电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近所述主动面的一端均匀分布至接近所述基板的一端。
2.如权利要求1所述的半导体封装，还包括位于所述电镀金-锡合金凸块与所述传导垫之间的传导柱。
3.如权利要求1所述的半导体封装，其中所述电镀金-锡合金凸块的高度是在约7微米至约31微米的范围内。
4.如权利要求1所述的半导体封装，其中一介金属化合物位于所述传导柱与所述电镀金-锡合金凸块之间。
5.如权利要求1所述的半导体封装，其中所述传导垫是电极，并且所述电镀金-锡合金凸块是位于所述电极与所述导线之间。
6.如权利要求1所述的半导体封装，其中所述半导体芯片是发光二极管。
7.如权利要求6所述的半导体封装，其中所述传导垫是p型电极，另一传导垫是n型电极，所述电镀金-锡合金凸块是位于所述p型电极与所述导线之间，并且另一电镀金-锡凸块是在所述n型电极与所述导线之间。
8.如权利要求7所述的半导体封装，其中所述两个电镀金-锡合金凸块的高度是在约3微米至约10微米的范围内，所述两个电镀金-锡合金凸块的宽度是在200至600微米的范围内，以及所述两个电镀金-锡合金凸块的长度是在500至1500微米的范围内。
9.如权利要求1所述的半导体封装，其中所述半导体封装是覆晶薄膜封装。
10.如权利要求1所述的半导体封装，其中所述半导体封装是玻璃上芯片封装。
11.一种半导体封装，其包括：
半导体芯片，其包含具有传导垫于其上的主动面；
电镀金-锡合金凸块，其位于所述主动面上方；以及
玻璃基板，其包含与所述电镀金-锡合金凸块电性耦合的导线，
其中所述电镀金-锡合金凸块具有重量百分比约Au0.85Sn0.15至约Au0.75Sn0.25的组成成分，从接近所述主动面的一端均匀分布至接近所述玻璃基板的一端。
12.如权利要求11所述的半导体封装，还包括位于所述电镀金-锡合金凸块与所述传导垫之间的传导柱。
13.如权利要求11所述的半导体封装，其中所述半导体芯片与所述玻璃基板之间没有非等向性传导膜(ACF)。
14.如权利要求11所述的半导体封装，其中一介金属化合物是位于所述传导柱与所述电镀金-锡合金凸块之间。
15.如权利要求12所述的半导体封装，其中各个所述传导柱是由选自于金、铜、银及其合金所组成的群组之材料所制成。
16.一种制造半导体封装的方法，其包括：
在半导体芯片的主动面上，形成传导垫的图案；
在所述传导垫上方，电镀金-锡合金凸块；以及
藉由回焊程序或热压程序，将所述半导体芯片接合在基板上对应的导线上。
17.如权利要求16所述的制造半导体封装的方法，其中电镀如权利要求1所述金-锡合金凸块的步骤包括：
将所述半导体芯片浸入金-锡电镀槽中；
将流经所述金-锡电镀槽的电流密度控制在约0.2ASD至约1.0ASD的范围内；以及
将所述金-锡电镀槽的温度控制在约摄氏35度至约摄氏60度的范围内。
18.如权利要求16所述的制造半导体封装的方法，其中电镀金-锡合金凸块的速度是控制在约0.2微米/分钟至约0.4微米/分钟的范围内。
19.如权利要求16所述的制造半导体封装的方法，其中所述半导体芯片接合在基板上对应的导线上的步骤包括加热所述半导体芯片，使得所述金-锡合金凸块与所述导线之间的接口温度达到约摄氏280度至约摄氏320度。
20.如权利要求16所述的制造半导体封装的方法，其中在所述电镀程序之后且在所述接合程序之前，不进行退火程序。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109663998A (zh) * 2018-11-29 2019-04-23 贵州振华风光半导体有限公司 一种功率半导体芯片钎焊溢料控制方法
CN111433907A (zh) * 2017-11-17 2020-07-17 美光科技公司 具有多层囊封剂的半导体装置及相关联系统、装置与方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069606B2 (en) * 2016-10-06 2021-07-20 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
CN109424864B (zh) * 2017-08-31 2021-04-30 京东方科技集团股份有限公司 光源结构、电子装置及光源结构制作方法
CN110592634B (zh) * 2019-10-22 2020-10-02 常州顺烨电子有限公司 一种半导体二极管电镀处理系统
US11505867B1 (en) * 2021-06-14 2022-11-22 Consolidated Nuclear Security, LLC Methods and systems for electroless plating a first metal onto a second metal in a molten salt bath, and surface pretreatments therefore
CN114481100B (zh) * 2022-04-01 2022-07-19 绍兴中芯集成电路制造股份有限公司 化学镀不同厚度的金属的方法、器件的封装方法
TWI838903B (zh) * 2022-10-07 2024-04-11 國立陽明交通大學 三族氮化物半導體三維積體電路
CN116564916A (zh) * 2023-03-31 2023-08-08 江苏纳沛斯半导体有限公司 一种驱动ic的凸块封装结构及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1600495A (zh) * 2004-10-27 2005-03-30 新磊微制造股份有限公司 导体接合方法及应用其中的锡金焊料结构
CN1603054A (zh) * 2003-10-01 2005-04-06 三星电子株式会社 锡银金焊料凸点、其制造方法及用其焊接发光装置的方法
CN101075650A (zh) * 2006-05-18 2007-11-21 洲磊科技股份有限公司 适用于覆晶封装的发光二极管结构及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6115992A (ja) * 1984-06-29 1986-01-24 Sumitomo Metal Mining Co Ltd 金−錫合金メツキ浴及びメツキ方法
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
USH1934H1 (en) * 1992-05-01 2001-01-02 Lucent Technologies, Inc. Gold-tin solder suitable for self-aligning applications
US5951893A (en) * 1995-12-05 1999-09-14 Motorola, Inc. Integrated circuit pad structure with high temperature heating element and method therefor
JP3239231B2 (ja) * 1996-04-11 2001-12-17 日本特殊陶業株式会社 パッドを備えるセラミック基板、端子部材を備えるセラミック基板およびそれらの製造方法
JP2001192886A (ja) * 2000-01-06 2001-07-17 Ne Chemcat Corp 金−錫合金電気めっき浴
JP2002289768A (ja) * 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
JP3723453B2 (ja) * 2000-09-12 2005-12-07 ローム株式会社 半導体装置
US7247514B2 (en) * 2003-04-11 2007-07-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing the same
TWI237370B (en) * 2004-07-30 2005-08-01 Advanced Semiconductor Eng Chip package structure and process for fabricating the same
GB0507887D0 (en) * 2005-04-20 2005-05-25 Rohm & Haas Elect Mat Immersion method
US7713859B2 (en) * 2005-08-15 2010-05-11 Enthone Inc. Tin-silver solder bumping in electronics manufacture
KR100719905B1 (ko) * 2005-12-29 2007-05-18 삼성전자주식회사 Ｓｎ-Ｂｉ계 솔더 합금 및 이를 이용한 반도체 소자
US7473580B2 (en) * 2006-05-18 2009-01-06 International Business Machines Corporation Temporary chip attach using injection molded solder
US8236610B2 (en) * 2009-05-26 2012-08-07 International Business Machines Corporation Forming semiconductor chip connections
US7919406B2 (en) * 2009-07-08 2011-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming pillar bump structure having sidewall protection
US8779604B1 (en) * 2013-11-06 2014-07-15 Chipmos Technologies Inc. Semiconductor structure and manufacturing method thereof
US20150171039A1 (en) * 2013-12-13 2015-06-18 Chipmos Technologies Inc. Redistribution layer alloy structure and manufacturing method thereof
US9136237B2 (en) * 2013-12-17 2015-09-15 Oracle International Corporation Electroplated solder for high-temperature interconnect
US9520370B2 (en) * 2014-05-20 2016-12-13 Micron Technology, Inc. Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1603054A (zh) * 2003-10-01 2005-04-06 三星电子株式会社 锡银金焊料凸点、其制造方法及用其焊接发光装置的方法
CN1600495A (zh) * 2004-10-27 2005-03-30 新磊微制造股份有限公司 导体接合方法及应用其中的锡金焊料结构
CN101075650A (zh) * 2006-05-18 2007-11-21 洲磊科技股份有限公司 适用于覆晶封装的发光二极管结构及其制造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JEONG-WON YOON 等: "Reliability analysis of Au–Sn flip-chip solder bump fabricated by co-electroplating", 《JOURNAL OF MATERIALS RESEARCH》 *
杨圣: "《先进传感技术》", 31 January 2014, 合肥：中国科学技术大学出版社 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111433907A (zh) * 2017-11-17 2020-07-17 美光科技公司 具有多层囊封剂的半导体装置及相关联系统、装置与方法
CN111433907B (zh) * 2017-11-17 2024-01-09 美光科技公司 具有多层囊封剂的半导体装置及相关联系统、装置与方法
CN109663998A (zh) * 2018-11-29 2019-04-23 贵州振华风光半导体有限公司 一种功率半导体芯片钎焊溢料控制方法

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