TWI578532B - 場效電晶體及其製備方法 - Google Patents

場效電晶體及其製備方法 Download PDF

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TWI578532B
TWI578532B TW105107619A TW105107619A TWI578532B TW I578532 B TWI578532 B TW I578532B TW 105107619 A TW105107619 A TW 105107619A TW 105107619 A TW105107619 A TW 105107619A TW I578532 B TWI578532 B TW I578532B
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layer
field effect
effect transistor
iii
gate
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TW105107619A
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TW201714308A (zh
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肖德元
汝京 張
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上海新昇半導體科技有限公司
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Description

場效電晶體及其製備方法
本發明涉及半導體製造技術領域,尤其涉及一種場效電晶體及其製備方法。
高電子遷移率電晶體(HEMT)的基本結構中包括一個調製摻雜異質接面,由於組成異質接面的兩種材料的禁帶寬度不同,HEMT的閘極上加上偏壓後,在異質接面介面處分別形成勢阱和勢障,由於極化效應或調製摻雜產生的自由電子積累在異質接面靠近介面處的勢阱中,形成二維電子氣(2-DEG),二維電子氣由於不受電離雜質離子散射的影響,遷移率非常高。並且,因為電子與雜質中心在空間上是分隔開的,在極低溫度下也不“凍結”(即不複合),因此,HEMT有很好的低溫性能,可用於低溫研究工作(如分數量子Hall效應)中。HEMT是電壓控制元件,閘極電壓Vg可控制異質接面勢阱的深度,從而控制勢阱中2-DEG的面密度,進而控制元件的工作電流。
本發明的目的在於,提供一種場效電晶體及其製作方法,場效電晶體為高電子遷移率電晶體,進一步提高元件的性能。
為解決上述技術問題,本發明提供一種場效電晶體,包括:半導體基板;位於所述半導體基板中的鍺奈米線;包圍在鍺奈米線四周的第一III-V化合物層;依次包圍在部分所述第一III-V化合物層四周的勢障層、閘介電層和閘極;以及位於所述第一III-V化合物層上,並分別位於所述閘極兩側的源極區和汲極區。
可選的,所述鍺奈米線為P型摻雜,所述鍺奈米線的截面為圓形,直徑為10nm~100nm。
可選的,所述第一III-V化合物層為N型InGaAs,厚度為10nm~100nm。
可選的,所述勢障層為Si摻雜的InP,Si的摻雜濃度為1.0×1018cm-3~1.5×1018cm-3,所述勢障層的厚度為50nm~100nm。
可選的,所述閘介電層為高k介電層,所述閘介電層的材料為Al2O3或TiSiOx,厚度為1nm~5nm。
可選的,所述閘極為TiN、NiAu或CrAu中的一種。
可選的,所述源極區和所述汲極區為N型離子摻雜的In0.25Ga0.75As。
可選的,所述場效電晶體還包括位於所述閘極兩側的側牆、位於所述源極區上的源極和位於所述汲極區上的汲極。
作為本發明的另一方面,本發明還提供一種場效電晶體的製備方法,包括:提供半導體基板,所述半導體基板表面具有溝槽以及懸空於所述溝槽上方的鍺奈米線; 形成依次包圍在所述鍺奈米線四周的第一III-V化合物層和第二III-V化合物層;在所述第二III-V化合物層中形成凹槽,所述凹槽暴露所述第一III-V化合物層;在所述凹槽中依次形成勢障層、閘介電層以及閘極;在所述閘極兩側的所述第二III-V化合物層上形成側牆;對所述第二III-V化合物層進行N型離子植入,分別形成源極區和汲極區。
可選的,在所述半導體基板表面形成所述鍺奈米線的步驟包括:形成一鍺矽合金層,所述鍺矽合金層覆蓋所述半導體基板;形成淺溝槽隔離結構,所述淺溝槽隔離結構將所述鍺矽合金層分割開;去除部分所述淺溝槽隔離結構,暴露部分所述鍺矽合金層的側壁;進行選擇性磊晶,形成多邊形結構的鍺矽合金層;進行熱氧化,多邊形結構的鍺矽合金層形成氧化矽層以及包裹在所述氧化矽層中的鍺奈米線;去除所述氧化矽層,形成所述溝槽以及懸空在所述溝槽中的所述鍺奈米線;在氫氣中對所述鍺奈米線進行熱退火;在所述溝槽中形成一氧化矽層。
可選的,所述鍺奈米線為P型摻雜,所述鍺奈米線的截面為圓形,直徑為10nm~100nm。
可選的,採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成所述第一III-V化合物層,所述第一III-V化合物層的材料為N型InGaAs,厚度為10nm~100nm。
可選的,採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成所述第二III-V化合物層,所述第二III-V化合物層為In0.25Ga0.75As。
可選的,採用電感耦合等離子體蝕刻所述第二III-V化合物層,形成所述凹槽。
可選的,採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成所述勢障層,所述勢障層為Si摻雜的InP,Si的摻雜濃度為1.0×1018cm-3~1.5×1018cm-3,所述勢障層的厚度為50nm~100nm。
可選的,採用金屬有機化合物化學氣相沉積、原子層沉積或等離子體增強化學氣相沉積形成所述閘介電層,所述閘介電層為高k介電層,所述閘介電層的材料為Al2O3或TiSiOx,厚度為1nm~5nm。
可選的,採用物理氣相沉積、金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成所述閘極,所述閘極為TiN、NiAu或CrAu中的一種。
可選的,所述場效電晶體的製備方法還包括:在所述源極區上形成源極,在所述汲極區上形成汲極。
可選的,所述源極和所述汲極為TiN、NiAu或CrAu中的一種。
本發明提供的場效電晶體及其製備方法中,勢障層的禁帶寬度比第一III-V化合物層的禁帶寬度寬,並且,勢障層和第一III-V化合物層的能帶彎曲不同,使得在第一III-V化合物層靠近勢障層的介面處形成二維電子氣,二維電子氣遷移率較高,從而場效電晶體具有更好的電學性能。此外,場效電晶體為閘極完全包圍的元件,提高場效電晶體的電學性能。
S110,S120,S130
100‧‧‧半導體基板
110‧‧‧鍺矽合金層
120‧‧‧淺溝槽隔離結構
130、150‧‧‧氧化矽層
210‧‧‧溝道
211‧‧‧鍺奈米線
212‧‧‧第一III-V化合物層
220‧‧‧勢障層
230‧‧‧閘極
231‧‧‧閘介電層
232‧‧‧閘極層
241、261‧‧‧源極區
242、262‧‧‧汲極區
250‧‧‧側牆
270‧‧‧第二III-V化合物層
280‧‧‧凹槽
第1圖為本發明一實施例中的場效電晶體的剖面結構示意圖; 第2圖為本發明一實施例中製備場效電晶體的製備方法的流程圖;第3a圖~第3m圖為本發明一實施例中製備場效電晶體各步驟中的剖面結構示意圖;第4圖為本發明一實施例中的不加偏壓時場效電晶體的能帶圖;第5圖為本發明一實施例中的加正向偏壓時N型場效電晶體的能帶圖。
下面將結合示意圖對本發明的場效電晶體及其製備方法進行更詳細的描述,其中表示了本發明的優選實施例,應該理解本領域技術人員可以修改在此描述的本發明,而仍然實現本發明的有利效果。因此,下列描述應當被理解為對於本領域技術人員的廣泛知道,而並不作為對本發明的限制。
本發明的核心思想在於,提供的場效電晶體中,鍺奈米線與第一III-V化合物層形成III-V鍺量子阱的溝道,勢障層的禁帶寬度比第一III-V化合物層的禁帶寬度寬,並且,勢障層和第一III-V化合物層的能帶彎曲不同,使得在第一III-V化合物層靠近勢障層的介面處形成二維電子氣,二維電子氣遷移率較高,從而場效電晶體具有更好的電學性能。此外,場效電晶體為閘極全包圍的元件,提高場效電晶體的電學性能。
下文結合附圖對本發明的場效電晶體進行詳細的描述。本發明提供的場效電晶體的剖面結構示意圖參考第1圖所示,場效電晶體包括:半導體基板100;位於所述半導體基板100中的鍺奈米線211;包圍在鍺奈米線211四周的第一III-V化合物層212;依次包圍在部分所述第一III-V化合物層212四周的勢障層220、閘介電層231和閘極232;以及位於所述第一III-V化合物層212上,並分別位於所述閘極232兩側的源極區241和汲極區242。
在本實施例中,所述鍺奈米線211為P型摻雜,所述鍺奈米線211的截面為圓形,直徑為10nm~100nm。所述第一III-V化合物層212的材料為N型InGaAs,第一III-V化合物層212的厚度為10nm~100nm。鍺奈米線211與第一III-V化合物層212構成N型場效電晶體的溝道210,即形成III-V/鍺量子阱的溝道。
所述勢障層220為Si摻雜的InP,Si的摻雜濃度為1.0×1018cm-3~1.5×1018cm-3,勢障層220的厚度為50nm~100nm。可以理解的是,勢障層220與第一III-V化合物層212之間形成場效電晶體的異質接面結構,勢障層220的禁帶寬度比第一III-V化合物層212的禁帶寬度寬,並且,當在閘極上加偏壓後,勢障層220和第一III-V化合物層212的能帶彎曲不同,使得在第 一III-V化合物層212靠近勢障層220的介面處形成二維電子氣(2DEG),二維電子氣遷移率較高,從而場效電晶體具有更好的傳輸性能。
所述閘介電層231為高k介電層,例如,所述閘介電層的材料為Al2O3或TiSiOx,所述閘介電層231的厚度為1nm~5nm。所述閘極232為TiN、NiAu或CrAu中的一種。閘介電層231與閘極232形成場效電晶體的閘極230。需要說明的是,本發明中,閘極230完全包圍在溝道210周圍,形成閘極全包圍的元件,並且,採用高k材料的的閘介電層,提高場效電晶體的電學性能。
本實施例中,以N型場效電晶體為例進行說明,所述源極區241和汲極區242為N型重離子摻雜的In0.25Ga0.75As,並且,所述N型場效電晶體還包括位於源極區241上的源極261和位於汲極區242上的汲極262,源極261將源極區241引出,汲極262將汲極區242引出。
此外,本發明的場效電晶體中包括位於閘極230兩側的側牆250,側牆250為氧化矽、氮化矽等,側牆250用於保護閘極230。
作為本發明的另一方面,本發明還提供一種場效電晶體的製備方法,第2圖為場效電晶體的製備方法的流程圖,結合第3a~3m圖對場效電晶體的製備過程進行說明,其具體包括如下步驟:首先,執行步驟S1,參考第3a圖所示,提供半導體基板100,所述半導體基板100表面具有溝槽以及懸空於所述溝槽上方的鍺奈米線。在所述半導體基板表面形成所述溝槽以及懸空於所述溝槽上的所述鍺奈米線的步驟進一步包括:參考第3a圖所示,形成一鍺矽合金層110,所述鍺矽合金層110覆蓋所述半導體基板100; 參考第3b圖所示,在半導體基板100中形成淺溝槽隔離結構120,淺溝槽隔離結構120間隔的設置在半導體基板100中,並且,所述淺溝槽隔離結構120將所述鍺矽合金層110分隔開;參考第3c圖所示,去除部分所述淺溝槽隔離結構120,暴露部分所述鍺矽合金層110的側壁;參考第3d圖所示,進行選擇性磊晶,由於鍺矽合金各個晶向上的生長速率的差異,使得鍺矽合金形成多邊形結構的鍺矽合金層110,例如,形成六邊形的鍺矽合金層110,多邊形結構的鍺矽合金層便於後續製程中進行氧化濃縮,形成鍺奈米線;參考第3e圖所示,進行熱氧化,多邊形的鍺矽合金層110形成氧化矽層130以及包裹在所述氧化矽層130中的鍺奈米線211,熱氧化的過程中,矽、鍺進行氧化濃縮,使得鍺聚集形成鍺奈米線,在本實施例中,所述鍺奈米線211的截面均為圓形,直徑為10nm~100nm,此外,熱氧化的過程中,氧化矽層130還包括所述半導體基板100表面形成氧化矽;參考第3f圖所示,去除所述氧化矽層130,形成所述溝槽(圖中未示出)以及懸空在所述溝槽中的鍺奈米線211;之後,在氫氣中對所述鍺奈米線211進行熱退火,使得鍺奈米線211的表面更加光滑;參考第3g圖所示,在所述溝槽中形成一氧化矽層150,防止後續的製程影響半導體基板100。
其次,執行步驟S2,參考第3h圖和第3i圖所示,其中,第3i圖是第3h圖沿AA’方向的剖面圖,形成依次包圍在所述鍺奈米線211四周的 第一III-V化合物層212和第二III-V化合物層270。在本實施例中,採用金屬有機化合物化學氣相沉積(Metal organic chemical vapor deposition,MOCVD)、原子層沉積(Atomic layer deposition,ALD)或分子束磊晶(Molecular beam epitaxy,MBE)形成所述第一III-V化合物層212,所述第一III-V化合物層212的材料為N型InGaAs。採用金屬有機化合物化學氣相沉積(MOCVD)、原子層沉積(ALD)或分子束磊晶(MBE)形成所述第二III-V化合物層270,所述第二III-V化合物層270的材料為N型重離子摻雜的In0.25Ga0.75As,厚度為10nm~200nm。
再次,執行步驟S3,參考第3j圖所示,蝕刻所述第二III-V化合物層270,在所述第二III-V化合物層270形成凹槽280,所述凹槽280暴露所述第一III-V化合物層212。採用電感耦合電漿(Induced coupling plasma,ICP)蝕刻所述第二III-V化合物層270形成所述凹槽280。
執行步驟S4,參考第3k圖所示,依次形成勢障層220、閘介電層231以及閘極232,勢障層220、閘介電層231以及閘極232依次包圍所述凹槽280以及所述第二III-V化合物層270。本實施例中,採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成所述勢障層220,所述勢障層220的材料為Si摻雜的InP,Si的摻雜濃度為1.0×1018cm-3~1.5×1018cm-3,所述勢障層220的厚度為50nm~100nm。採用金屬有機化合物化學氣相沉積、原子層沉積或電漿增強化學氣相沉積形成所述閘介電層231,所述閘介電層231的材料高k介電層,例如,所述閘介電層231的材料為Al2O3或TiSiOx,所述閘介電層231的厚度為1nm~5nm。採用物理氣相沉積、金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成所述閘極232,所述閘極231為TiN、NiAu 或CrAu中的一種。需要說明的是,勢障層220、閘介電層231以及閘極232完全包圍溝道210,閘介電層231以及閘極232形成場效電晶體的閘極230,從而形成閘極完全包圍的元件,提高載子的遷移率,提高元件的性能。
接著,參考第31圖所示,蝕刻閘極232、所述閘介電層231以及勢障層220,保留凹槽280中以及部分所述第二III-V化合物層270上的閘極232、所述閘介電層231以及勢障層220。在本實施例中,勢障層220用於調節第一III-V化合物層212中的二維電子氣的面密度,從而控制場效電晶體的工作電流。
執行步驟S5,參考第3m圖所示,在第二III-V化合物層270上所述閘極232的兩側形成側牆250,側牆250用於保護閘極230; 執行步驟S6,參考第1圖所示,對所述第二III-V化合物層270進行N型離子植入,形成源極區241和汲極區242。本發明中,簡化源極區241和汲極區242的製備方法,形成的非平面場效電晶體具有更小的寄生電阻。
此外,所述場效電晶體的製備方法還包括:在源極區241上形成源極261,在所述汲極區242上形成汲極262。所述源極261、所述汲極262均為TiN、NiAu或CrAu中的一種。
參考第4圖中所示,在閘極230上不加偏壓時,場效電晶體異質接面的能帶均不發生彎曲。參考第5圖中所示,在閘極230上加上正向偏壓、源極連接地端時,由於異質接面中第一勢障層220的禁帶寬度(1.35eV)大於第一III-V化合物層212的禁帶寬度(1.0eV),並且,第一勢障層220和第一III-V化合物層212的能帶彎曲不同,使得導帶Ec中的電子進入費米能級Ef以下,從而第一III-V化合物層212靠近第一勢障層220的介面處形成二維電子 氣,從而場效電晶體導通。本發明中,二維電子氣(2-DEG)作為場效電晶體的載子,其遷移率高,從而大大提高場效電晶體的傳輸性能。
綜上所述,本發明中,勢障層的禁帶寬度比第一III-V化合物層的禁帶寬度寬,並且,勢障層和第一III-V化合物層的能帶彎曲不同,使得在第一III-V化合物層靠近勢障層的介面處形成二維電子氣,二維電子氣遷移率較高,從而場效電晶體具有更好的電學性能。此外,場效電晶體為閘極全包圍的元件,提高場效電晶體的電學性能。
顯然,本領域的技術人員可以對本發明進行各種改動和變型而不脫離本發明的精神和範圍。這樣,倘若本發明的這些修改和變型屬於本發明權利要求及其等同技術的範圍之內,則本發明也意圖包含這些改動和變型在內。
以上敍述依據本發明多個不同實施例,其中各項特徵可以單一或不同結合方式實施。因此,本發明實施方式之揭露為闡明本發明原則之具體實施例,應不拘限本發明於所揭示的實施例。進一步言之,先前敍述及其附圖僅為本發明示範之用,並不受其限囿。其他元件之變化或組合皆可能,且不悖於本發明之精神與範圍。
S1~S6‧‧‧步驟

Claims (18)

  1. 一種場效電晶體,包括:半導體基板;位於所述半導體基板中的鍺奈米線;包圍在鍺奈米線四周的第一III-V化合物層;依次包圍在部分所述第一III-V化合物層四周的勢障層、閘介電層和閘極;以及位於所述第一III-V化合物層上,並分別位於所述閘極兩側的源極區和汲極區,其中所述勢障層為Si摻雜的InP,Si的摻雜濃度為1.0×1018cm-3~1.5×1018cm-3,所述勢障層的厚度為50nm~100nm。
  2. 如權利要求1所述的場效電晶體,其中所述鍺奈米線為P型摻雜,所述鍺奈米線的截面為圓形,直徑為10nm~100nm。
  3. 如權利要求1所述的場效電晶體,其中所述第一III-V化合物層為N型InGaAs,厚度為10nm~100nm。
  4. 如權利要求1所述的場效電晶體,其中所述閘介電層為高k介電層,所述閘介電層的材料為Al2O3或TiSiOx,厚度為1nm~5nm。
  5. 如權利要求1所述的場效電晶體,其中所述閘極為TiN、NiAu或CrAu中的一種。
  6. 如權利要求1所述的場效電晶體,其中所述源極區和所述汲極區為N型離子摻雜的In0.25Ga0.75As。
  7. 如權利要求1所述的場效電晶體,其中所述場效電晶體還包括位於所述閘極兩側的側牆、位於所述源極區上的源極和位於所述汲極區上的汲極。
  8. 一種場效電晶體的製備方法,包括:提供半導體基板,所述半導體基板表面具有溝槽以及懸空於所述溝槽上方的鍺奈米線;形成依次包圍在所述鍺奈米線四周的第一III-V化合物層和第二III-V化合物層;在所述第二III-V化合物層中形成凹槽,所述凹槽暴露所述第一III-V化合物層;在所述凹槽中依次形成勢障層、閘介電層以及閘極;在所述閘極兩側的所述第二III-V化合物層上形成側牆;對所述第二III-V化合物層進行N型離子植入,分別形成源極區和汲極區。
  9. 如權利要求8所述的場效電晶體的製備方法,其中在所述半導體基板表面形成所述鍺奈米線的步驟包括:形成一鍺矽合金層,所述鍺矽合金層覆蓋所述半導體基板;形成淺溝槽隔離結構,所述淺溝槽隔離結構將所述鍺矽合金層分割開;去除部分所述淺溝槽隔離結構,暴露部分所述鍺矽合金層的側壁;進行選擇性磊晶,形成多邊形結構的鍺矽合金層;進行熱氧化,多邊形結構的鍺矽合金層形成氧化矽層以及包裹在所述氧化矽層中的鍺奈米線;去除所述氧化矽層,形成所述溝槽以及懸空在所述溝槽中的所述鍺奈米線;在氫氣中對所述鍺奈米線進行熱退火; 在所述溝槽中形成一氧化矽層。
  10. 如權利要求9所述的場效電晶體的製備方法,其中所述鍺奈米線為P型摻雜,所述鍺奈米線的截面為圓形,直徑為10nm~100nm。
  11. 如權利要求8所述的場效電晶體的製備方法,其中所述第一III-V化合物層係採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成,所述第一III-V化合物層的材料為N型InGaAs,厚度為10nm~100nm。
  12. 如權利要求8所述的場效電晶體的製備方法,其中所述第二III-V化合物層係採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成,所述第二III-V化合物層為In0.25Ga0.75As。
  13. 如權利要求8所述的場效電晶體的製備方法,其中所述凹槽係採用電感耦合電漿蝕刻所述第二III-V化合物層而形成。
  14. 如權利要求8所述的場效電晶體的製備方法,其中所述勢障層係採用金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成,所述勢障層為Si摻雜的InP,Si的摻雜濃度為1.0×1018cm-3~1.5×1018cm-3,所述勢障層的厚度為50nm~100nm。
  15. 如權利要求8所述的場效電晶體的製備方法,其中所述閘介電層係採用金屬有機化合物化學氣相沉積、原子層沉積或電漿增強化學氣相沉積形成,所述閘介電層為高k介電層,所述閘介電層的材料為Al2O3或TiSiOx,厚度為1nm~5nm。
  16. 如權利要求8所述的場效電晶體的製備方法,其中所述閘極係採用物理氣相沉積、金屬有機化合物化學氣相沉積、原子層沉積或分子束磊晶形成,所述閘極為TiN、NiAu或CrAu中的一種。
  17. 如權利要求8所述的場效電晶體的製備方法,更包括:在所述源極區上形成源極,在所述汲極區上形成汲極。
  18. 如權利要求17所述的場效電晶體的製備方法,其中所述源極和所述汲極為TiN、NiAu或CrAu中的一種。
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