TWI548781B - 鍍覆浴及方法 - Google Patents
鍍覆浴及方法 Download PDFInfo
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- TWI548781B TWI548781B TW103138321A TW103138321A TWI548781B TW I548781 B TWI548781 B TW I548781B TW 103138321 A TW103138321 A TW 103138321A TW 103138321 A TW103138321 A TW 103138321A TW I548781 B TWI548781 B TW I548781B
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- tin
- alkyl
- acid
- silver
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- C—CHEMISTRY; METALLURGY
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- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/30—Electroplating: Baths therefor from solutions of tin
- C25D3/32—Electroplating: Baths therefor from solutions of tin characterised by the organic bath constituents used
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- C25D3/56—Electroplating: Baths therefor from solutions of alloys
- C25D3/60—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of tin
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Description
本發明通常係關於電鍍覆金屬之領域。特別地,本發明係關於電鍍覆錫之領域。
金屬及金屬合金於商業上係重要者,尤其在電子工業中,往往用於作為電性觸點、最終處理劑及焊料。由於對使用鉛之限制增加,曾經最常用之錫合金焊料錫-鉛的使用業經下滑。無鉛焊料如錫、錫-銀、錫-銅、錫-鉍、錫-銀-銅等係錫-鉛焊料之常用替代品。往往使用鍍覆浴如電鍍覆浴,將此等焊料沉積於基板上。
以金屬塗層電鍍覆物件之方法通常係包括:令電流穿過位於鍍覆溶液中之兩個電極之間,其中,該等電極之一者(典型係陰極)係該待鍍覆之物件。典型之錫鍍覆溶液係包含經溶解之錫離子、水、其量足以賦予該浴以導電性之酸電解質如甲磺酸、抗氧化劑、及適宜之佐劑以改善鍍覆之均勻性及金屬沉積之品質。此等佐劑係包括界面活性劑、細晶劑等。
於電子工業中,對於無鉛焊料鍍覆之某些應用係存在挑戰。舉例而言,當用於作為銅導柱上之封蓋
層時,係將相對小量之無鉛焊料如錫-銀焊料沉積於銅導柱之頂部。於鍍覆此等小量之焊料時,無論於晶片內或橫越晶圓,往往皆難以將均勻高度之焊料組成物鍍覆於各導柱上。使用傳統之焊料電鍍覆浴亦導致具有相對粗糙表面形貌之沉積,舉例而言,具有平均表面粗糙度(Ra)約為800奈米(nm)或更大,粗糙度係藉由光學輪廓測量儀量測。此相對粗糙表面形貌往往係與再焊後焊料中空洞之形成相關聯,其根本上引起對於焊料接點可實現性之關注。藉此,於工業中,對於避免較粗糙之表面形貌之問題並改善模內均勻性的錫或錫合金焊料沉積存在興趣。
多種傳統錫電鍍覆浴係已知者。當所欲者係光亮表面時,光亮劑,有時係指細晶劑,典型係用於錫電鍍覆浴中。傳統光亮劑係包括醛類、酮類、羧酸類、羧酸衍生物、胺類、或其混合物。於第7,314,543號美國專利中業經報導,自含有磺基丙基化陰離子性界面活性劑及細晶劑之酸性錫電鍍覆浴沉積的錫層,於周邊環境下存儲6個月後,並不顯示晶鬚,上述界面活性劑係諸如式R(OCH2CH2)nO(CH2)3SO3X之化合物,其中,R係正烷基且X為陽離子部分,而該細晶劑係諸如界於10與30ppm之間的亞苄基丙酮。惟,當使用含有磺基丙基化之陰離子性界面活性劑及亞苄基丙酮作為細晶劑的錫或錫合金電鍍覆浴,在半導體晶圓上沉積含錫焊料凸塊時,此等焊料凸塊飽受較差形貌及極差模內(WID)均勻性之苦,通常係>30% WID。因此,工業上對用於在銅導柱上沉積含錫焊料層如
焊料凸塊或封帽的電鍍覆浴及方法存在需求,且該等焊料凸塊或封帽係兼具適宜之形貌及良好之模內均勻性兩者。
本發明係提供一種電鍍覆組成物,其係包含:錫離子源;酸電解質;0.0001至0.075g/L之式(1)或(2)之細晶劑
其中,每一R1係獨立為(C1-6)烷基、(C1-6)烷氧基、羥基、或鹵素;R2與R3係獨立選自H及(C1-6)烷基;R4係H、OH、(C1-6)烷基或O(C1-6)烷基;m係0至2之整數;每一R5係獨立為(C1-6)烷基;每一R6係獨立選自H、OH、(C1-6)烷基、或O(C1-6)烷基;n係1或2;以及,p係0、1或2;式(3)或(4)之非離子性界面活性劑:
其中,A與B係代表不同之環氧烷部分,且x與y係分別代表各環氧烷之重複單元的數目;以及水。
本發明亦提供一種於半導體基板沉積含錫層的方法,係包含:提供包含複數個導電結合部分(bonding feature)之半導體晶圓;令該半導體晶圓與上揭之組成物接
觸;以及,施用足量之電流密度,以於該等導電結合部分沉積一含錫層。
第1圖係掃描電子顯微照片(SEM),其係顯示使用本發明之電鍍覆浴的錫-銀焊料沉積。
第2圖係SEM,其係顯示使用比較性電鍍覆浴的錫-銀焊料沉積。
本說明書中,除非內文明確指出者,下述縮寫應具有下述意義:ASD=A/dm2=安培每平方公分;℃=攝氏度;g=公克;mg=毫克;L=公升;Å=埃;nm=奈米;μm=micron=微米;mm=毫米;min=分鐘;DI=去離子;以及,mL=毫升。除了特別指出者,全部之量係重量百分比(「wt%」),且全部比係重量比。全部數值範圍係包括邊值且可以任意次序組合,惟此等數值範圍係明確界定其加和為100%。
本說明書中,術語「鍍覆」係指金屬電鍍覆。本說明書中,「沉積」與「鍍覆」可互換使用。「純錫」係指並非錫合金之錫沉積,但此沉積可含有最高5原子%之雜質。「鹵化物」係指氯化物、溴化物、碘化物及氟化物。冠詞「一」、「該」係指單數及複數。「烷基」係指線性、分支鏈、及環狀烷基。「芳基」係指芳族碳環及芳族雜環。術語「(甲基)丙烯酸系」係指「丙烯酸系」及「甲基丙烯酸系」兩者。當一元件被指為「沉積於另一元件上」時,其
可直接位於該另一元件上或存在於其與另一元件之間間隔元件。反之,當一元件被指為「直接沉積於另一元件上」,則不存在間隔元件。本文中,術語「及/或」係包括一個或多個所列述之相關項目的任意及全部組合。
本發明之組成物係包含:錫離子源;酸電解質;0.0001至0.075g/L之式(1)或(2)之細晶劑
其中,每一R1係獨立為(C1-6)烷基、(C1-6)烷氧基、羥基、或鹵素;R2與R3係獨立選自H及(C1-6)烷基;R4係H、OH、(C1-6)烷基或O(C1-6)烷基;m係0至2之整數;每一R5係獨立為(C1-6)烷基;每一R6係獨立選自H、OH、(C1-6)烷基、或O(C1-6)烷基;n係1或2;以及,p係0、1或2;式(3)或(4)之非離子性界面活性劑:
其中,A與B係代表不同之環氧烷部分,且x與y係分別代表每一環氧烷基之重複單元的數目;以及水。
任意之浴溶性二價錫鹽可適用於作為該錫離子源。此等錫鹽之實例係包括,但不限於,氧化錫;及鹽類,如鹵化錫,硫酸錫,烷磺酸錫如甲烷磺酸錫及乙烷磺酸
錫,芳基磺酸錫如苯磺酸錫、苯酚磺酸錫(phenolsulfonate)、甲酚磺酸錫、及甲苯磺酸錫,烷醇磺酸錫等。當使用鹵化錫時,較佳係該鹵化物為氯化物。較佳係該錫化合物為氧化錫、硫酸錫、氯化錫、烷磺酸錫或芳基磺酸錫。更佳地,該錫鹽係甲磺酸、乙磺酸、丙磺酸、2-羥基乙烷-1-磺酸、2-羥基丙烷-1-磺酸、1-羥基丙烷-2-磺酸、苯磺酸、甲苯磺酸、苯酚磺酸或甲酚磺酸之亞錫鹽,甚至更佳係甲磺酸、苯磺酸或苯酚磺酸之亞錫鹽。可使用錫鹽之混合物。可用於本發明之錫化合物通常可自多種來源商購之,且可不經進一步之純化而使用。或者,可用於本發明之錫化合物可藉由文獻中已知之方法製備之。典型地,本發明之組成物中錫離子的量係10至300g/L之範圍,較佳20至200g/L,更佳30至100g/L。
於本發明中,可使用浴溶性且不對電解質組成物造成負面影響之任意酸電解質。適宜之酸電解質係包括,但不限於:烷磺酸類,如甲磺酸、乙磺酸及丙磺酸;芳基磺酸類如苯磺酸、甲苯磺酸、苯酚磺酸、及甲酚磺酸;烷醇磺酸類;硫酸;胺基磺酸;及無機酸類,如鹽酸、氫溴酸及氫氟酸。烷磺酸類及芳基磺酸類係較佳之酸電解質,且烷磺酸類更佳。甲磺酸係特佳。特別有用者係酸電解質之混合物,例如,但不限於烷磺酸類及硫酸之混合物。由是,於本發明中,較佳可使用超過一種酸電解質。可用於本發明之酸性電解質通常係可商購者,且可不經進一步之純化而使用。或者,該等酸電解質可藉由文獻中已知之
方法製備之。典型地,本發明之組成物中酸的量係10至1000g/L之範圍,較佳20至750g/L,更佳30至500g/L。
本發明之組成物係包含細晶劑,其係選自式(1)或(2)之化合物
其中,每一R1係獨立為(C1-6)烷基、(C1-6)烷氧基、羥基、或鹵素;R2與R3係獨立選自H及(C1-6)烷基;R4係H、OH、(C1-6)烷基或O(C1-6)烷基;m係0至2之整數;每一R5係獨立為(C1-6)烷基;每一R6係獨立選自H、OH、(C1-6)烷基、或O(C1-6)烷基;n係1或2;以及,p係0、1或2。較佳地,每一R1係獨立為(C1-6)烷基、(C1-3)烷氧基、或羥基,更佳係(C1-4)烷基、(C1-2)烷氧基、或羥基。較佳地,R2與R3係獨立選自H及(C1-3)烷基,更佳係H及甲基。較佳地,R4係H、OH、(C1-4)烷基或O(C1-4)烷基,更佳係H、OH、或(C1-4)烷基。較佳地,R5係(C1-4)烷基,更佳係(C1-3)烷基。每一R6係獨立選自H、OH、或(C1-6)烷基,更佳係H、OH、或(C1-3)烷基,再更佳係H或OH。較佳地,m係0或1,更佳地,m係0。較佳地,n=1。較佳地,p係0或1,更佳地,p=0。可使用細晶劑之混合物,如2種不同之式1之細晶劑的混合物,2種不同之式2之細晶劑的混合物,或式1之細晶劑與式2之細晶劑的混合物。較佳地,該細晶劑係式(1)之化合物。
可用於作為細晶劑之例示性化合物係包括,但不限於,肉桂酸、肉桂醛、亞苄基丙酮、2-吡啶甲酸、吡啶二甲酸、吡啶甲醛、吡啶二甲醛、或其混合物。較佳之細晶劑係包括肉桂酸、肉桂醛、及亞苄基丙酮。
於本發明之鍍覆浴中,細晶劑係以0.0001至0.045g/L之量存在。較佳地,細晶劑係以0.0001至0.04g/L,更佳0.0001至0.035g/L,再更佳0.0001至0.03g/L之量存在。可用於作為細晶劑之化合物通常係可自多種來源商購之,且可直接使用或可經進一步純化後使用。
一種或多種非離子性界面活性劑係用於本發明之組成物中,該界面活性劑係衍生自不同環氧烷與伸乙二胺化合物之加成反應的四官能性聚醚。此等界面活性劑係具有式(3)或(4):
其中,A與B係表示不同之環氧烷部分,且x與y係分別表示每一環氧烷基重複單元的數目。較佳地,A與B係選自(C2-4)環氧烷,更佳係選自環氧丙烷(PO)及環氧乙烷(EO)。於式3及4之化合物中,該等環氧烷部分可為嵌段、交替或隨機排列,且更佳係嵌段排列。於式3及4中,x:y之莫耳比典型係自10:90至90:10,較佳係自10:90至80:20。此等非離子性界面活性劑典型係具有平均分子量500至
40000,較佳750至35000,更佳1000至30000。此等四官能性聚醚通常可自例如,BASF(Ludwigshafen,Germany)於Tetronic品牌下商購,且可不經進一步之純化而直接使用。於該電解質組成物中,此等非離子性界面活性劑之存在濃度典型係,以該組成物之重量為基準計,1至10,000ppm,較佳5至10,000ppm。
通常,本發明之組成物係含有水。水可以寬範圍之量存在。可使用任意類型之水,如蒸餾水、去離子水或自來水。
本發明之組成物可視需要包括一種或多種佐劑,如抗氧化劑、有機溶劑、合金金屬、導電性酸、第二細晶劑、第二界面活性劑、錯合劑、及其混合物。
抗氧化劑可視需要添加至本發明之組成物中,以輔助將該錫保持為可溶之二價狀態。較佳係於本發明之組成物中使用一種或多種抗氧化劑。例示性抗氧化劑係包括,但不限於,氫醌,以及羥基化之芳族化合物,包括此等芳族化合物之磺酸衍生物,且較佳係:氫醌;甲基氫醌;間苯二酚;兒茶酚;1,2,3-三羥基苯;1,2-二羥基苯-4-磺酸;1,2-二羥基苯-3,5-二磺酸;1,4-二羥基苯-2-磺酸;1,4-二羥基苯-2,5-二磺酸;及2,4-二羥基苯磺酸。此等抗氧化劑係揭露於第4,871,429號美國專利中。其他適宜之抗氧化劑或還原劑係包括,但不限於,釩化合物,如乙醯基丙酮釩、三乙醯基丙酮釩、鹵化釩、氧鹵化釩、烷氧化釩、及烷氧化氧釩(vanadyl alkoxide)。此等還原劑之濃度係熟
識該技藝之人士所習知者,但典型係自0.1至10g/L之範圍,較佳係自1至5g/L。此等抗氧化劑通常可自多種來源商購之。
可將適當之有機溶劑加至本發明之錫電鍍覆組成物。典型之可用於本發明之組成物的溶劑係脂族醇類。較佳之有機溶劑係甲醇、乙醇、正丙醇、異丙醇、正丁醇、及異丁醇。此溶劑可以自0.05至15g/L,較佳自0.05至10g/L之量存在於錫電鍍覆組成物中。
視需要,本發明之鍍覆浴可含有一種或多種合金金屬離子源。適宜之合金金屬係包括,而不限於,銀、金、銅、鉍、銦、鋅、銻、錳、及其混合物。較佳之合金金屬係銀、銅、鉍、銦、及其混合物,更佳係銀。較佳地,本發明之組成物係不含鉛。該合金金屬之任意浴溶性鹽可適用於作為該合金金屬離子源。此等合金金屬鹽類之實例係包括,但不限於:金屬氧化物;金屬鹵化物;金屬氟硼酸鹽;金屬硫酸鹽;金屬烷磺酸鹽,如金屬甲磺酸鹽、金屬乙磺酸鹽及金屬丙磺酸鹽;金屬芳基磺酸鹽,如金屬苯磺酸鹽、金屬甲苯磺酸鹽及金屬苯酚磺酸鹽;金屬羧酸鹽類,如金屬葡萄糖酸鹽及金屬乙酸鹽等。較佳之合金金屬鹽類係金屬硫酸鹽;金屬烷磺酸鹽;及金屬芳基磺酸鹽。當將一種合金金屬加至本發明之組成物中時,係達成二元合金沉積。當將2種、3種或更多種不同之合金金屬加至本發明之組成物中時,則達成三元、四元或更高級之合金沉積。此合金金屬於本發明之組成物中的用量將取
決於所欲之特定錫合金。合金金屬之此等量的選擇係處於熟識該技藝之人士的能力範圍內。熟識該技藝之人士將明晰,當使用某種合金金屬如銀時,可能需要額外之錯合劑。此等錯合試劑(或錯合劑)係該技藝中習知者且可以任意適宜之量使用。
導電性酸可視需要加至本發明之組成物中。此等導電性酸係包括,但不限於,硼酸、烷酸、羥基烷酸、及此等酸之鹽,至該等可溶於水之程度。較佳係甲酸、乙酸、草酸、檸檬酸、蘋果酸、酒石酸、葡萄糖酸、葡萄糖二酸、葡萄糖醛酸、及此等酸之鹽。當使用時,此等導電性酸及其鹽係以傳統量採用之。
本發明之組成物除了包括上揭之細晶劑外,亦可視需要包括一種或多種第二細晶劑。極多種此等第二細晶劑係該技藝中已知者且任意者皆適宜,如彼等於第4,582,576號美國專利中揭示者。可用於本發明之較佳之第二細晶劑係α,β-不飽和脂族羰基化合物,包括,但不限於,α,β-不飽和羧酸類、α,β-不飽和羧酸酯類、α,β-不飽和醯胺類、及α,β-不飽和醛類。較佳地,該第二細晶劑係選自α,β-不飽和羧酸類、α,β-不飽和羧酸酯類、及α,β-不飽和醛類,更佳係α,β-不飽和羧酸類及α,β-不飽和醛類。例示性第二細晶劑係包括(甲基)丙烯酸、巴豆酸、(甲基)丙烯酸(C1-C6)烷基酯、(甲基)丙烯醯胺、巴豆酸(C1-C6)烷基酯、巴豆醯胺、巴豆醛、(甲基)丙烯醛、或其混合物。較佳之α,β-不飽和脂族羰基化合物係(甲基)
丙烯酸、巴豆酸、巴豆醛、(甲基)丙烯醛、或其混合物。當存在時,該第二細晶劑之用量典型係0.005至5g/L。較佳地,該第二細晶劑係以0.005至0.5g/L之量存在,更佳以0.005至0.25g/L之量存在,再更佳為0.01至0.25g/L。可用於作為該等第二細晶劑之化合物通常可自多種來源商購之,且可直接使用或可經進一步純化後使用。
視需要,一種或多種第二界面活性劑可用於本發明之組成物中。此等第二界面活性劑可為陰離子性、非離子性、兩性或陽離子性,較佳係非離子性。此等第二界面活性劑典型係具有自200至100,000,較佳自500至50,000,更佳自500至25,000,且再更佳750至15,000的平均分子量。當用於本發明之組成物中時,此等第二界面活性劑之存在的濃度典型係,以該組成物之重量為基準計,自1至10,000ppm,較佳自5至10,000ppm。較佳之非離子性界面活性劑係含有環氧烷之界面活性劑,尤其是聚伸烷基二醇類及(C2-4)環氧烷之縮合產物,其每一者均可藉由具有至少一個羥基及20個或更少碳原子的有機化合物封端,該有機化合物係具有一種類型之環氧烷或具有2種或更多種不同之環氧烷。較佳之環氧烷係環氧乙烷、環氧丙烷、環氧丁烷及其混合物。
典型地,可用於作為第二界面活性劑之聚伸烷基二醇類係彼等具有200至100,000,較佳自900至20,000範圍內之平均分子量者。較佳之聚伸烷基二醇類係聚乙二醇及聚丙二醇。此等聚伸烷基二醇類通常可自多種
來源商購之,且可不經進一步之純化而使用。亦可適宜地使用經封端之聚伸烷基二醇,其中,一個或多個末端氫係經烴基替代。適宜之聚伸烷基二醇的實例係式R-O-(CXYCX'Y'O)nR'之諸化合物,其中,R與R'係獨立選自H、(C2-20)烷基、及C6-20芳基;X、Y、X'及Y'係各自獨立選自氫,烷基如甲基、乙基或丙基,芳基如苯基,或芳烷基如苄基;以及,n係5至100,000之整數。典型地,X、Y、X'及Y'之一者或多者係氫。
尤其有用之(C2-4)環氧烷縮合產物係環氧乙烷/環氧丙烷(「EO/PO」)共聚物。適宜之EO/PO共聚物通常係具有自10:90至90:10,較佳10:90至80:20的EO:PO重量比。此等EO/PO共聚物較佳係具有平均分子量為1000至15,000。較佳之EO/PO共聚物係具有結構EO/PO/EO或PO/EO/PO的嵌段共聚物。此等EO/PO共聚物可自多種來源獲得,如彼等可自BASF於Pluronic品牌下商購者。適宜之以具有至少一個羥基及20個或更少碳原子之有機化合物封端的環氧烷縮合產物係包括下述者:具有1個至7個碳原子之脂族烴類、未經取代之芳族化合物、或於烷基部分具有6個或更少碳原子之經烷基化之芳族化合物,如彼等於第5,174,887號美國專利中揭露者。脂族醇類可為飽和或不飽和。適宜之芳族化合物係彼等具有最多兩個芳環者。於經環氧乙烷衍生化之前,芳族醇類係具有最多20個碳原子。此等脂族及芳族醇類可進一步經諸如硫酸酯基或磺酸酯基取代。此等適宜之環氧烷化合物係包括,但不限
於:具有12莫耳EO的乙氧基化聚苯乙烯化苯酚、具有5莫耳EO的乙氧基化丁醇、具有16莫耳EO的乙氧基化丁醇、具有8莫耳EO的乙氧基化丁醇、具有12莫耳EO的乙氧基化辛醇、具有13莫耳EO的乙氧基化β-萘酚、具有10莫耳EO的乙氧基化雙酚A、具有30莫耳EO的乙氧基化硫酸化雙酚A、及具有8莫耳EO的乙氧基化雙酚A。
本發明之電鍍覆組成物可藉由該技藝中已知之任意適宜之方法製備。典型地,其等係藉由將酸電解質加至容器內,之後加入錫化合物、細晶劑、界面活性劑、水及任意之適當組分而製備。該等組成物之組分的加入可使用其他次序。一旦該組成物製備完成,即藉由諸如過濾而移除任意非所欲之材質,並隨後加入水以調節該組成物之最終體積。該組成物可藉由任意已知手段如攪拌、泵浦、通氣、或噴射該組成物而攪動,從而提高沉積速度。
本發明之鍍覆浴係酸性,亦即,其具有<7之pH。典型地,本發明之鍍覆浴的pH係自-1至<7,較佳自-1至6.5,更佳自-1至6,且再更佳自-1至2。
本發明之電鍍覆組成物係適用於沉積含錫層,該等可為純錫層或錫合金層。例示性錫合金層係包括,而不限於,錫-銀、錫-銀-銅、錫-銀-銅-銻、錫-銀-銅-錳、錫-銀-鉍、錫-銀-銦、錫-銀-鋅-銅、及錫-銀-銦-鉍。較佳地,本發明之電鍍覆組成物係沉積純錫、錫-銀、錫-銀-銅、錫-銀-鉍、錫-銀-銦、及錫-銀-銦-鉍,且更佳係沉積純錫、錫-銀、或錫-銀-銅。自本發明之電鍍覆浴沉
積之合金係含有其量為0.01至99.99wt%範圍之錫,以及其量為99.99至0.01wt%範圍之一種或多種合金金屬,該等量係以該合金之重量為基準計,且係藉由原子吸收光譜(AAS)、X-射線螢光(XRF)、感應耦合電漿(ICP)或示差掃描量熱法(DSC)量測之。較佳地,使用本發明沉積之錫-銀合金係含有自75至99.99wt%之錫及0.01至10wt%之銀,以及任意其他合金金屬。更佳地,該等錫-銀合金沉積係含有自95至99.9wt%之錫及0.1至5wt%之銀及任意之其他合金金屬。錫-銀合金係較佳之錫合金沉積,且較佳係含有自90至99.9wt%之錫及自10至0.1wt%之銀。更佳地,該等錫-銀合金沉積係含有自95至99.9wt%之錫及自5至0.1wt%之銀。對於多種應用,可使用合金之共熔組成物。根據本發明沉積之合金係事實上不含鉛,亦即,其等含有1wt%之鉛,更佳0.5wt%,再更佳0.2wt%,且又更佳係不含鉛。
本發明之鍍覆組成物係可用於需要含錫層的多種鍍覆方法,尤其可用於在包含複數個導電性結合部分之半導體晶圓上沉積含錫之焊料層。鍍覆方法係包括,但不限於,水平或垂直晶圓鍍覆、滾筒鍍覆、掛鍍、高速鍍覆如卷盤至卷盤及噴鍍,且較佳係水平或垂直晶圓鍍覆。根據本發明,可對多種基板鍍覆含錫之沉積。待鍍覆之基板係導電性,且可包含銅、銅合金、鎳、鎳合金、含鎳-鐵之材質。此等基板可為電子元件之形式,如鉛框、連接器、晶片電容器、晶片電阻器及半導體封裝件;塑膠,
如電路板;以及半導體晶圓;且較佳係半導體晶圓。藉此,本發明亦提供一種於半導體晶圓上沉積含錫層的方法,係包含:提供包含複數個導電結合部分之半導體晶圓;令該半導體晶圓與上揭組成物接觸;以及,施用足夠之電流密度以於該等導電結合部分上沉積含錫層。較佳地,該等結合部分係包含銅,其係純銅層、銅合金層、或包含銅之任意互連結構的形式。銅導柱係一種較佳之導電結合部分。視需要,該等銅導柱可包含頂部金屬層,如鎳層。當該等導電結合部分具有頂部金屬層時,則該純錫焊料層係沉積於該結合部分之該頂部金屬層上。導電結合部分,如結合墊、銅導柱等,係該技藝中習知者,如第7,781,325號美國專利及第2008/0054459號、第2008/0296761號及第2006/0094226號美國專利公開申請案中揭示者。
本發明中,術語「半導體晶圓」係試圖涵蓋「電子裝置基板」、「半導體基板」、「半導體裝置」、及用於多種水準互連的各種封裝件,包括單晶片晶圓、多晶片晶圓、用於多種水準之封裝件、或需要焊料連結之其他組件。尤其適宜之基板係經圖案化之晶圓,如經圖案化之矽晶圓、經圖案化之藍寶石晶圓、及經圖案化之砷化鎵晶圓。此等晶圓可為任意適宜之尺寸。較佳之晶圓直徑係200mm至300mm,但亦可根據本發明適宜地採用具有更小及更大直徑之晶圓。本文中,術語「半導性晶圓」係包括具有一層或多層半導體層或結構之任意基板,其係包括半導體裝置之活性或可操作部分。術語「半導體基板」係定義為意
指包含半導性材質之任意構件,包括,但不限於,整體半導性材質如單獨之半導性晶圓或其上包含其他材質之組件形式的半導性晶圓,以及單獨之半導性材質層或包含其他材質之組件形式的半導性材質層。半導體裝置係指其上業經或即將批次加工至少一個微電子裝置的半導體基板。
欲以含錫層鍍覆基板,係令該基板與本發明之組成物接觸,以及施用一段時間之電流密度以將該含錫層沉積於該基板上。該接觸可藉由將待鍍覆之基板置於該鍍覆浴組成物中或將該鍍覆浴組成物泵浦至該基板上而實施。該基板係導電性且係陰極。該鍍覆浴係含有陽極,其可為可溶或不可溶。電勢典型係施用至該陰極。施用足夠之電流密度,且鍍覆係實施足夠之一段時間,以於該基板上沉積具有所欲厚度的含錫層。欲電鍍覆包含複數個結合部分之半導體晶圓係令該晶圓與本發明之鍍覆浴接觸,並對其施以一段時間之電流密度,以於該複數個結合部分上沉積含錫層。該半導體晶圓係作為陰極之功用。
用以沉積該含錫層之特定電流密度係取決於特定之鍍覆方法、待鍍覆之基板、以及待沉積者係純錫層或錫合金層。適宜之電流密度係自0.1至200A/dm2。該電流密度較佳係自0.5至100A/dm2,更佳自0.5至30A/dm2,甚至更佳自0.5至20A/dm2,且最佳2至20A/dm2。依賴於待鍍覆之特定結合部分以及彼等熟識該技藝者已知之其他顧慮,可使用其他電流密度。此電流密度之選擇係處於彼等熟識該技藝者的能力內。
可於10℃或更高之溫度,較佳於自10至65℃之範圍,更佳自15至40℃,沉積含錫層。通常,對於給定之溫度及電流密度,基板被鍍覆之時間愈長,則沉積愈厚;而時間愈短,則沉積愈薄。由是,可利用基板於鍍覆組成物中停留時間之長短以控制所得含錫沉積之厚度。通常,金屬沉積速率可高達15μm/min。典型地,沉積速率可為自0.5至15μm/min之範圍,且較佳係自1至10μm/min。
如上揭者,儘管本發明之電解質組成物可用於多種應用中,例示性應用仍為形成晶圓水準封裝用之互連凸點(焊料凸點)。本方法係包括:提供具有複數個導電結合部分(如互連凸點墊)之半導體晶片(die)(晶圓晶片);於該等結合部分上形成籽晶層;藉由令該半導體晶片與本發明之電鍍覆組成物接觸並令電流穿行通過該電鍍覆組成物,以於該基板上形成含錫互連凸點層,從而於該等結合部分上形成含錫凸點層;以及,再焊該互連凸點層以形成焊料凸點。該導電互連凸點墊可為一層或多層金屬、複合金屬或金屬合金,其典型係藉由物理氣相沉積(PVD)如濺射形成。典型之導電結合部分係包含,而不限於,鋁、銅、氮化鈦、及其等之合金。
鈍化層係形成於該等結合部分之上方,且藉由蝕刻製程,典型藉由乾蝕刻,於該鈍化層內部形成延伸至該等結合部分之開口。該鈍化層典型係絕緣金屬,例如,氮化矽、氧氮化矽、或氧化矽,如磷矽酸鹽玻璃。此
等材質可藉由化學氣相沉積(CVD)製程如電漿增強CVD沉積之。典型由複數層金屬或金屬合金層形成之凸點下金屬化(UBM)結構係沉積於該裝置之上方。該UBM係作為黏著層及用於作為待形成之互連凸點的電性接觸基質(籽晶層)。形成該UBM結構之層可藉由PVD製程如濺射或蒸發、或CVD製程沉積之。該UBM結構可為,舉例而言,依次包括底部鉻層、銅層、及上部錫層之複合結構,而不限於此。鎳係一種用於UBM應用之金屬。
通常,係將光阻層施用至半導體晶圓,之後進行標準光微影曝光及顯影技術以形成其內部具有開口或導孔(鍍覆導孔)的經圖案化之光阻層(或鍍覆罩)。該鍍覆罩之維度(該鍍覆罩之厚度及該圖案中開口之尺寸)係定義沉積於I/O墊及UBM上方之錫-銀層的尺寸及位置。此等沉積之直徑典型係自5至300μm之範圍,較佳係自10至150μm。此等沉積之高度典型係自10至150μm之範圍,較佳係自15至150μm,更佳係自20至80μm。適宜之光阻材質係可商購者(如自陶氏電子材料公司(Dow Electronic Materials,Marlborough,Massachusetts,USA)購得)且係該技藝中習知者。
互連凸點材質係藉由電鍍覆製程使用上揭之電鍍覆組成物沉積於該裝置上。互連凸點材質係包括,舉例而言,純錫或任意適宜之錫合金。例示性錫合金係上揭之彼等。此等合金亦可作為共熔組成物或任意其他適宜之組成物而使用。該凸點材質係電沉積於藉由該鍍覆導孔
界定之區域內。對於這一目標,典型係使用水平或垂直晶圓鍍覆系統如噴鍍(fountain plating)系統並採取直流或脈衝鍍覆技術。於該鍍覆製程中,該互連凸點材質係完全填充向上延伸之導孔以及該鍍覆罩上表面之一部分,得到蘑菇型金屬沉積。這確保沉積足夠體積之互連材質以於再焊後達成所欲之球形尺寸。於該導孔鍍覆製程中,該光阻係具有足夠之厚度,故適當體積之互連凸點材質係容納於該鍍覆罩導孔內。於鍍覆該互連凸點材質之前,可電沉積一層銅或鎳。該層可用於作為再焊時該互連凸點之可潤濕基底。
於該互連凸點材質之沉積後,使用適當之溶劑或其他移除器剝離該鍍覆罩。該等移除器係該技藝中習知者。隨後,使用已知技術選擇性蝕刻該UBM結構,自該等互連凸點之周邊及之間之區域移除全部金屬。
或者,於該光阻層中形成鍍覆導孔後,可將不含錫之金屬互連結構如導柱沉積於該等結合部分上。通常為銅導柱。典型地,該金屬沉積經常於鍍覆導孔被完全填充之前停止。隨後,可使用上揭電鍍覆組成物透過電鍍覆製程藉由含錫層將該等互連結構如銅導柱封端。該含錫層係電沉積於該鍍覆導孔所界定之區域內。對於這一目標,典型係使用水平或垂直晶圓鍍覆系統如噴鍍系統並採取直流或脈衝鍍覆技術。於鍍覆該含錫層之前,可將頂部金屬如鎳,電沉積於該銅導柱上方之鍍覆導孔內。該頂部金屬層可用於作為純錫焊料層之可潤濕基底,及/或提供阻
擋層。該含錫層之高度可為自20至50μm之範圍,但其他高度亦適宜,且係具有實質上與其上所沉積之互連結構相等的直徑。於該含錫焊料層之沉積之後,使用適當之溶劑或其他移除器剝離該鍍覆罩。該等移除器係該技藝中習知者。隨後,使用已知技術選擇性蝕刻該UBM結構,自該等互連凸點之周邊及之間之區域移除全部金屬。
隨後,視需要以焊劑處理該晶圓,並於再焊箱中加熱至該含錫焊料層熔化並流動為截形之實質上球形的溫度。加熱技術係該技藝中已知者,且係包括,舉例而言,紅外技術、傳導技術、對流技術、及其組合。經再焊之互連凸點通常係與該UBM結構之邊緣共延伸。該熱處理步驟可於惰性氣體氛圍或空氣中施行,且特定製程溫度及時間係取決於該互連凸點材質之特定組成。
當沉積(或鍍覆)時,自本發明之組成物電沉積之含錫焊料係實質上不具孔洞,此等焊料較佳係於一次再焊循環之後,較佳於重複之再焊循環如3次再焊循環之後,更佳於5次再焊循環之後,實質上不具孔洞者。適宜之再焊循環係使用來自Sikama International,Inc.之具有5個加熱區及2個冷卻區的Falcon 8500工具,使用條件為140/190/230/230/260℃溫度,30秒駐留時間,運載器速率約100cm/min,且氮氣流速為40立方呎/小時。Alpha 100-40助焊劑(Cookson Electronics,Jersey City,New Jersey,USA)係本再焊製程中使用之適宜助焊劑。本文中,術語「孔洞」係意指界面處孔洞及整體含錫層內之孔洞兩者。「實質上不
具孔洞」係意指,使用Cougar微焦X-射線系統(YXLON International GmbH,Hamburg,Germany)未見直徑大於3μm,較佳大於2μm,更佳大於1μm之孔洞。
對於確保元件適度結合至晶圓,焊料凸點之均勻性係關鍵。晶片內(WID)均勻性係習知用以測定給定晶片內,該含錫沉積之平均高度的均勻性。晶圓內(WIW)均勻性係習知用以測定,橫貫一半導體晶圓之該含錫沉積之平均高度的均勻性。使用本發明之組成物沉積於半導體晶圓上之含錫焊料係具有非常好的WID及WIW均勻性,此係以具有75μm直徑導孔、3種不同節距尺寸(150、225及375μm)、可鍍覆區域為3至20%、負性乾膜高度為75μm、及籽晶為1k Å Ti/3k Å Cu的經圖案化之晶圓測定。對於每一晶片,使用針式輪廓儀(KLA-Tencor P-15 Surface Profiler,Milpitas,California,USA)量測11個凸點之高度,以獲得WID均勻性(或共面性),其係藉由等式1計算之:
其中,hmax係晶片中最高之含錫凸點的高度,hmin係晶片中最矮之含錫凸點的高度,且havg係含錫焊料凸點之平均高度。共面性(或WID均勻性)值愈小,則該等含錫焊料凸點愈均勻。本發明之電鍍覆組成物係具有非常好的WID均勻性,其WID均勻性係5%,較佳3%。此等焊料沉積亦顯示非常好的WIW均勻性,其WIW均勻性係5%,較佳4.5%,甚至更佳4%。本發明之電鍍覆組成物亦提供鍍覆
過程具有相對平滑表面的含錫焊料沉積,亦即,鍍覆過程之表面係具有平均表面粗糙度(Ra)為200nm,較佳150nm,且甚至更佳100nm,該粗糙度係使用光學輪廓儀(Leica DCM3D,Leica Microsystems GmbH,Wetzlar,Germany)量測。
實施例1
藉由混合下述者而製備用於沉積錫-銀合金之電鍍覆組成物:75g/L之錫(來自甲磺酸錫)、0.65g/L之銀(來自甲磺酸銀)、104g/L之甲磺酸、5g/L之衍生自依序將EO與PO加至乙二胺之四官能嵌段共聚物(EO:PO約為40:60,Tetronic 90R4)作為非離子性界面活性劑、0.0166g/L之亞苄基丙酮作為第一細晶劑、0.1g/L之甲基丙烯酸作為第二細晶劑、0.6g/L之二硫烷基二醇作為第一銀錯合劑、3.1g/L之巰基四唑衍生物作為第二銀錯合劑、1.5g/L之醇溶劑、1g/L之商用抗氧化劑、及DI水(餘量)。該組成物之pH係<1。
將具有75μm(直徑)x 75μm(深度)之光阻圖案化導孔及銅籽晶層的4cm x 4cm晶圓片材浸沒於上揭電鍍覆組成物中,使用8A/dm2之電流密度鍍覆錫-銀凸點。該浴之溫度為25℃。使用不溶之鍍鉑鈦電極作為陽極。進行電鍍覆,直至鍍覆完成60μm之凸點。第1圖係所鍍覆之錫-銀焊料凸點的SEM。自第1圖可見,所得錫-銀焊料凸點沉積係平坦且具有平滑形貌。發現所鍍覆之晶圓片材鍍覆過程具有非常好的WID,其值為5%,且使用Leica
DCM3D光學輪廓儀量測之平均表面粗糙度為250nm。隨後,使用具有5個加熱區及2個冷卻區之Falcon 8500工具(Sikama International,Inc.)將該錫-銀焊料沉積再焊一次,再焊條件為140/190/230/230/260℃溫度、30秒駐留時間、運載器速率約100cm/min、且氮氣流速為40立方呎/小時。該焊料沉積係以Alpha 100-40助焊劑處理。使用Cougar微焦X-射線系統(YXLON International GmbH,Hamburg,Germany)評估經再焊之錫-銀沉積,發現其不具孔洞。
實施例2
藉由合併下述者製備用於沉積錫-銀之電鍍覆組成物:75g/L之錫(來自甲磺酸錫)、0.65g/L之銀(來自甲磺酸銀)、104g/L之甲磺酸、5g/L之衍生自依序將EO與PO加至乙二胺之四官能嵌段共聚物(EO:PO約為40:60,Tetronic 90R4)作為非離子性界面活性劑、0.0166g/L之亞苄基丙酮作為細晶劑、0.6g/L之二硫烷基二醇作為第一銀錯合劑、3.1g/L之巰基四唑衍生物作為第二銀錯合劑、1.5g/L之醇溶劑、1g/L之商用抗氧化劑、及DI水(餘量)。該組成物之pH係<1。根據實施例1之步驟,將具有75μm(直徑)x 75μm(深度)之光阻圖案化導孔及銅籽晶層的晶圓片材(4cm x 4cm)浸沒於該電鍍覆組成物中,並鍍覆錫-銀凸點。所得錫-銀焊料沉積係顯示類似之WID均勻性及形貌,並發現該等凸點於再焊後不具孔洞。
實施例3
藉由混合下述者而製備用於沉積純錫之電鍍覆組成
物:75g/L之錫(來自甲磺酸錫)、104g/L之甲磺酸、5g/L之衍生自依序將EO與PO加至乙二胺之四官能嵌段共聚物(EO:PO約為40:60,Tetronic 90R4)作為非離子性界面活性劑、0.0166g/L之亞苄基丙酮作為細晶劑、0.1g/L之甲基丙烯酸作為第二細晶劑、1.5g/L之醇溶劑、1g/L之商用抗氧化劑、及DI水(餘量)。該組成物之pH係<1。
將具有75μm(直徑)x75μm(深度)之光阻圖案化導孔及37μm高之預形成銅導柱的晶圓片材(4cmx4cm)浸沒於含有上揭組成物之電鍍槽(plating cell)中,並於8A/dm2電流密度鍍覆純錫層。該浴之溫度為25℃。使用不溶之鍍鉑鈦電極作為陽極,且該晶圓片材係陰極。進行電鍍覆,直至於銅導柱之頂部鍍覆完成高度為23μm的蘑菇狀錫蓋。所得錫層之形貌係使用Hitachi S2460TM掃描電子顯微鏡檢查之,發現其係均勻、平滑、緊緻、且不具結節。
實施例4
藉由重複實施例1之步驟並以表1中列述之金屬離子源替代銀離子源而製備多種錫合金電鍍覆組成物。
實施例5
藉由重複實施例1或實施例4之步驟並以表2中列述者替代非離子性界面活性劑及細晶劑而製備多種電鍍覆組成物。非離子性界面活性劑或為式3或為式4,其中,A=EO,而B=PO。
比較例1
藉由合併下述者而製備用於沉積錫-銀合金之電鍍覆組成物:75g/L之錫(來自甲磺酸錫)、0.5g/L之銀(來自甲磺酸銀)、140g/L之甲磺酸、5g/L之聚乙二醇α-(辛基)ω-(3-磺基丙基)二醚鉀鹽作為陰離子性界面活性劑(Ralufon EA 15-90,購自Raschig GmbH)、0.0166g/L之亞苄基丙酮作為細晶劑、2.3g/L之二硫烷基二醇作為銀錯合劑、1.5g/L之醇溶劑、1g/L之商用抗氧化劑、及DI水(餘量)。該組成物之pH係<1。此組成物不含有本發明之非離子性界面活性劑。根據實施例1之步驟,將具有75μm(直徑)x 75μm(深度)之光阻圖案化導孔及銅籽晶層的晶圓片材(4cm x 4cm)浸沒於該電鍍覆組成物中,並鍍覆錫-銀凸點。所得錫-銀焊料凸點沉積對於WID均勻性量測來說過於粗糙。第2圖係使用該電鍍覆組成物鍍覆之錫-銀焊料沉積的SEM。
比較例2
藉由合併下述者而製備用於沉積錫-銀合金之電鍍覆組成物:75g/L之錫(來自甲磺酸錫)、0.5g/L之銀(來自甲磺酸銀)、140g/L之甲磺酸、5g/L之衍生自依序將EO與PO加至乙二胺之四官能嵌段共聚物(EO:PO約為10:90,Tetronic 701)作為非離子性界面活性劑、0.05g/L之2’,3,4’,5,7-五羥基黃酮作為細晶劑、及2.3g/L之二硫烷基二醇作為銀錯合劑。該組成物之pH係<1。此組成物不含有本發明之細晶劑。根據實施例1之步驟,將具有75μm(直徑)x 75
μm(深度)之光阻圖案化導孔及銅籽晶層的晶圓片材(4cm x 4cm)浸沒於該電鍍覆組成物中,並鍍覆錫-銀凸點。所得錫-銀焊料凸點沉積顯示極差之WID均勻性(11%)。
比較例3
藉由合併下述者而製備用於沉積錫-銀合金之電鍍覆組成物:75g/L之錫(來自甲磺酸錫)、0.65g/L之銀(來自甲磺酸銀)、104g/L之甲磺酸、5g/L之衍生自依序將EO與PO加至乙二胺之四官能嵌段共聚物(EO:PO約為40:60,Tetronic 90R4)作為非離子性界面活性劑、0.6g/L之二硫烷基二醇作為第一銀錯合劑、3.1g/L之巰基四唑衍生物作為第二銀錯合劑、1.5g/L之醇溶劑、1g/L之商用抗氧化劑、及DI水(餘量)。該組成物之pH係<1。此組成物不含有細晶劑。根據實施例1之步驟,將具有75μm(直徑)x75μm(深度)之光阻圖案化導孔及銅籽晶層的晶圓片材(4cmx4cm)浸沒於該電鍍覆組成物中,並鍍覆錫-銀凸點。所得錫-銀焊料凸點沉積顯示極差之WID均勻性(12%)。
Claims (12)
- 一種用於將含錫層沉積於半導體晶圓上之電鍍覆組成物,包含:錫離子源;酸電解質;0.0001至0.075g/L之式(1)或(2)之一或多種細晶劑
- 如申請專利範圍第1項所述之電鍍覆組成物,其中,A 與B係獨立選自(C2-4)環氧烷。
- 如申請專利範圍第1項所述之電鍍覆組成物,其中,x與y係獨立為1至100之整數。
- 如申請專利範圍第1項所述之電鍍覆組成物,其中,該一或多種非離子性界面活性劑係具有平均分子量1000至30000。
- 如申請專利範圍第1項所述之電鍍覆組成物,另包含合金金屬離子源。
- 如申請專利範圍第5項所述之電鍍覆組成物,其中,該合金金屬離子源係選自銅離子、銀離子、金離子、鉍離子、鋅離子、銦離子、或其混合物。
- 如申請專利範圍第1項所述之電鍍覆組成物,其pH值為0至6。
- 如申請專利範圍第1項所述之電鍍覆組成物,其中,該細晶劑係選自肉桂酸、肉桂醛、亞苄基丙酮、2-吡啶甲酸、吡啶二甲酸、吡啶甲醛、吡啶二甲醛、或其混合物。
- 一種電鍍覆含錫層的方法,包含:提供包含複數個導電結合部分之半導體晶圓;令該半導體晶圓與含有下列成分之電鍍覆組成物接觸:錫離子源;酸電解質;0.0001至0.075g/L之式(1)或(2)之一或多種細晶劑
- 如申請專利範圍第9項所述之方法,其中,該細晶劑係選自肉桂酸、肉桂醛、亞苄基丙酮、2-吡啶甲酸、吡啶二甲酸、吡啶甲醛、吡啶二甲醛、或其混合物。
- 如申請專利範圍第9項所述的方法,其中,A與B係獨立選自(C2-4)環氧烷。
- 如申請專利範圍第9項所述的方法,其中,x與y係獨立為1至100之整數。
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US20160298249A1 (en) * | 2014-09-30 | 2016-10-13 | Rohm And Haas Electronic Materials Llc | Cyanide-free electroplating baths for white bronze based on copper (i) ions |
US9850588B2 (en) | 2015-09-09 | 2017-12-26 | Rohm And Haas Electronic Materials Llc | Bismuth electroplating baths and methods of electroplating bismuth on a substrate |
JP6210148B2 (ja) | 2015-12-28 | 2017-10-11 | 三菱マテリアル株式会社 | SnAg合金めっき液 |
EP3199666B1 (en) * | 2016-01-29 | 2018-09-26 | ATOTECH Deutschland GmbH | Aqueous indium or indium alloy plating bath and process for deposition of indium or an indium alloy |
JP6834070B2 (ja) | 2016-06-13 | 2021-02-24 | 石原ケミカル株式会社 | 電気スズ及びスズ合金メッキ浴、当該メッキ浴を用いて電着物を形成した電子部品の製造方法 |
US9809892B1 (en) * | 2016-07-18 | 2017-11-07 | Rohm And Haas Electronic Materials Llc | Indium electroplating compositions containing 1,10-phenanthroline compounds and methods of electroplating indium |
US10428436B2 (en) * | 2016-07-18 | 2019-10-01 | Rohm And Haas Electronic Materials Llc | Indium electroplating compositions containing amine compounds and methods of electroplating indium |
CN106757212B (zh) * | 2016-11-30 | 2018-02-02 | 昆山成功环保科技有限公司 | 用于晶圆级封装的电镀锡银合金溶液 |
CN110462108B (zh) * | 2017-03-27 | 2022-02-01 | 三菱综合材料株式会社 | 电镀液 |
JP6620859B2 (ja) * | 2017-10-24 | 2019-12-18 | 三菱マテリアル株式会社 | 錫又は錫合金めっき堆積層の形成方法 |
WO2019121092A1 (en) * | 2017-12-20 | 2019-06-27 | Basf Se | Composition for tin or tin alloy electroplating comprising suppressing agent |
US20190259722A1 (en) * | 2018-02-21 | 2019-08-22 | Rohm And Haas Electronic Materials Llc | Copper pillars having improved integrity and methods of making the same |
EP3781729A1 (en) | 2018-04-20 | 2021-02-24 | Basf Se | Composition for tin or tin alloy electroplating comprising suppressing agent |
WO2019239440A1 (en) * | 2018-06-15 | 2019-12-19 | Todescan Alberto | Electrolytic treatment process for coating stainless steel objects |
JP7070360B2 (ja) * | 2018-11-16 | 2022-05-18 | トヨタ自動車株式会社 | スズ膜形成用のスズ溶液、及びそれを用いたスズ膜の形成方法 |
KR102634250B1 (ko) * | 2018-12-27 | 2024-02-07 | 솔브레인 주식회사 | 도금 조성물 및 솔더 범프 형성 방법 |
CN111690958B (zh) * | 2019-03-15 | 2023-07-28 | 上海新阳半导体材料股份有限公司 | 一种锡镀液、其制备方法和应用 |
CN111321435B (zh) * | 2020-04-17 | 2022-03-01 | 广州鑫睿表面技术有限公司 | 一种酸性电镀锡液及其制备方法与应用 |
KR102617125B1 (ko) * | 2021-12-24 | 2023-12-27 | 주식회사 호진플라텍 | 저온 솔더를 위한 인듐-비스무스 합금용 전기 도금액 |
CN115029745A (zh) * | 2022-07-08 | 2022-09-09 | 云南锡业集团(控股)有限责任公司研发中心 | 一种可减少元件镀层工艺步骤并提升焊点可靠性的方法 |
CN115636695B (zh) * | 2022-12-21 | 2023-04-18 | 四川科尔威光电科技有限公司 | 一种半导体氮化铝陶瓷预置金锡焊料热沉的制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200422439A (en) * | 2003-01-24 | 2004-11-01 | Ishihara Chemical Co Ltd | Tin-containing plating bath |
TW201006966A (en) * | 2008-06-12 | 2010-02-16 | Rohm & Haas Elect Mat | Electrolytic tin plating solution and electrolytic tin plating method |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4072582A (en) * | 1976-12-27 | 1978-02-07 | Columbia Chemical Corporation | Aqueous acid plating bath and additives for producing bright electrodeposits of tin |
US4139425A (en) * | 1978-04-05 | 1979-02-13 | R. O. Hull & Company, Inc. | Composition, plating bath, and method for electroplating tin and/or lead |
US4871429A (en) | 1981-09-11 | 1989-10-03 | Learonal, Inc | Limiting tin sludge formation in tin or tin/lead electroplating solutions |
JPS61117297A (ja) * | 1984-11-13 | 1986-06-04 | Ebara Yuujiraito Kk | スズ属金属めつき液 |
US4582576A (en) * | 1985-03-26 | 1986-04-15 | Mcgean-Rohco, Inc. | Plating bath and method for electroplating tin and/or lead |
US5174887A (en) | 1987-12-10 | 1992-12-29 | Learonal, Inc. | High speed electroplating of tinplate |
JP2856857B2 (ja) * | 1990-07-27 | 1999-02-10 | 石原薬品株式会社 | 錫、鉛または錫―鉛合金めっき浴 |
US5282954A (en) * | 1991-12-30 | 1994-02-01 | Atotech Usa, Inc. | Alkoxylated diamine surfactants in high-speed tin plating |
JP3538499B2 (ja) * | 1996-05-15 | 2004-06-14 | 株式会社大和化成研究所 | 錫−銀合金電気めっき浴 |
JP4362568B2 (ja) * | 2000-06-02 | 2009-11-11 | 奥野製薬工業株式会社 | 錫−銅合金電気めっき液 |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
TWI245402B (en) | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US7314543B2 (en) | 2003-10-14 | 2008-01-01 | Intel Corporation | Tin deposition |
TWI254995B (en) * | 2004-01-30 | 2006-05-11 | Phoenix Prec Technology Corp | Presolder structure formed on semiconductor package substrate and method for fabricating the same |
TWI240979B (en) | 2004-10-28 | 2005-10-01 | Advanced Semiconductor Eng | Bumping process |
KR100921919B1 (ko) | 2007-11-16 | 2009-10-16 | (주)화백엔지니어링 | 반도체 칩에 형성되는 구리기둥-주석범프 및 그의 형성방법 |
CN102187749A (zh) * | 2008-10-21 | 2011-09-14 | 埃托特克德国有限公司 | 用于在衬底上形成焊料沉积物的方法 |
JP5410201B2 (ja) * | 2009-08-26 | 2014-02-05 | 三菱伸銅株式会社 | 銅合金板への高電流密度Snめっき用硫酸浴及びSnめっき方法 |
JP5033979B1 (ja) * | 2011-09-29 | 2012-09-26 | ユケン工業株式会社 | スズからなるめっき用酸性水系組成物 |
US8888984B2 (en) * | 2012-02-09 | 2014-11-18 | Rohm And Haas Electronic Materials Llc | Plating bath and method |
-
2013
- 2013-11-05 US US14/071,679 patent/US20150122662A1/en not_active Abandoned
-
2014
- 2014-11-05 JP JP2014224806A patent/JP6482822B2/ja active Active
- 2014-11-05 CN CN201410858387.4A patent/CN104674311A/zh active Pending
- 2014-11-05 EP EP14191883.9A patent/EP2868778B1/en active Active
- 2014-11-05 TW TW103138321A patent/TWI548781B/zh active
- 2014-11-05 KR KR1020140153178A patent/KR102454558B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200422439A (en) * | 2003-01-24 | 2004-11-01 | Ishihara Chemical Co Ltd | Tin-containing plating bath |
TW201006966A (en) * | 2008-06-12 | 2010-02-16 | Rohm & Haas Elect Mat | Electrolytic tin plating solution and electrolytic tin plating method |
Also Published As
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JP6482822B2 (ja) | 2019-03-13 |
EP2868778A3 (en) | 2015-08-12 |
CN104674311A (zh) | 2015-06-03 |
KR102454558B1 (ko) | 2022-10-13 |
EP2868778B1 (en) | 2023-05-31 |
TW201522720A (zh) | 2015-06-16 |
EP2868778A2 (en) | 2015-05-06 |
KR20150051927A (ko) | 2015-05-13 |
US20150122662A1 (en) | 2015-05-07 |
JP2015092022A (ja) | 2015-05-14 |
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