TWI520232B - 具有經封包之通孔的積體電路封裝系統及其製造方法 - Google Patents

具有經封包之通孔的積體電路封裝系統及其製造方法 Download PDF

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TWI520232B
TWI520232B TW099130277A TW99130277A TWI520232B TW I520232 B TWI520232 B TW I520232B TW 099130277 A TW099130277 A TW 099130277A TW 99130277 A TW99130277 A TW 99130277A TW I520232 B TWI520232 B TW I520232B
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integrated circuit
substrate
package
interposer
buffer
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TW099130277A
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TW201118964A (en
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趙南柱
池熺朝
申翰佶
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星科金朋有限公司
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description

具有經封包之通孔的積體電路封裝系統及其製造方法
本發明一般而言係關於一種積體電路封裝系統，而詳而言之，係關於一種用於具有通孔之積體電路封裝系統的系統。
組件微縮化的增進、更大的積體電路(“IC”)封裝密度、更高的效能以及更低的成本係電腦工業不斷追求的目標。半導體封裝件結構持續朝向微縮化邁進，以增進封裝件中所封裝之組件密度，同時縮減採用該等半導體封裝件結構之產品的尺寸。此係回應對於資訊與通訊產品之尺寸、厚度、及成本不斷縮減與效能不斷增進的持續需求。
例如，於可攜式資訊與通訊裝置(如行動電話、免持式行動電話耳機、個人數位助理(“PDA”)、攝錄影機、筆記型電腦等)中這些微縮化的持續需求更為顯著。所有這些裝置持續被製造成更小且更薄以改善其可攜性。因此，結合至這些裝置中的大型積體電路(“LSI”)封裝件必須被製造成更小且更薄。用以罩蓋並保護LSI的封裝件組構亦必須被製造成更小且更薄。
許多習知的半導體(或“晶片”)封裝件是將半導體晶粒以樹脂(如環氧模製化合物)模製入封裝件中的形式。許多的封裝件方法係堆疊多個積體電路晶粒或封裝件中封裝件(package in package；PIP)或其組合。其他的封裝件方法包含封裝件層次堆疊或封裝件上封裝件(package-on-package；POP)。封裝件上封裝件(POP)設計存在有可靠度方面的挑戰與成本較高的問題。
因此，對於積體電路封裝系統提供低製造成本、經改善之良率、輕薄外形、及經改善之可靠度的需求仍然存在。有鑑於節省成本與改善效率的需求不斷增加，找出這些問題的答案顯得更加關鍵。
這些問題的解決方案已經過長期探究，但先前的研究發展皆未能提供任何教示或建議的解決方案，因此這些問題的解決方案長期以來已困擾著本技術領域中具有通常知識者。
本發明提供一種積體電路封裝系統之製造方法，包含：設置基板；於該基板上方接置積體電路；將緩衝互連件附接至該基板且附接於該基板上方；於該基板上方形成封包，該封包覆蓋該緩衝互連件與該積體電路；以及，於該封包中形成通孔並且達至該緩衝互連件。
本發明提供一種積體電路封裝系統，包含：基板；積體電路，係位於該基板上方；緩衝互連件，係附接至該基板且附接於該基板上方；通孔，係連接至該緩衝互連件；以及，封包，係位於該基板上方，該封包覆蓋該通孔、該緩衝互連件、與該積體電路，並曝露出該通孔。
本發明之某些實施例具有除了上述步驟或元件以外或者替代上述步驟或元件之其他步驟或元件。當參酌附加圖式作為參考時，本技術領域中具有通常知識者將經由閱讀以下詳述之說明書內容而清楚明瞭該等步驟或元件。
以下實施例係經充分詳細描述以使得本技術領域中具有通常知識者能夠製造並使用本發明。將了解到，基於本發明之揭露內容，其他實施例將變得清楚明瞭，並且可於不背離本發明範疇的前提下進行系統、製程、或機構上的改變。
於以下說明書中，給定許多特定細節，以提供對於本發明的通透了解。然而，將體認到本發明可於缺少這些特定細節的前提下實現。為了避免混淆本發明，一些眾所熟知的電路、系統組構、以及製程步驟並未詳細揭露。同樣地，顯示該系統之實施例的圖式係半概略且未依實際尺寸描繪，更詳而言之，一些尺寸係為了清楚呈現並以誇張的尺寸顯示於該等圖式中。一般而言，本發明可操作於任何定向。
此外，於本說明書中所揭露與描述的多個實施例具有一些共同特徵，為了清楚並容易說明、描述及理解本發明，互相類似或相同的特徵通常將以相同的參考編號描述。為了方便描述，該等實施例已編號為第一實施例、第二實施例等，而並非意圖具有任何其他含意或限制本發明。
為了說明的目的，於本說明書中所使用的用語“水平的(horizontal)”係定義為平行於該積體電路的平面或表面的平面，而與其定向無關。該用語“垂直的(vertical)”係與垂直於先前所定義之水平的方向。如圖所示，如“在...之上(above)”、“在…之下(below)”、“底部(bottom)”、“頂部(top)”、“側邊(side)”(如同“側壁(sidewall)”)、“較高的(higher)”、“下側的(lower)”、“上側的(upper)”、“在…上方(over)”、以及“在…下方(under)”等用語係相對於水平平面而定義。
名詞“在…上(on)”意指元件之間有直接接觸。如本說明書中所使用之用語“製程(processing)”包含材料沉積、圖案化(patterning)、曝光(exposure)、顯影(development)、蝕刻、清潔、模製(molding)及/或移除材料或如形成上述結構所需者。
現在請參照第1圖，係顯示本發明第一實施例中積體電路封裝系統100之頂視圖。該頂視圖描繪沿著封包(encapsulation)104(如由環氧模製化合物、可貫穿的封包材料(penetrable encapsulation material)、或薄膜中導線(wire in film)所形成之封包)周圍(periphery)之通孔102(如導電通道(conductive channel)或導電栓(conductive plug))。
為了說明的目的，儘管了解該積體電路封裝系統100可具有不同的通孔102組構，但所示之積體電路封裝系統100具有沿著該封包104之周圍部分之通孔102。舉例而言，該等通孔102可放置成朝向或放置於該封包104之中央部分處，或者可沿著該積體電路封裝系統100之所有側邊放置。
該等通孔102可以一些不同的方法形成。舉例而言，可藉由通孔形成製程(未圖示)(如雷射燒蝕(laser-ablating)或機械鑽孔(mechanical drilling))隨後接著間隙填充製程(如銲錫球挑選與落下(pick and dropping)、銲錫膏網印(screen printing)、或銅電鍍)而形成該等通孔102。
已經發現到，為了將積體電路封裝系統堆疊於彼此的頂部上，期望具有穿透積體電路封裝系統之封包的通孔。然而，已經發現到，該通孔形成製程會導致可負面影響該積體電路封裝系統之效能、良率、及可靠度的損害。舉例而言，於採用雷射燒蝕之通孔形成製程之情況下，光強度變異(light intensity variation)經常會損害位於該等通孔基底(base)處之積體電路封裝系統下面的組件。如同進一步的範例，於採用機械鑽孔之通孔形成製程之情況下，鑽頭高度控制或基板厚度變異將對下面的層造成損害。
現在請參照第2圖，係顯示積體電路封裝系統100沿著第1圖之線段2--2之剖面圖。該剖面圖描繪基板206，如導線架(lead frame)、以長條為基礎的薄板(strip based laminate)、帶狀物(tape)、嵌入式晶粒基板、或穿透矽通孔(through-silicon via)。該基板206可包含基板第一側208與基板第二側210。接點墊片219可自該基板第一側208曝露出來。外部互連件212(如銲錫球、導電凸塊(conductive bump)、或導電柱(conductive post))可附接至該基板第二側210。
積體電路214(如積體電路晶粒、或覆晶(flip chip))可設置於該基板第一側208上方。內部互連件216(如接合導線、引線接合導線(ribbon bond wire)、或銲錫球)可連接該積體電路214與該基板第一側208。
該積體電路214與該基板206可能為被該通孔形成製程所損害之積體電路封裝系統下面的組件之範例。舉例而言，雷射燒蝕或機械鑽孔可能損害該接點墊片219並且中斷該基板206中之電性連接。機械鑽孔需要精確的鑽孔高度控制，否則該機械應力不但可能損害該等接點墊片219，也可能造成破裂、翹曲及其他缺陷。
緩衝互連件218(如銲錫球、銲錫柱、銅柱、或導電圓柱(conductive column))係附接至該等接點墊片219。該等緩衝互連件218係於製造製程期間保護該基板206免於受到損害之實體緩衝(physical buffer)。舉例而言，該等緩衝互連件218藉由作為對該基板206之實體阻障(physical barrier)而於該等通孔102之形成期間避免對該基板206造成損害。
該封包104可形成於該基板第一側208上方，覆蓋該等緩衝互連件218、該等內部互連件216、及該積體電路214。該等通孔102可形成於該封包104中。該等通孔102可自封包頂部側220延伸穿透該封包104，並且連接至該等緩衝互連件218。自該封包104所曝露出來之該等通孔102的部分可與該封包頂部側220成平面。
為了說明的目的，如圖所示之積體電路封裝系統100具有附接至該等接點墊片219之緩衝互連件218，然而，應了解到，該等通孔102可以不同方式進行連接，而該等緩衝互連件218可以不同方式進行附接。舉例而言，該等緩衝互連件218可附接至該積體電路214並附接於該積體電路214上方。此外，該等通孔102可形成為自該封包頂部側220延伸穿透該封包104，並且與附接至該積體電路214之緩衝互連件218相連接。
已進一步發現到，於該等通孔102之底部處設置實體阻障或緩衝係將於該通孔形成製程期間避免造成損害，而緩衝互連件218(如銲錫球、銲錫柱、銅柱、或導電圓柱)可於該通孔形成製程期間避免損害。該等緩衝互連件218提供穩定的緩衝，其降低對於雷射燒蝕中光強度變異與機械鑽孔中鑽頭高度控制或基板厚度變異的製造敏感度(sensitivity)。
亦已發現到，該緩衝互連件218亦藉由提供較淺的通孔深度而縮減製程時間與成本。該等緩衝互連件218排除了對於通孔102延伸至該基板206之需求，藉此縮減該等通孔102之深度。
因此，包含該等緩衝互連件218係增加可靠度、改善良率、以及降低成本，同時利用較寬的製程視窗(process window)提供較簡易的製程控制。
現在請參照第3圖，係顯示本發明第二實施例中積體電路封裝系統300之頂視圖。該頂視圖描繪了內插件(interposer)324，如以長條或片段為基礎的薄板、帶狀物、或導線架。該內插件324包含內插件第一側326。接置墊片328(如接點墊片或終端墊片)可自該內插件第一側326曝露出來。
通孔302(如導電通道或導電栓)可自該內插件第一側326曝露出來，並且可沿著該內插件第一側326的周圍。儘管應了解到該等通孔302可不必沿著該內插件324之周圍部分，但為了說明的目的，所示之積體電路封裝系統300具有沿著該內插件324之周圍部分之通孔302。舉例而言，該等通孔302可放置成朝向或放置於該內插件324之中央部分處。
再者，儘管應了解到該積體電路封裝系統300可具有不同組態的接置墊片328，但為了說明的目的，所示之積體電路封裝系統300具有位於該內插件324之兩側周圍處之接置墊片328。舉例而言，除了沿著兩個相對側以外，該等接置墊片328亦可沿著該內插件324的不同周圍部分。
現在請參照第4圖，係顯示該積體電路封裝系統300沿著第3圖之線段4--4之剖面圖。該剖面圖描繪具有基板第一側408與基板第二側410之基板406(如以長條為基礎的薄板、帶狀物、嵌入式晶粒基板、或穿透矽通孔)。外部互連件412(如銲錫球或導電柱)可附接至該基板第二側410。
積體電路414(如積體電路晶粒或覆晶)可接置於該基板第一側408上方。內部互連件416(如接合導線、引線接合導線、或銲錫球)可連接該積體電路414與該基板第一側408。
緩衝互連件418(如銲錫球、銲錫柱、銅板柱、或導電凸塊)係附接至該基板第一側408。該等緩衝互連件418係於該製造製程期間保護該基板406免於受到損害之實體緩衝。舉例而言，該等緩衝互連件418避免於該等通孔302之形成期間對該基板406造成損害。該等緩衝互連件418係附接至該基板第一側408之接點墊片419。
封包404(如由環氧模製化合物、可貫穿的封包材料、或薄膜中導線所形成之封包)可形成於該基板第一側408上方，覆蓋該等緩衝互連件418、該積體電路414、以及該等內部互連件416。該內插件324可位於封包404、該基板第一側408、該等內部互連件416、該等緩衝互連件418、及該積體電路414的上方。該內插件324可包含面向封包404之內插件第二側430。
該封包404可以多種方式形成。舉例而言，藉由將該內插件324懸掛(suspend)於該基板第一側408、該等內部互連件416、該等緩衝互連件418、及該積體電路414上方，該內插件324可設置於該基板406上方。藉由透過頂部模套(mold chase)(未圖示)以真空承托該內插件324可達到上述之懸掛。可藉由在該內插件324與該基板406之間流入或注入模製化合物(molding compound)而形成該封包404。該基板406可由底部模套(未圖示)所支撐。
該等通孔302可形成為穿透該等內插件324並形成於該封包404中。該等通孔302可自該內插件第一側326延伸連接至該等緩衝互連件418。自該內插件第一側326所曝露出來之該等通孔302的部分可與該內插件第一側326成平面。
為了說明的目的，所示之積體電路封裝系統300具有附接至該基板第一側408之緩衝互連件418，然而，應了解到，該等通孔302可以不同方式進行連接，而該等緩衝互連件418可以不同方式進行附接。舉例而言，該等緩衝互連件418可附接至該積體電路414並附接於該積體電路414上方。此外，可形成該等通孔302以自該內插件第一側326延伸，並且與附接至該積體電路414之緩衝互連件418相連接。
該等通孔302可以多種方式形成。舉例而言，通道421可利用鑽孔製程(如雷射燒蝕或機械鑽孔)而形成為穿透該內插件324、形成於該封包404中、並達至該緩衝互連件418。可藉由間隙填充製程(如銲錫球挑選與落下、銲錫膏網印、或銅電鍍)形成該等通孔302。
已進一步發現到，本發明提供了具有緊密互連機制之積體電路封裝系統。該內插件可提供接置並重新分配至該積體電路封裝系統。穿透該內插件的通孔自該內插件提供緊密的連接至該積體電路封裝系統之其餘部分。
現在請參照第5圖，係顯示本發明第三實施例中積體電路封裝系統500之頂視圖。該頂視圖描繪內堆疊模組(interstack module)532。該內堆疊模組532可包含具有內插件第一側526之內插件524(如以長條或片段為基礎的薄板、帶狀物、或導線架)。該內堆疊模組532亦可包含接置於該內插件第一側526上方經封裝的積體電路536(如經封包之積體電路晶粒或經封包之覆晶)。
通孔502(如導電通道或導電栓)可自該內插件第一側526曝露出來，並且可沿著該內插件第一側526的周圍。儘管應了解到該等通孔502可不必沿著該內插件524之周圍部分，但為了說明的目的，所示之積體電路封裝系統500具有沿著該內插件524之周圍部的之通孔502。舉例而言，該等通孔502可放置成朝向或放置於該內插件524之中央部分處。
現在請參照第6圖，係顯示該積體電路封裝系統500沿著第5圖之線段6--6之剖面圖。該剖面圖描繪具有基板第一側608與基板第二側610之基板606(如以長條為基礎的薄板、帶狀物、嵌入式晶粒基板、或穿透矽通孔)。外部互連件612(如銲錫球或導電柱)可附接至該基板第二側610。
積體電路614(如積體電路晶粒或覆晶)可接置於該基板第一側608上方。內部互連件616(如接合導線、引線接合導線、或銲錫球)可連接該積體電路614與該基板第一側608。
緩衝互連件618(如銲錫球、銲錫柱、銅板柱、或導電凸塊)係附接至該基板第一側608。該等緩衝互連件618係於該製造製程期間保護該基板606免於受到損害之實體緩衝。舉例而言，該等緩衝互連件618避免於該等通孔502之形成期間對該基板606造成損害。該等緩衝互連件618係附接至該基板第一側608之接點墊片619。
封包604(如由環氧模製化合物、可貫穿的封包材料、或薄膜中導線所形成之封包)可形成於該基板第一側608與內插件第二側630之間，覆蓋該等緩衝互連件618與該積體電路614。該內插件524可位於該基板第一側608、該等內部互連件616、該等緩衝互連件618、及該積體電路614的上方。
該封包604可以多種方式形成。舉例而言，藉由將該內堆疊模組532懸掛於該基板第一側608、該等內部互連件616、該等緩衝互連件618、及該積體電路614上方，該內堆疊模組532可設置於該基板606上方。藉由透過頂部模套以真空承托該內堆疊模組532可達到上述之懸掛。可藉由在該內堆疊模組532與該基板606之間流入或注入模製化合物而形成該封包604。該基板606可由底部模套(未圖示)所支撐。如進一步範例，可利用該頂部模套形成該封包604，而無須將該內堆疊模組532懸掛或承托於該基板606上方。在形成該封包604之後，該內堆疊模組532可接置於該封包604上方。
該等通孔502可形成為穿透該內堆疊模組532之內插件524並形成於該封包604中。該等通孔502可自該內插件第一側526延伸、並於該封包604中延伸，連接至該等緩衝互連件618。自該內插件第一側526所曝露出來之該等通孔502的部分可與該內插件第一側526成平面。
為了說明的目的，所示之積體電路封裝系統500具有附接至該基板第一側608之緩衝互連件618，然而，應了解到，該等通孔502可以不同方式進行連接，而該等緩衝互連件618可以不同方式進行附接。舉例而言，該等緩衝互連件618可附接至該積體電路614並附接於該積體電路614上方。此外，可形成該等通孔502以自該內插件第一側526延伸，並且與附接至該積體電路614之緩衝互連件618相連接。
該等通孔502可以多種方式形成。舉例而言，通道621可利用鑽孔製程(未圖示)(如雷射燒蝕或機械鑽孔)而形成為穿透該內插件524、形成於該封包604中、並達至該緩衝互連件618。可藉由間隙填充製程(未圖示)(如銲錫球挑選與落下、銲錫膏網印、或銅電鍍)形成該等通孔502。
現在請參照第7圖，係顯示本發明第四實施例中封裝件上封裝件系統700之頂視圖。該頂視圖描繪可接置結構740，如經封裝之積體電路、覆晶、被動組件、第1圖之積體電路封裝系統100、第3圖之積體電路封裝系統300、或者第5圖之積體電路封裝系統500。
儘管應了解到該封裝件上封裝件系統700可具有不同的形狀，但為了說明的目的，所示之封裝件上封裝件系統700具有方形的幾何形狀。舉例而言，該封裝件上封裝件系統700可具有矩形的形狀。
現在請參照第8圖，係顯示封裝件上封裝件系統700沿著第7圖之線段8--8之剖面圖。該剖面圖描繪接置於第1圖之積體電路封裝系統100上方之可接置結構740。該可接置結構740可接置於該封包104上方。如銲錫球之接置互連件842可連接該可接置結構740與該等通孔102。
儘管應了解到該封裝件上封裝件系統700可具有不同的組構，但為了說明的目的，所示之封裝件上封裝件系統700具有接置於該積體電路封裝系統100上方之可接置結構740。舉例而言，該可接置結構740可接置於第3圖之積體電路封裝系統300或者第5圖之積體電路封裝系統500的上方。
現在請參照第9圖，係顯示本發明第五實施例中封裝件上封裝件系統900沿著第7圖之線段8--8之剖面圖。該剖面圖描繪基底結構944，如扇入(fan-in)封裝件上封裝件、扇出(fan-out)封裝件上封裝件、第1圖之積體電路封裝系統100、第3圖之積體電路封裝系統300、或者第5圖之積體電路封裝系統500。第1圖之積體電路封裝系統100可接置於該基底結構944上方。
可接置結構940(如經封裝之積體電路、覆晶、被動組件、該積體電路封裝系統100、該積體電路封裝系統300、或者該積體電路封裝系統500)可接置於該積體電路封裝系統100上方。該可接置結構940可接置於該封包104上方。接置互連件942可連接該可接置結構940與該等通孔102。
儘管應了解到該封裝件上封裝件系統900可具有不同的組構，但為了說明的目的，所示之封裝件上封裝件系統900具有接置於該基底結構944上方之積體電路封裝系統100，而該可接置結構940接置於該積體電路封裝系統100上方。舉例而言，該積體電路封裝系統300或該積體電路封裝系統500可接置於該基底結構944上方，而該可接置結構940可接置於該積體電路封裝系統300或者該積體電路封裝系統500的上方。
現在請參照第10圖，係顯示第3圖之積體電路封裝系統300於形成該封包404時之剖面圖。所示之積體電路封裝系統300不具有第4圖之外部互連件412或者第4圖之通孔302。於接下來的製程中，該等外部互連件412可附接至該基板第二側410。
該封包404可以多種方式形成。舉例而言，藉由將該內插件324懸掛於該基板第一側408、該等內部互連件416、該等緩衝互連件418、及該積體電路414上方，該內插件324可設置於該基板406上方。藉由透過具有真空孔1048之頂部模套1046以真空承托該內插件324可達到上述之懸掛。可藉由在該內插件324與該基板406之間流入或注入模製化合物而形成該封包404。該基板406可由底部模套1050所支撐。
如另一範例，該封包404可形成有可貫穿的封包材料，如薄膜中導線(wire-in-film)。該封包404可預先附接至該內插件324之底部。該頂部模套1046可承托該內插件324，該內插件324附接有該封包404。該頂部模套1046可將該封包404推壓至圍繞該等內部互連件416、該等緩衝互連件418、及該積體電路414的基板406。
現在請參照第11圖，係顯示本發明進一步實施例中積體電路封裝系統之製造方法1100的流程圖。該方法包含：於步驟方塊1102中，設置基板；於步驟方塊1104中，於該基板上方接置積體電路；於步驟方塊1106中，將緩衝互連件附接至該基板且附接於該基板上方；於步驟方塊1108中，於該基板上方形成封包，該封包覆蓋該緩衝互連件與該積體電路；以及，於步驟方塊1110中，於該封包中形成通孔並且達至該緩衝互連件。
本發明之另一個重要的態樣係有利地支持並有助於降低成本、簡化系統、及增進效能的長期趨勢。
因此，本發明的這些與其他有利態樣將技術狀態進一步推進至至少下一個層次。
儘管已經結合特定最佳模式對本發明進行描述，但應了解，對於本技術領域中具有通常知識者而言，按照先前說明書內容對本發明作出許多替代、修改及變更將是明顯的。因此，欲強調對於本發明的所有替代、修改及變更皆落於本說明書所附加之申請專利範圍的範疇內。本說明書中所提及的或圖式中所示的所有內容皆為說明而非限制本發明。
2--2、4--4、6--6、8--8．．．線段
100、300、500．．．積體電路封裝系統
102、302、502．．．通孔
104、404、604．．．封包
206、406、606．．．基板
208、408、608．．．基板第一側
210、410、610．．．基板第二側
212、412、612．．．外部互連件
214、414、614．．．積體電路
216、416、616．．．內部互連件
218、418、618．．．緩衝互連件
219、419、619．．．接點墊片
220．．．封包頂部側
324、524．．．內插件
326、526．．．內插件第一側
328．．．接置墊片
421、621．．．通道
430、630．．．內插件第二側
532．．．內堆疊模組
536．．．經封裝的積體電路
700、900．．．封裝件上封裝件系統
740、940．．．可接置結構
842、942．．．接置互連件
944．．．基底結構
1046．．．頂部模套
1048．．．真空孔
1050．．．底部模套
1100．．．方法
1102、1104、1106、1108、1110．．．步驟方塊
第1圖係本發明第一實施例中積體電路封裝系統之頂視圖；
第2圖係積體電路封裝系統沿著第1圖之線段2--2之剖面圖；
第3圖係本發明第二實施例中積體電路封裝系統之頂視圖；
第4圖係積體電路封裝系統沿著第3圖之線段4--4之剖面圖；
第5圖係本發明第三實施例中積體電路封裝系統之頂視圖；
第6圖係積體電路封裝系統沿著第5圖之線段6--6之剖面圖；
第7圖係本發明第四實施例中封裝件上封裝件系統之頂視圖；
第8圖係封裝件上封裝件系統沿著第7圖之線段8--8之剖面圖；
第9圖係本發明第五實施例中封裝件上封裝件系統沿著第7圖之線段8--8之剖面圖；
第10圖係第3圖之積體電路封裝系統於形成該封包時之剖面圖；以及
第11圖係本發明進一步實施例中積體電路封裝系統之製造方法的流程圖。
100．．．積體電路封裝系統
102．．．通孔
104．．．封包
206．．．基板
208．．．基板第一側
210．．．基板第二側
212．．．外部互連件
214．．．積體電路
216．．．內部互連件
218．．．緩衝互連件
219．．．接點墊片
220．．．封包頂部側

Claims (7)

  1. 一種用於形成積體電路封裝系統之製造方法，包括：設置基板；於該基板上方接置積體電路；將緩衝互連件附接至該基板且附接於該基板上方；於該基板上方形成封包，該封包覆蓋該緩衝互連件與該積體電路；於該封包中形成通孔並且達至該緩衝互連件；以及於該基板上方設置內插件；其中：形成該封包包含將該封包預先附接至該內插件；以及形成該通孔包含形成穿透該內插件之該通孔，以從該內插件之頂表面曝露該通孔。
  2. 如申請專利範圍第1項所述之方法，復包括：於該封包上方接置內插件；以及其中：形成該通孔包含形成穿透該內插件之該通孔。
  3. 如申請專利範圍第1項所述之方法，復包括：內堆疊模組，該內堆疊模組具有內插件且位於該封包上方；以及其中：形成該通孔包含形成穿透該內插件之該通孔。
  4. 如申請專利範圍第1項所述之方法，復包括： 將該緩衝互連件附接至該積體電路且附接於該積體電路上方；以及其中，形成該通孔包含於該封包中形成該通孔並且達至附接至該積體電路之該緩衝互連件。
  5. 一種積體電路封裝系統，包括：基板；積體電路，係位於該基板上方；緩衝互連件，係附接至該基板且附接於該基板上方；通孔，係連接至該緩衝互連件；以及封包，係位於該基板上方，該封包覆蓋該緩衝互連件、與該積體電路，且該通孔穿透該封包並自該封包曝露出；內堆疊模組，該內堆疊模組具有內插件且位於該封包上方，其中，該通孔穿透該內插件，以從該內插件之頂表面曝露該通孔。
  6. 如申請專利範圍第5項所述之系統，其中，該緩衝互連件係附接至該積體電路且附接於該積體電路上方。
  7. 如申請專利範圍第5項所述之系統，其中，該通孔之頂面部分係與該封包之封包頂部側成共平面。
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