TWI486964B - 高效能快閃記憶體資料傳送方法及裝置 - Google Patents
高效能快閃記憶體資料傳送方法及裝置 Download PDFInfo
- Publication number
- TWI486964B TWI486964B TW096114457A TW96114457A TWI486964B TW I486964 B TWI486964 B TW I486964B TW 096114457 A TW096114457 A TW 096114457A TW 96114457 A TW96114457 A TW 96114457A TW I486964 B TWI486964 B TW I486964B
- Authority
- TW
- Taiwan
- Prior art keywords
- data
- controller
- flash memory
- input
- mode
- Prior art date
Links
- 238000012546 transfer Methods 0.000 title claims description 241
- 230000015654 memory Effects 0.000 title claims description 179
- 238000000034 method Methods 0.000 title claims description 50
- 230000006854 communication Effects 0.000 claims description 72
- 238000004891 communication Methods 0.000 claims description 72
- 230000007704 transition Effects 0.000 claims description 41
- 230000004044 response Effects 0.000 claims description 26
- 230000005540 biological transmission Effects 0.000 claims description 16
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 1
- 240000007320 Pinus strobus Species 0.000 description 64
- 238000012545 processing Methods 0.000 description 27
- 230000000630 rising effect Effects 0.000 description 27
- 230000008569 process Effects 0.000 description 23
- 230000001360 synchronised effect Effects 0.000 description 20
- 239000000463 material Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 11
- 239000004020 conductor Substances 0.000 description 10
- UEKHZPDUBLCUHN-UHFFFAOYSA-N 2-[[3,5,5-trimethyl-6-[2-(2-methylprop-2-enoyloxy)ethoxycarbonylamino]hexyl]carbamoyloxy]ethyl 2-methylprop-2-enoate Chemical compound CC(=C)C(=O)OCCOC(=O)NCCC(C)CC(C)(C)CNC(=O)OCCOC(=O)C(C)=C UEKHZPDUBLCUHN-UHFFFAOYSA-N 0.000 description 7
- 238000013459 approach Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
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- 230000008901 benefit Effects 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
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- 102100034004 Gamma-adducin Human genes 0.000 description 2
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- 208000033748 Device issues Diseases 0.000 description 1
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- 238000003491 array Methods 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
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- 238000013500 data storage Methods 0.000 description 1
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- 230000037406 food intake Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Read Only Memory (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/379,910 US7345926B2 (en) | 2006-04-24 | 2006-04-24 | High-performance flash memory data transfer |
| US11/379,895 US7366028B2 (en) | 2006-04-24 | 2006-04-24 | Method of high-performance flash memory data transfer |
| US11/424,581 US7366029B2 (en) | 2006-04-24 | 2006-06-16 | High-performance flash memory data transfer |
| US11/424,573 US7525855B2 (en) | 2006-04-24 | 2006-06-16 | Method of high-performance flash memory data transfer |
| US11/458,431 US7499339B2 (en) | 2006-07-19 | 2006-07-19 | High-performance flash memory data transfer |
| US11/458,422 US7499369B2 (en) | 2006-07-19 | 2006-07-19 | Method of high-performance flash memory data transfer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200818206A TW200818206A (en) | 2008-04-16 |
| TWI486964B true TWI486964B (zh) | 2015-06-01 |
Family
ID=38627002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096114457A TWI486964B (zh) | 2006-04-24 | 2007-04-24 | 高效能快閃記憶體資料傳送方法及裝置 |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP2011122A2 (enExample) |
| JP (1) | JP5226669B2 (enExample) |
| KR (1) | KR101458381B1 (enExample) |
| CN (1) | CN101479804B (enExample) |
| TW (1) | TWI486964B (enExample) |
| WO (1) | WO2007127678A2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5106219B2 (ja) | 2008-03-19 | 2012-12-26 | 株式会社東芝 | メモリデバイス、ホストデバイス、メモリシステム、メモリデバイスの制御方法、ホストデバイスの制御方法、およびメモリシステムの制御方法 |
| KR101087195B1 (ko) * | 2008-05-26 | 2011-11-29 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치 |
| US8677056B2 (en) | 2008-07-01 | 2014-03-18 | Lsi Corporation | Methods and apparatus for interfacing between a flash memory controller and a flash memory array |
| JP5266589B2 (ja) * | 2009-05-14 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置 |
| JP5449032B2 (ja) * | 2009-05-28 | 2014-03-19 | パナソニック株式会社 | メモリシステム |
| JP2011058847A (ja) * | 2009-09-07 | 2011-03-24 | Renesas Electronics Corp | 半導体集積回路装置 |
| EP3703055B1 (en) * | 2010-02-23 | 2022-03-16 | Rambus Inc. | Methods and circuits for dynamically scaling dram power and performance |
| US8422315B2 (en) * | 2010-07-06 | 2013-04-16 | Winbond Electronics Corp. | Memory chips and memory devices using the same |
| JP2012198965A (ja) * | 2011-03-22 | 2012-10-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US9053066B2 (en) | 2012-03-30 | 2015-06-09 | Sandisk Technologies Inc. | NAND flash memory interface |
| KR102130171B1 (ko) * | 2014-01-13 | 2020-07-03 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| US9385721B1 (en) | 2015-01-14 | 2016-07-05 | Sandisk Technologies Llc | Bulk driven low swing driver |
| US9792994B1 (en) | 2016-09-28 | 2017-10-17 | Sandisk Technologies Llc | Bulk modulation scheme to reduce I/O pin capacitance |
| JP6894459B2 (ja) * | 2019-02-25 | 2021-06-30 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | 疑似スタティックランダムアクセスメモリとその動作方法 |
| JP7714432B2 (ja) * | 2021-07-21 | 2025-07-29 | キオクシア株式会社 | 半導体記憶装置 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001067870A (ja) * | 1999-08-31 | 2001-03-16 | Hitachi Ltd | 半導体装置 |
| US20010046163A1 (en) * | 2000-05-19 | 2001-11-29 | Fujitsu Limited | Memory system and memory controller with reliable data latch operation |
| US6337832B1 (en) * | 1998-06-10 | 2002-01-08 | Mitsubishi Denki Kabushiki Kaisha | Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode |
| TWI228259B (en) * | 2000-05-22 | 2005-02-21 | Samsung Electronics Co Ltd | Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same |
| TW200522076A (en) * | 2003-12-30 | 2005-07-01 | Hynix Semiconductor Inc | Write circuit of double data rate synchronous dram |
| US6961269B2 (en) * | 2003-06-24 | 2005-11-01 | Micron Technology, Inc. | Memory device having data paths with multiple speeds |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5696917A (en) * | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
| KR100252057B1 (ko) * | 1997-12-30 | 2000-05-01 | 윤종용 | 단일 및 이중 데이터 율 겸용 반도체 메모리 장치 |
| JP2002007200A (ja) * | 2000-06-16 | 2002-01-11 | Nec Corp | メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体 |
| US7370168B2 (en) * | 2003-04-25 | 2008-05-06 | Renesas Technology Corp. | Memory card conforming to a multiple operation standards |
| DE102004026808B4 (de) * | 2004-06-02 | 2007-06-06 | Infineon Technologies Ag | Abwärtskompatibler Speicherbaustein |
| KR100546418B1 (ko) * | 2004-07-27 | 2006-01-26 | 삼성전자주식회사 | 데이터 출력시 ｄｄｒ 동작을 수행하는 비휘발성 메모리장치 및 데이터 출력 방법 |
-
2007
- 2007-04-20 JP JP2009507905A patent/JP5226669B2/ja active Active
- 2007-04-20 WO PCT/US2007/067090 patent/WO2007127678A2/en not_active Ceased
- 2007-04-20 KR KR1020087028524A patent/KR101458381B1/ko not_active Expired - Fee Related
- 2007-04-20 EP EP07761017A patent/EP2011122A2/en not_active Ceased
- 2007-04-20 CN CN200780019176XA patent/CN101479804B/zh active Active
- 2007-04-24 TW TW096114457A patent/TWI486964B/zh active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337832B1 (en) * | 1998-06-10 | 2002-01-08 | Mitsubishi Denki Kabushiki Kaisha | Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode |
| JP2001067870A (ja) * | 1999-08-31 | 2001-03-16 | Hitachi Ltd | 半導体装置 |
| US6335901B1 (en) * | 1999-08-31 | 2002-01-01 | Hitachi, Ltd. | Semiconductor device |
| US6754133B2 (en) * | 1999-08-31 | 2004-06-22 | Hitachi, Ltd. | Semiconductor device |
| US20010046163A1 (en) * | 2000-05-19 | 2001-11-29 | Fujitsu Limited | Memory system and memory controller with reliable data latch operation |
| TWI228259B (en) * | 2000-05-22 | 2005-02-21 | Samsung Electronics Co Ltd | Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same |
| US6961269B2 (en) * | 2003-06-24 | 2005-11-01 | Micron Technology, Inc. | Memory device having data paths with multiple speeds |
| TW200522076A (en) * | 2003-12-30 | 2005-07-01 | Hynix Semiconductor Inc | Write circuit of double data rate synchronous dram |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2011122A2 (en) | 2009-01-07 |
| CN101479804B (zh) | 2013-05-01 |
| KR20090026267A (ko) | 2009-03-12 |
| TW200818206A (en) | 2008-04-16 |
| JP5226669B2 (ja) | 2013-07-03 |
| KR101458381B1 (ko) | 2014-11-07 |
| CN101479804A (zh) | 2009-07-08 |
| WO2007127678A2 (en) | 2007-11-08 |
| JP2009534785A (ja) | 2009-09-24 |
| WO2007127678A3 (en) | 2008-02-07 |
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