WO2007127678A3 - High-performance flash memory data transfer - Google Patents

High-performance flash memory data transfer Download PDF

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Publication number
WO2007127678A3
WO2007127678A3 PCT/US2007/067090 US2007067090W WO2007127678A3 WO 2007127678 A3 WO2007127678 A3 WO 2007127678A3 US 2007067090 W US2007067090 W US 2007067090W WO 2007127678 A3 WO2007127678 A3 WO 2007127678A3
Authority
WO
WIPO (PCT)
Prior art keywords
controller
flash memory
data
mode
data transfer
Prior art date
Application number
PCT/US2007/067090
Other languages
French (fr)
Other versions
WO2007127678A2 (en
Inventor
Yishai Kagan
Rizwan Ahmed
Farookh Moogat
Jason Lin
Original Assignee
Sandisk Corp
Yishai Kagan
Rizwan Ahmed
Farookh Moogat
Jason Lin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/379,895 external-priority patent/US7366028B2/en
Priority claimed from US11/379,910 external-priority patent/US7345926B2/en
Priority claimed from US11/424,573 external-priority patent/US7525855B2/en
Priority claimed from US11/424,581 external-priority patent/US7366029B2/en
Priority claimed from US11/458,422 external-priority patent/US7499369B2/en
Priority claimed from US11/458,431 external-priority patent/US7499339B2/en
Priority to CN200780019176XA priority Critical patent/CN101479804B/en
Priority to KR1020087028524A priority patent/KR101458381B1/en
Application filed by Sandisk Corp, Yishai Kagan, Rizwan Ahmed, Farookh Moogat, Jason Lin filed Critical Sandisk Corp
Priority to JP2009507905A priority patent/JP5226669B2/en
Priority to EP07761017A priority patent/EP2011122A2/en
Publication of WO2007127678A2 publication Critical patent/WO2007127678A2/en
Publication of WO2007127678A3 publication Critical patent/WO2007127678A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Read Only Memory (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a 'legacy' mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, data is read at a higher frequency, for example at twice the frequency, of that available in the normal mode. In the advanced mode, the input data is presented by the controller at a higher frequency than is available in the normal mode. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.
PCT/US2007/067090 2006-04-24 2007-04-20 High-performance flash memory data transfer WO2007127678A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07761017A EP2011122A2 (en) 2006-04-24 2007-04-20 High-performance flash memory data transfer
JP2009507905A JP5226669B2 (en) 2006-04-24 2007-04-20 High-efficiency flash memory data transfer
CN200780019176XA CN101479804B (en) 2006-04-24 2007-04-20 High-performance flash memory data transfer
KR1020087028524A KR101458381B1 (en) 2006-04-24 2007-04-20 High-performance flash memory data transfer

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US11/379,895 US7366028B2 (en) 2006-04-24 2006-04-24 Method of high-performance flash memory data transfer
US11/379,910 2006-04-24
US11/379,895 2006-04-24
US11/379,910 US7345926B2 (en) 2006-04-24 2006-04-24 High-performance flash memory data transfer
US11/424,581 2006-06-16
US11/424,573 2006-06-16
US11/424,581 US7366029B2 (en) 2006-04-24 2006-06-16 High-performance flash memory data transfer
US11/424,573 US7525855B2 (en) 2006-04-24 2006-06-16 Method of high-performance flash memory data transfer
US11/458,422 2006-07-19
US11/458,431 US7499339B2 (en) 2006-07-19 2006-07-19 High-performance flash memory data transfer
US11/458,422 US7499369B2 (en) 2006-07-19 2006-07-19 Method of high-performance flash memory data transfer
US11/458,431 2006-07-19

Publications (2)

Publication Number Publication Date
WO2007127678A2 WO2007127678A2 (en) 2007-11-08
WO2007127678A3 true WO2007127678A3 (en) 2008-02-07

Family

ID=38627002

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/067090 WO2007127678A2 (en) 2006-04-24 2007-04-20 High-performance flash memory data transfer

Country Status (6)

Country Link
EP (1) EP2011122A2 (en)
JP (1) JP5226669B2 (en)
KR (1) KR101458381B1 (en)
CN (1) CN101479804B (en)
TW (1) TWI486964B (en)
WO (1) WO2007127678A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5106219B2 (en) 2008-03-19 2012-12-26 株式会社東芝 Memory device, host device, memory system, memory device control method, host device control method, and memory system control method
KR101087195B1 (en) * 2008-05-26 2011-11-29 주식회사 하이닉스반도체 Non volatile memory device
WO2010002943A1 (en) 2008-07-01 2010-01-07 Lsi Corporation Methods and apparatus for interfacing between a flash memory controller and a flash memory array
JP5266589B2 (en) * 2009-05-14 2013-08-21 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device
JP5449032B2 (en) * 2009-05-28 2014-03-19 パナソニック株式会社 Memory system
JP2011058847A (en) * 2009-09-07 2011-03-24 Renesas Electronics Corp Semiconductor integrated circuit device
EP4053840A1 (en) * 2010-02-23 2022-09-07 Rambus Inc. Methods and circuits for dynamically scaling dram power and performance
US8422315B2 (en) * 2010-07-06 2013-04-16 Winbond Electronics Corp. Memory chips and memory devices using the same
JP2012198965A (en) * 2011-03-22 2012-10-18 Toshiba Corp Nonvolatile semiconductor storage device
US9053066B2 (en) 2012-03-30 2015-06-09 Sandisk Technologies Inc. NAND flash memory interface
KR102130171B1 (en) * 2014-01-13 2020-07-03 에스케이하이닉스 주식회사 Semiconductor device and semiconductor system
US9385721B1 (en) 2015-01-14 2016-07-05 Sandisk Technologies Llc Bulk driven low swing driver
US9792994B1 (en) 2016-09-28 2017-10-17 Sandisk Technologies Llc Bulk modulation scheme to reduce I/O pin capacitance
JP6894459B2 (en) * 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． Pseudo-static random access memory and how it works

Citations (5)

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Publication number Priority date Publication date Assignee Title
WO1995034030A2 (en) * 1994-06-03 1995-12-14 Intel Corporation Flash memory based main memory
US6094375A (en) * 1997-12-30 2000-07-25 Samsung Electronics Co., Ltd. Integrated circuit memory devices having multiple data rate mode capability and methods of operating same
US6335901B1 (en) * 1999-08-31 2002-01-01 Hitachi, Ltd. Semiconductor device
US20040215996A1 (en) * 2003-04-25 2004-10-28 Renesas Technology Corp. Memory card
US20050270891A1 (en) * 2004-06-02 2005-12-08 Bjorn Flach Backwards-compatible memory module

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000067577A (en) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp Synchronous semiconductor memory
US6466491B2 (en) * 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
TWI228259B (en) * 2000-05-22 2005-02-21 Samsung Electronics Co Ltd Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same
JP2002007200A (en) * 2000-06-16 2002-01-11 Nec Corp Memory controller and operation switching method and interface device and semiconductor integrated chip and recording medium
US6961269B2 (en) * 2003-06-24 2005-11-01 Micron Technology, Inc. Memory device having data paths with multiple speeds
KR100521049B1 (en) * 2003-12-30 2005-10-11 주식회사 하이닉스반도체 Write circuit of the Double Data Rate Synchronous DRAM
KR100546418B1 (en) * 2004-07-27 2006-01-26 삼성전자주식회사 Non-volatile memory device performing double data rate operation in reading operation and method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995034030A2 (en) * 1994-06-03 1995-12-14 Intel Corporation Flash memory based main memory
US6094375A (en) * 1997-12-30 2000-07-25 Samsung Electronics Co., Ltd. Integrated circuit memory devices having multiple data rate mode capability and methods of operating same
US6335901B1 (en) * 1999-08-31 2002-01-01 Hitachi, Ltd. Semiconductor device
US20040215996A1 (en) * 2003-04-25 2004-10-28 Renesas Technology Corp. Memory card
US20050270891A1 (en) * 2004-06-02 2005-12-08 Bjorn Flach Backwards-compatible memory module

Also Published As

Publication number Publication date
KR20090026267A (en) 2009-03-12
EP2011122A2 (en) 2009-01-07
TW200818206A (en) 2008-04-16
CN101479804A (en) 2009-07-08
JP2009534785A (en) 2009-09-24
JP5226669B2 (en) 2013-07-03
WO2007127678A2 (en) 2007-11-08
KR101458381B1 (en) 2014-11-07
TWI486964B (en) 2015-06-01
CN101479804B (en) 2013-05-01

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